Running out of ideas: stability, bootstrap

On 2017-05-28 13:09, Gerhard Hoffmann wrote:
> Am 28.05.2017 um 18:46 schrieb John Larkin:
>
>>
>> Over what frequency range is the Zin negative?
>
> The network analyzer starts officially at 300 KHz,
> non-guaranteed at 150KHz. At 150 KHz Zin is already
> negative. It seems, at about 10 MHz everything is
> running out of steam, so it stops being offensive.
>
> Every impedance inside the circle that goes through 0
> has a positive real part. Everything on the circle
> through 0 has zero Ohms, only LC.
> Everything outside of that circle has a negative
> real part.
> The Smith diagram is in the same photo album.
>
> There are no complaints by LTspice.
> In a very old version of Genesys, I get about the same
> behavior regarding Zin. But I could not make the
> bias loop converge, so setting the operating point
> is clumsy.
>
>
>> Where does GATE_BIAS come from?
>
> That comes from an integrator. I have added that
> part of the circuit. Since the 30uF input capacitance
> * 66Meg bias resistor takes an eternity to settle,
> I have added a window comparator & analog switch to
> reduce the bias resistor by paralleling 4Meg7.
> That works.
>
>>
>> How is this physically assembled?
>
> It is all on a small dual-sided circuit board.
> Pic included. It does no longer look that tidy.  :-)
>
> < https://www.flickr.com/photos/137684711@N07/albums/72157682404684680 >
>
> and the pics left/right of it.
>

The 17.6pF cap could perform better if it had a flag in the Borussia 
Dortmund colors black and yellow :-)

Just curious, shouldn't there be a cap to ground at the base of Q3 and 
maybe also Q2?

-- 
Regards, Joerg

http://www.analogconsultants.com/

Gerhard Hoffmann wrote...
>
> Some observations:
>
>- Zin is negative also with the feedback loop cut

 I think you could safely add a little resistance
 in Q3's emitter.  BTW, while studying the Zin
 scene, you can make changes that would damage
 the noise performance, just saying.


-- 
 Thanks,
    - Win

On 05/29/2017 10:36 AM, Winfield Hill wrote:
> Gerhard Hoffmann wrote...
>>
>> Some observations:
>>
>> - Zin is negative also with the feedback loop cut
> 
>   I think you could safely add a little resistance
>   in Q3's emitter.  BTW, while studying the Zin
>   scene, you can make changes that would damage
>   the noise performance, just saying.
> 
> 

If you have a chance could you confirm and/or deny that there might be a 
problem with the feedback connection from Q3's collector to U1A? It 
looks that way to me or else I'm not understanding correctly how this 
circuit is supposed to work, which is entirely possible given it's still 
before noon ;-)

On a sunny day (Mon, 29 May 2017 11:20:44 -0400) it happened bitrex
<bitrex@de.lete.earthlink.net> wrote in <g%WWA.109122$Qg.95262@fx14.iad>:

>On 05/29/2017 10:36 AM, Winfield Hill wrote:
>> Gerhard Hoffmann wrote...
>>>
>>> Some observations:
>>>
>>> - Zin is negative also with the feedback loop cut
>> 
>>   I think you could safely add a little resistance
>>   in Q3's emitter.  BTW, while studying the Zin
>>   scene, you can make changes that would damage
>>   the noise performance, just saying.
>> 
>> 
>
>If you have a chance could you confirm and/or deny that there might be a 
>problem with the feedback connection from Q3's collector to U1A? It 
>looks that way to me or else I'm not understanding correctly how this 
>circuit is supposed to work, which is entirely possible given it's still 
>before noon ;-)

I looked at it twice and declined to comment as I 
1) have no idea what it does.
2) have no idea what it is supposed to do.
3) have no idea why make a peeseebee for something that one has not tested.
4) looks overly complicatiaotiantiated to me, brain abort.

On 05/29/2017 11:36 AM, Jan Panteltje wrote:

> I looked at it twice and declined to comment as I
> 1) have no idea what it does.
> 2) have no idea what it is supposed to do.
> 3) have no idea why make a peeseebee for something that one has not tested.
> 4) looks overly complicatiaotiantiated to me, brain abort.
> 

Yeah, this is why I don't feel too bad if my suggestion wasn't on the mark.

I know I'm guilty of this myself sometimes, but while people are very 
familiar with their own designs I don't think everyone else can 
immediately intuit what's going on in a circuit that has say, more than 
a couple transistors or op amps. A few sentences of explanation of 
what's _supposed_ to happen would help OP a lot before jumping right 
into what the problems are with...whatever it is.

My impression was that it's a cascode source follower with U1A acting as 
a post amplifier, then feeding an integrator which then feeds the FET 
gate resistor. Holding the collector of the top cascode transistor at 
virtual ground by tying it to the op amp inverting input is clever, but 
it also seems sketchy as the only way U1A has to hold it there is around 
the loop to the FET gate. Transimpedance amp-connected op amp -> 
integrator is at least 270 degrees of phase shift at high frequency 
right off the bat. Seems sketch.

Jan Panteltje wrote...
>
>4) looks overly complicatiaotiantiated to me, brain abort.

 Bleep! Bleep!  Jan Panteltje brain abort!  Bleep!


-- 
 Thanks,
    - Win

On 05/29/2017 11:44 AM, bitrex wrote:
> On 05/29/2017 11:36 AM, Jan Panteltje wrote:
> 
>> I looked at it twice and declined to comment as I
>> 1) have no idea what it does.
>> 2) have no idea what it is supposed to do.
>> 3) have no idea why make a peeseebee for something that one has not 
>> tested.
>> 4) looks overly complicatiaotiantiated to me, brain abort.
>>
> 
> Yeah, this is why I don't feel too bad if my suggestion wasn't on the mark.
> 
> I know I'm guilty of this myself sometimes, but while people are very 
> familiar with their own designs I don't think everyone else can 
> immediately intuit what's going on in a circuit that has say, more than 
> a couple transistors or op amps. A few sentences of explanation of 
> what's _supposed_ to happen would help OP a lot before jumping right 
> into what the problems are with...whatever it is.
> 
> My impression was that it's a cascode source follower with U1A acting as 
> a post amplifier, then feeding an integrator which then feeds the FET 
> gate resistor. Holding the collector of the top cascode transistor at 
> virtual ground by tying it to the op amp inverting input is clever, but 
> it also seems sketchy as the only way U1A has to hold it there is around 
> the loop to the FET gate. Transimpedance amp-connected op amp -> 
> integrator is at least 270 degrees of phase shift at high frequency 
> right off the bat. Seems sketch.

Unless one is willing to grunge through all the math to make sure 
everything works out then IMO feedback loops around stuff need to be 
super-tight and encompass the bare minimum of stages. Just wrapping 
stuff around stuff and assuming it will all work out because the ideal 
op amp equations say this voltage must be equal to this voltage in a 
negative feedback configuration is asking for trouble - even if the 
feedback loop is only "designed" to operate at DC.

On a sunny day (29 May 2017 08:46:13 -0700) it happened Winfield Hill
<hill@rowland.harvard.edu> wrote in <oghfo5012sr@drn.newsguy.com>:

>Jan Panteltje wrote...
>>
>>4) looks overly complicatiaotiantiated to me, brain abort.
>
> Bleep! Bleep!  Jan Panteltje brain abort!  Bleep!

The real Art is Simple City, ehh simplicity.
:-)

On a sunny day (Mon, 29 May 2017 11:44:20 -0400) it happened bitrex
<bitrex@de.lete.earthlink.net> wrote in <olXWA.100487$df3.20124@fx30.iad>:

>On 05/29/2017 11:36 AM, Jan Panteltje wrote:
>
>> I looked at it twice and declined to comment as I
>> 1) have no idea what it does.
>> 2) have no idea what it is supposed to do.
>> 3) have no idea why make a peeseebee for something that one has not tested.
>> 4) looks overly complicatiaotiantiated to me, brain abort.
>> 
>
>Yeah, this is why I don't feel too bad if my suggestion wasn't on the mark.
>
>I know I'm guilty of this myself sometimes, but while people are very 
>familiar with their own designs I don't think everyone else can 
>immediately intuit what's going on in a circuit that has say, more than 
>a couple transistors or op amps. A few sentences of explanation of 
>what's _supposed_ to happen would help OP a lot before jumping right 
>into what the problems are with...whatever it is.
>
>My impression was that it's a cascode source follower with U1A acting as 
>a post amplifier, then feeding an integrator which then feeds the FET 
>gate resistor. Holding the collector of the top cascode transistor at 
>virtual ground by tying it to the op amp inverting input is clever, but 
>it also seems sketchy as the only way U1A has to hold it there is around 
>the loop to the FET gate. Transimpedance amp-connected op amp -> 
>integrator is at least 270 degrees of phase shift at high frequency 
>right off the bat. Seems sketch.

Yes, and there is more we need to know, drive impedance, requirements,
I posted long ago here about my (accidently discovered) better alternative
vidicon preamp (better than the common bootstrap circuit).
It all depends...

On Monday, May 29, 2017 at 10:13:51 AM UTC-4, Joerg wrote:
> On 2017-05-28 13:09, Gerhard Hoffmann wrote:
> > Am 28.05.2017 um 18:46 schrieb John Larkin:
> >
> >>
> >> Over what frequency range is the Zin negative?
> >
> > The network analyzer starts officially at 300 KHz,
> > non-guaranteed at 150KHz. At 150 KHz Zin is already
> > negative. It seems, at about 10 MHz everything is
> > running out of steam, so it stops being offensive.
> >
> > Every impedance inside the circle that goes through 0
> > has a positive real part. Everything on the circle
> > through 0 has zero Ohms, only LC.
> > Everything outside of that circle has a negative
> > real part.
> > The Smith diagram is in the same photo album.
> >
> > There are no complaints by LTspice.
> > In a very old version of Genesys, I get about the same
> > behavior regarding Zin. But I could not make the
> > bias loop converge, so setting the operating point
> > is clumsy.
> >
> >
> >> Where does GATE_BIAS come from?
> >
> > That comes from an integrator. I have added that
> > part of the circuit. Since the 30uF input capacitance
> > * 66Meg bias resistor takes an eternity to settle,
> > I have added a window comparator & analog switch to
> > reduce the bias resistor by paralleling 4Meg7.
> > That works.
> >
> >>
> >> How is this physically assembled?
> >
> > It is all on a small dual-sided circuit board.
> > Pic included. It does no longer look that tidy.  :-)
> >
> > < https://www.flickr.com/photos/137684711@N07/albums/72157682404684680 >
> >
> > and the pics left/right of it.
> >
> 
> The 17.6pF cap could perform better if it had a flag in the Borussia 
> Dortmund colors black and yellow :-)
> 
> Just curious, shouldn't there be a cap to ground at the base of Q3 and 
> maybe also Q2?

+1 on Q3.  I'd suggest moving the aptly-named C666 to Q3's base.
Current-source Q2 is bypassed to +10V, so no problem there.

I don't trust 2.7V zeners or emitter-followers with big base resistors
here. Moving C666 should reveal whether this node is the source of the
weirdness.

Cheers,
James Arthur