On Tuesday, May 30, 2017 at 9:54:13 AM UTC-4, Gerhard Hoffmann wrote:
> Am 30.05.2017 um 12:55 schrieb Winfield Hill:
> > dagmargoodboat@yahoo.com wrote...
> >>
> >> I don't trust 2.7V zeners or emitter-followers with
> >> big base resistors here. Moving C666 should reveal
> >> whether this node is the source of the weirdness.
> >
> > Indeed. Zin for the cascode Q3 emitter is 100/beta
> > and beta = fT/f, which is 13 at 10MHz for FZT851, or
> > Zin = 7.7 ohms at 10MHz, rising with f, acting as
> > nasty 207nH inductor. Not to mention a 1.3nV.rt-Hz
> > voltage-noise source. Axe that 100 ohms.
>
> Yes, the 100R are just there to check the sensitivity.
> The bad thing is that even for a zero Ohm resistor, the
> S11 comes only a bit closer to the circle that
> encloses the positive resistance region, but it still
> takes a walk outside.
>
> But I need at least a few Ohms so I can insert the
> buffered input voltage for the bootstrap.
Thanks for the details. In your original post, you wrote:
"That was not so funny because it features a negative
input impedance over most frequencies, so with
a suitable inductance on the input it makes a stable
oscillator."
If putting an inductor on the input makes an oscillator, this
can only mean that energy is being fed from the output back to
the input.
The two obvious paths for that are Cdg and Cgs.
You seem to have eliminated Cdg as a cause, by your report
that the negative resistance is relatively insensitive to
the cascode's base resistance.
Logically, this points suspicion at Cgs, a positive-feedback
capacitance famous for making BJTs into oscillators.
I'd suspect your feedback loop, injecting energy into the FET array's
source that couples through to its gate, except you've already reported
that the problem persists even with the feedback loop disabled.
This leaves the FETs themselves.
You could also test the possibility that Cgs feedthrough is the cause,
by temporarily lowering the operating current and disconnecting most
of the JFET array.
If 4 x Cgs is a problem, 1 x Cgs should be one-fourth as bad.
If you can identify the source of the problem, you'll be able
to devise a correction for it. (E.g., if this were r.f.,
neutralization.)
The frequency of oscillation for an input inductor L might give a
hint as to the value of any capacitance at play here.
Cheers,
James Arthur
Reply by Gerhard Hoffmann●May 30, 20172017-05-30
Am 29.05.2017 um 14:38 schrieb bitrex:
> I'm assuming the goal here is to build a low-noise source follower, with
> the output buffered by an op amp.
No, a very low noise amplifier with 60 dB gain, 100 mHz to 1 MHz.
I'm aiming for 100pV/rtHz at least on the sweet spot.
> It looks like the non-inverting input of U1A is tied to a virtual
> ground, and the inverting input is tied to the collector of Q3, I'm
> guessing to try to use negative feedback to fix the collector voltage at
> 4.57. But since Q3 is fed by current source Q2, the collector of Q3
> (test point P3) is a high-impedance node and so it seems to me that the > only way the DC voltage there can be controlled is by U1A sensing the
> source voltage of the FET, through the R17/R23 network, and then around
> the loop through the integrator (not shown) back to the gate of the FET,
> if I'm understanding the circuit correctly.
The current source defines the bias current and the FET's gate voltage
is adjusted by an integrator until the cascode collector equals the
level of CENTER.
> The gain from the gate of the cascoded FET to the output of U1A isn't
> well-defined; from "its perspective" it looks like a current source
> loaded common-emitter amplifier feeding a transimpedance converter. It
> will be very large. Plus the phase shift from U1A and the integrator to
> the gate it sounds like a recipe for oscillation.
The signal gain from the gate to the output of U1A is determined by
the gm of the FET array, which _is_ large and by the transimpedance
amplifier. (assuming open loop)
The current source and the cascode transistor do not enter the
equation other than second order effects like the ccs diverting
some signal current or that the BJT has probably a much higher
Early voltage and thus higher output impedance.
The integrator is also not in the signal path. It is as slow
as molasse. It takes a minute until the window comparator
thinks that the operating point has been reached. There may
be some influence in the mHz region, but I have no problem there.
> If I were dead-set on using a current source for the cascode collector
> load I think it would be better to let one op-amp section handle a
> feedback loop around the upper current source to set the DC bias at Q3's
> collector, and let U1A and the integrator just handle setting the FET's
> bias and the 0V DC level to the post amplifier. Delegate some
> responsibility...
The current source is necessary to suppress the noise on VCC; without it
it takes a supply better than 2nV/rtHz (for 8 FETs and twice the
current). There also must be 5 diodes in series or the noise of
the current source emitter resistor starts playing a role.
Gerhard
who got a 54754A differential TDR plug in this morning, still a month
under service. That needs to be played with now. :-) :-)
Reply by Gerhard Hoffmann●May 30, 20172017-05-30
Am 30.05.2017 um 12:55 schrieb Winfield Hill:
> dagmargoodboat@yahoo.com wrote...
>>
>> I don't trust 2.7V zeners or emitter-followers with
>> big base resistors here. Moving C666 should reveal
>> whether this node is the source of the weirdness.
>
> Indeed. Zin for the cascode Q3 emitter is 100/beta
> and beta = fT/f, which is 13 at 10MHz for FZT851, or
> Zin = 7.7 ohms at 10MHz, rising with f, acting as
> nasty 207nH inductor. Not to mention a 1.3nV.rt-Hz
> voltage-noise source. Axe that 100 ohms.
Yes, the 100R are just there to check the sensitivity.
The bad thing is that even for a zero Ohm resistor, the
S11 comes only a bit closer to the circle that
encloses the positive resistance region, but it still
takes a walk outside.
But I need at least a few Ohms so I can insert the
buffered input voltage for the bootstrap.
The entire bias chain has no impact on the total noise,
even including the Zener and with absolutely minimum
decoupling.
Here is a stripped down version in LTspice:
screendump:
<
https://www.flickr.com/photos/137684711@N07/34987159135/in/album-72157682404684680/
>
noise results, including some contributors:
<https://www.flickr.com/photos/137684711@N07/34823792822/in/album-72157682404684680/
>
It seems that above 1 MHz, the active loads quickly becomes ineffective
in suppressing the VCC noise. But 1 MHz BW is enough.
regards, Gerhard
---- >% ---- >% ---- >% ---- >% ---- >% ---- >% ---- >% ---- >%
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Reply by Winfield Hill●May 30, 20172017-05-30
dagmargoodboat@yahoo.com wrote...
>
> I don't trust 2.7V zeners or emitter-followers with
> big base resistors here. Moving C666 should reveal
> whether this node is the source of the weirdness.
Indeed. Zin for the cascode Q3 emitter is 100/beta
and beta = fT/f, which is 13 at 10MHz for FZT851, or
Zin = 7.7 ohms at 10MHz, rising with f, acting as
nasty 207nH inductor. Not to mention a 1.3nV.rt-Hz
voltage-noise source. Axe that 100 ohms.
--
Thanks,
- Win
Reply by ●May 30, 20172017-05-30
On Monday, May 29, 2017 at 11:20:49 AM UTC-4, bitrex wrote:
> On 05/29/2017 10:36 AM, Winfield Hill wrote:
> > Gerhard Hoffmann wrote...
> >>
> >> Some observations:
> >>
> >> - Zin is negative also with the feedback loop cut
> >
> > I think you could safely add a little resistance
> > in Q3's emitter. BTW, while studying the Zin
> > scene, you can make changes that would damage
> > the noise performance, just saying.
> >
> >
>
> If you have a chance could you confirm and/or deny that there might be a
> problem with the feedback connection from Q3's collector to U1A? It
> looks that way to me or else I'm not understanding correctly how this
> circuit is supposed to work, which is entirely possible given it's still
> before noon ;-)
Q2 is a current-source load.
U1A keeps the FET current constant by feeding back cascode Q3's collector
node, producing the output voltage in the process (not shown).
G = R20/R(drain) = 1,000 if I'm not mistaken. That's rather ambitious
for one stage.
Weirdness at Q3's base will affect the loop, & has to be ruled out. Q3
might also oscillate. I don't see that it should, but sometimes weird
things happen (e.g., negative input impedance).
Cheers,
James Arthur
Reply by ●May 30, 20172017-05-30
On Monday, May 29, 2017 at 10:13:51 AM UTC-4, Joerg wrote:
> On 2017-05-28 13:09, Gerhard Hoffmann wrote:
> > Am 28.05.2017 um 18:46 schrieb John Larkin:
> >
> >>
> >> Over what frequency range is the Zin negative?
> >
> > The network analyzer starts officially at 300 KHz,
> > non-guaranteed at 150KHz. At 150 KHz Zin is already
> > negative. It seems, at about 10 MHz everything is
> > running out of steam, so it stops being offensive.
> >
> > Every impedance inside the circle that goes through 0
> > has a positive real part. Everything on the circle
> > through 0 has zero Ohms, only LC.
> > Everything outside of that circle has a negative
> > real part.
> > The Smith diagram is in the same photo album.
> >
> > There are no complaints by LTspice.
> > In a very old version of Genesys, I get about the same
> > behavior regarding Zin. But I could not make the
> > bias loop converge, so setting the operating point
> > is clumsy.
> >
> >
> >> Where does GATE_BIAS come from?
> >
> > That comes from an integrator. I have added that
> > part of the circuit. Since the 30uF input capacitance
> > * 66Meg bias resistor takes an eternity to settle,
> > I have added a window comparator & analog switch to
> > reduce the bias resistor by paralleling 4Meg7.
> > That works.
> >
> >>
> >> How is this physically assembled?
> >
> > It is all on a small dual-sided circuit board.
> > Pic included. It does no longer look that tidy. :-)
> >
> > < https://www.flickr.com/photos/137684711@N07/albums/72157682404684680 >
> >
> > and the pics left/right of it.
> >
>
> The 17.6pF cap could perform better if it had a flag in the Borussia
> Dortmund colors black and yellow :-)
>
> Just curious, shouldn't there be a cap to ground at the base of Q3 and
> maybe also Q2?
+1 on Q3. I'd suggest moving the aptly-named C666 to Q3's base.
Current-source Q2 is bypassed to +10V, so no problem there.
I don't trust 2.7V zeners or emitter-followers with big base resistors
here. Moving C666 should reveal whether this node is the source of the
weirdness.
Cheers,
James Arthur
Reply by Jan Panteltje●May 29, 20172017-05-29
On a sunny day (Mon, 29 May 2017 11:44:20 -0400) it happened bitrex
<bitrex@de.lete.earthlink.net> wrote in <olXWA.100487$df3.20124@fx30.iad>:
>On 05/29/2017 11:36 AM, Jan Panteltje wrote:
>
>> I looked at it twice and declined to comment as I
>> 1) have no idea what it does.
>> 2) have no idea what it is supposed to do.
>> 3) have no idea why make a peeseebee for something that one has not tested.
>> 4) looks overly complicatiaotiantiated to me, brain abort.
>>
>
>Yeah, this is why I don't feel too bad if my suggestion wasn't on the mark.
>
>I know I'm guilty of this myself sometimes, but while people are very
>familiar with their own designs I don't think everyone else can
>immediately intuit what's going on in a circuit that has say, more than
>a couple transistors or op amps. A few sentences of explanation of
>what's _supposed_ to happen would help OP a lot before jumping right
>into what the problems are with...whatever it is.
>
>My impression was that it's a cascode source follower with U1A acting as
>a post amplifier, then feeding an integrator which then feeds the FET
>gate resistor. Holding the collector of the top cascode transistor at
>virtual ground by tying it to the op amp inverting input is clever, but
>it also seems sketchy as the only way U1A has to hold it there is around
>the loop to the FET gate. Transimpedance amp-connected op amp ->
>integrator is at least 270 degrees of phase shift at high frequency
>right off the bat. Seems sketch.
Yes, and there is more we need to know, drive impedance, requirements,
I posted long ago here about my (accidently discovered) better alternative
vidicon preamp (better than the common bootstrap circuit).
It all depends...
Reply by Jan Panteltje●May 29, 20172017-05-29
On a sunny day (29 May 2017 08:46:13 -0700) it happened Winfield Hill
<hill@rowland.harvard.edu> wrote in <oghfo5012sr@drn.newsguy.com>:
> On 05/29/2017 11:36 AM, Jan Panteltje wrote:
>
>> I looked at it twice and declined to comment as I
>> 1) have no idea what it does.
>> 2) have no idea what it is supposed to do.
>> 3) have no idea why make a peeseebee for something that one has not
>> tested.
>> 4) looks overly complicatiaotiantiated to me, brain abort.
>>
>
> Yeah, this is why I don't feel too bad if my suggestion wasn't on the mark.
>
> I know I'm guilty of this myself sometimes, but while people are very
> familiar with their own designs I don't think everyone else can
> immediately intuit what's going on in a circuit that has say, more than
> a couple transistors or op amps. A few sentences of explanation of
> what's _supposed_ to happen would help OP a lot before jumping right
> into what the problems are with...whatever it is.
>
> My impression was that it's a cascode source follower with U1A acting as
> a post amplifier, then feeding an integrator which then feeds the FET
> gate resistor. Holding the collector of the top cascode transistor at
> virtual ground by tying it to the op amp inverting input is clever, but
> it also seems sketchy as the only way U1A has to hold it there is around
> the loop to the FET gate. Transimpedance amp-connected op amp ->
> integrator is at least 270 degrees of phase shift at high frequency
> right off the bat. Seems sketch.
Unless one is willing to grunge through all the math to make sure
everything works out then IMO feedback loops around stuff need to be
super-tight and encompass the bare minimum of stages. Just wrapping
stuff around stuff and assuming it will all work out because the ideal
op amp equations say this voltage must be equal to this voltage in a
negative feedback configuration is asking for trouble - even if the
feedback loop is only "designed" to operate at DC.
Reply by Winfield Hill●May 29, 20172017-05-29
Jan Panteltje wrote...
>
>4) looks overly complicatiaotiantiated to me, brain abort.