Forums

Ultra-low power switching boost converter - in a DIP

Started by Peabody August 21, 2016
Den tirsdag den 23. august 2016 kl. 21.41.04 UTC+2 skrev rickman:
> On 8/23/2016 3:36 PM, Lasse Langwadt Christensen wrote: > > Den tirsdag den 23. august 2016 kl. 20.47.52 UTC+2 skrev rickman: > >> On 8/23/2016 8:46 AM, Tim Williams wrote: > >>> "rickman" <gnuarm@gmail.com> wrote in message > >>> news:npg0f3$7s1$6@dont-email.me... > >>>>> Do they make QFN adapters? There's a post-it on my door that says NO > >>>>> QFNS. Everybody hates them. > >>>> > >>>> Yeah, those who aren't very good at manufacturing don't like them. > >>>> That's why I'd never consider building my own assembly line. Contract > >>>> manufacturers don't seem to have any problem with them... or the big > >>>> builders who have to save every penny they can, like in cell phones, > >>>> etc. QFNs are very common and very useful. > >>> > >>> I love QFNs! Good thermal performance, smaller than QFP and more > >>> reliable, and impossible to short between pins (which was interesting as > >>> I had some rework recently where I had to add a short between pins..). > >> > >> For the most part, QFNs are just QFP packages with the leads cut off. I > >> suppose there are some smaller pin count packages which have not > >> corresponding QFPs and they can be uniquely small. But a 100 pin QFN > >> has the same body size as a 100 pin QFP. I have seen QFNs with multiple > >> rows of pads, but technically, I believe they become LGAs, no? > >> > >> > >>> What I don't like is the MCUs that invariably have pins coming out every > >>> which way. MSP430s do it. STM32s do it. The hell is up with that? Why > >>> would 32 bits of bus end up jumled!? It literally takes as much PCB > >>> space to rout such a QFN, as the QFP takes up! (The QFP would still be > >>> worse, though routing underneath is easier at least, not needing to > >>> allow for a ground pad.) > >> > >> Not sure what you mean, "every which way". Are you talking about pads > >> on all surfaces like a porcupine? The QFN parts I have seen were still > >> all planer. > >> > > > > I suspect he means that pins that would naturally be grouped together, like > > a data bus are spread out in a seemly random fashion, so to route a memory > > bus you need to get to all four sides of the chip and swap the order on the way > > Why would that be any different from any other package? The order of > pins on the package is usually the same or close to the order of pins on > the die.
not really any different, it's just that the idea of a small package is somewhat lost if the area you gain is just lost in routing and vias -Lasse
On 8/23/2016 4:19 PM, Lasse Langwadt Christensen wrote:
> Den tirsdag den 23. august 2016 kl. 21.41.04 UTC+2 skrev rickman: >> On 8/23/2016 3:36 PM, Lasse Langwadt Christensen wrote: >>> Den tirsdag den 23. august 2016 kl. 20.47.52 UTC+2 skrev rickman: >>>> On 8/23/2016 8:46 AM, Tim Williams wrote: >>>>> "rickman" <gnuarm@gmail.com> wrote in message >>>>> news:npg0f3$7s1$6@dont-email.me... >>>>>>> Do they make QFN adapters? There's a post-it on my door that says NO >>>>>>> QFNS. Everybody hates them. >>>>>> >>>>>> Yeah, those who aren't very good at manufacturing don't like them. >>>>>> That's why I'd never consider building my own assembly line. Contract >>>>>> manufacturers don't seem to have any problem with them... or the big >>>>>> builders who have to save every penny they can, like in cell phones, >>>>>> etc. QFNs are very common and very useful. >>>>> >>>>> I love QFNs! Good thermal performance, smaller than QFP and more >>>>> reliable, and impossible to short between pins (which was interesting as >>>>> I had some rework recently where I had to add a short between pins..). >>>> >>>> For the most part, QFNs are just QFP packages with the leads cut off. I >>>> suppose there are some smaller pin count packages which have not >>>> corresponding QFPs and they can be uniquely small. But a 100 pin QFN >>>> has the same body size as a 100 pin QFP. I have seen QFNs with multiple >>>> rows of pads, but technically, I believe they become LGAs, no? >>>> >>>> >>>>> What I don't like is the MCUs that invariably have pins coming out every >>>>> which way. MSP430s do it. STM32s do it. The hell is up with that? Why >>>>> would 32 bits of bus end up jumled!? It literally takes as much PCB >>>>> space to rout such a QFN, as the QFP takes up! (The QFP would still be >>>>> worse, though routing underneath is easier at least, not needing to >>>>> allow for a ground pad.) >>>> >>>> Not sure what you mean, "every which way". Are you talking about pads >>>> on all surfaces like a porcupine? The QFN parts I have seen were still >>>> all planer. >>>> >>> >>> I suspect he means that pins that would naturally be grouped together, like >>> a data bus are spread out in a seemly random fashion, so to route a memory >>> bus you need to get to all four sides of the chip and swap the order on the way >> >> Why would that be any different from any other package? The order of >> pins on the package is usually the same or close to the order of pins on >> the die. > > not really any different, it's just that the idea of a small package is > somewhat lost if the area you gain is just lost in routing and vias
Yes, to some extent. But real estate can be reclaimed by using smaller PCB features and adding layers. In some cases, size is more important that cost, so it's ok to transfer some cost to the PCB even if it ends up being more in total. -- Rick C
"rickman" <gnuarm@gmail.com> wrote in message 
news:npi5oj$m5j$1@dont-email.me...
> For the most part, QFNs are just QFP packages with the leads cut off. I > suppose there are some smaller pin count packages which have not > corresponding QFPs and they can be uniquely small. But a 100 pin QFN has > the same body size as a 100 pin QFP. I have seen QFNs with multiple rows > of pads, but technically, I believe they become LGAs, no?
Right, and the lead lengths plus pad toe length, plus tolerances, takes up a good 4mm or so around it. You can use that for routing instead. I kind of suspect QFPs are easier to route anyway, as there's no pad in the middle (usually) that ties up all layers, grounding it. You have very little room to do that under a QFN, so you end up using the pin+pad area for routing instead.
> Not sure what you mean, "every which way". Are you talking about pads on > all surfaces like a porcupine? The QFN parts I have seen were still all > planer.
As Lasse noted, I mean the pinout of GPIO ports and buses. Even SCK, MISO and MOSI end up jumbled! How the hell? One plus about ATmegas is their pinouts are always nice. Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
On Tue, 23 Aug 2016 14:47:49 -0400, rickman <gnuarm@gmail.com> wrote:

>On 8/23/2016 8:46 AM, Tim Williams wrote: >> "rickman" <gnuarm@gmail.com> wrote in message >> news:npg0f3$7s1$6@dont-email.me... >>>> Do they make QFN adapters? There's a post-it on my door that says NO >>>> QFNS. Everybody hates them. >>> >>> Yeah, those who aren't very good at manufacturing don't like them. >>> That's why I'd never consider building my own assembly line. Contract >>> manufacturers don't seem to have any problem with them... or the big >>> builders who have to save every penny they can, like in cell phones, >>> etc. QFNs are very common and very useful. >> >> I love QFNs! Good thermal performance, smaller than QFP and more >> reliable, and impossible to short between pins (which was interesting as >> I had some rework recently where I had to add a short between pins..). > >For the most part, QFNs are just QFP packages with the leads cut off.
Bullshit. They're completely different packages.
On 8/23/2016 7:14 PM, Tim Williams wrote:
> "rickman" <gnuarm@gmail.com> wrote in message > news:npi5oj$m5j$1@dont-email.me... >> For the most part, QFNs are just QFP packages with the leads cut off. >> I suppose there are some smaller pin count packages which have not >> corresponding QFPs and they can be uniquely small. But a 100 pin QFN >> has the same body size as a 100 pin QFP. I have seen QFNs with >> multiple rows of pads, but technically, I believe they become LGAs, no? > > Right, and the lead lengths plus pad toe length, plus tolerances, takes > up a good 4mm or so around it. > > You can use that for routing instead.
QFNs have pads and toe lengths and tolerances as well. I believe the difference ends up being 2 mm which is the extent of the leads on the QFP. So for smaller devices this can be appreciable but much less an issue with larger packages like a 48 or 64 pin device.
> I kind of suspect QFPs are easier to route anyway, as there's no pad in > the middle (usually) that ties up all layers, grounding it. You have > very little room to do that under a QFN, so you end up using the pin+pad > area for routing instead.
Or worse. My typical designs have very limited space and the loss of room for vias is a problem with QFNs. I like them, but mostly for smaller parts like 20 pin parts. I like BGAs a lot less. Mostly they require finer pitch lines and spaces as well as micro vias driving up the cost of the PCB.
>> Not sure what you mean, "every which way". Are you talking about pads >> on all surfaces like a porcupine? The QFN parts I have seen were >> still all planer. > > As Lasse noted, I mean the pinout of GPIO ports and buses.
I've never found a problem with that. Buses are a bit dated unless you are designing with external memory, not my typical design. Otherwise I find I can assign the I/O to suit my board routing. Heck, when I design with FPGAs, I do a schematic and then redo the pinout to optimize my board routing. Some designs just would not fit on the board if I didn't, at least not without more layers.
> Even SCK, MISO and MOSI end up jumbled! How the hell?
How can you care about routing three signals? What would you expect for a pinout?
> One plus about ATmegas is their pinouts are always nice.
I use FPGAs a lot more than micros. FPGAs will do anything a typical MCU will do, but not the converse. MCUs are useful if you need a lot of complex software to do the job. It would be hard to implement an IP stack in VHDL... unless you implement a CPU which I have done. Sometimes it's just easier to include it in the FPGA than to add another device and programming port and crystal and... -- Rick C