Power MOSFETs have highly-nonlinear capacitances. For the new super-junction types, voltages 500V to 800V, nonlinearity can be severe, up to 100x. A new Coss spec, effective capacitance, comes in time related (tr) and energy related (er) forms, with a stated voltage, usually 80% of breakdown. It's a fixed capacitance that matches the FET's charging time or energy consumption. Older FET datasheets are missing these values. Anyway, I have created an instrument to measure these parameters and more, like Eoss vs drain voltage. For schematic and pcb layout, see DropBox link: https://www.dropbox.com/sh/0r75g7tzy1yuqw8/AACVeaFZds1jb19D_fEfdwMha?dl=0 Non-proprietary, sharing is OK. Comments please. -- Thanks, - Win
MOSFET Coss(er), Coss(tr), Eoss, etc
Started by ●April 12, 2016
Reply by ●April 12, 20162016-04-12
On 12 Apr 2016 10:37:37 -0700, Winfield Hill <hill@rowland.harvard.edu> wrote:> > Power MOSFETs have highly-nonlinear capacitances. > For the new super-junction types, voltages 500V > to 800V, nonlinearity can be severe, up to 100x. > A new Coss spec, effective capacitance, comes in > time related (tr) and energy related (er) forms, > with a stated voltage, usually 80% of breakdown. > It's a fixed capacitance that matches the FET's > charging time or energy consumption. Older FET > datasheets are missing these values. Anyway, > I have created an instrument to measure these > parameters and more, like Eoss vs drain voltage. > For schematic and pcb layout, see DropBox link: > https://www.dropbox.com/sh/0r75g7tzy1yuqw8/AACVeaFZds1jb19D_fEfdwMha?dl=0 > Non-proprietary, sharing is OK. Comments please.Are Q11 etc to protect the LND150 gates? I tested some and they have internal zeners that conduct nicely at about +-42 volts. Wouldn't a c-v curve have the same information, after a little mashing? -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●April 12, 20162016-04-12
Cool! There are still other capacitance-measuring methods, _none_ of which really apply: "Energy equivalent" "Time related equivalent" (by CCS) "Time related equivalent" (by RC to 80%) "Hard switching equivalent" [*] (I think it's IR who uses the RC method.) Of course your circuit measures the energy parameter, and by measuring the risetime of the event (rail to rail, not 10-90%), you can get the CCS time equivalent as well. That's half of them! [*] I don't think I've seen this anywhere. So I guess I invented it. Explanation: consider that Superjunction capacitance acts like diode recovery, except over a span of 10s of volts, rather than ~1V. Consider an inductor switched across the transistor, from a constant voltage supply: at first, current will rise almost linearly with time (as the voltage creeps up), then as it leaves the high-C range, it explodes away with very fast dV/dt. As voltage crosses VDD, the inductance remains charged to some nonzero current, which is energy that must be minimized (if your layout can be made tight enough with respect to the switching speed of the transistors), or snubbed. Because the inductor doesn't have the same (or complementary, I'm not sure) nonlinearity, one cannot use an energy argument here, to evaluate either the peak current or the risetime from existing manufacturer data. In a typical application, the inductance being modeled, is the loop inductance of a half-bridge (high side - low side - supply bypass C). This would give a reasonably accurate result for hard-switching risetime. For something like, say, an LLC induction heater[**], risetime would vary between the CCS equivalent case (soft switching, load current-commutated) and hard switching (under light load). [**] An LLC converter might avoid hard switching, because it doesn't need a wide frequency range. So I'm just choosing this to be specific. Anyway, I like the divider-cascoded-into-bottom solution. U3A seems kind of overkill, but I suppose a matched pair (Q16 plus a companion) wouldn't be accurate enough. (Hey what? That VR25000002005KA100 is only 10%! and there's no trim..?!) Similarly elsewhere, there's a lot of trim for offsets, but not for divider tolerances, by the looks of it. Huh, PCAD.. ancient! ;) I don't suppose there's a color output mode, is there? It's hard to follow all the text boxes, net labels and component comments when they're all the same size, and packed so tightly on one sheet. (Alternately, can you do it on a bigger e.g. B or C sheet? I don't mean redraw the whole thing, just as a suggestion.) Like, what's the difference between "SIG" and "Vx/150 SIG" ? Are they all the "SIG" net and "Vx/150" is just a label? (And obligatory "Sloman should love it because it's got a 555". :^) Two of them even. A 556.) Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com "Winfield Hill" <hill@rowland.harvard.edu> wrote in message news:nejbp1048g@drn.newsguy.com...> > Power MOSFETs have highly-nonlinear capacitances. > For the new super-junction types, voltages 500V > to 800V, nonlinearity can be severe, up to 100x. > A new Coss spec, effective capacitance, comes in > time related (tr) and energy related (er) forms, > with a stated voltage, usually 80% of breakdown. > It's a fixed capacitance that matches the FET's > charging time or energy consumption. Older FET > datasheets are missing these values. Anyway, > I have created an instrument to measure these > parameters and more, like Eoss vs drain voltage. > For schematic and pcb layout, see DropBox link: > https://www.dropbox.com/sh/0r75g7tzy1yuqw8/AACVeaFZds1jb19D_fEfdwMha?dl=0 > Non-proprietary, sharing is OK. Comments please. > > > -- > Thanks, > - Win
Reply by ●April 12, 20162016-04-12
On 12 Apr 2016 10:37:37 -0700, Winfield Hill <hill@rowland.harvard.edu> wrote:> > Power MOSFETs have highly-nonlinear capacitances. > For the new super-junction types, voltages 500V > to 800V, nonlinearity can be severe, up to 100x. > A new Coss spec, effective capacitance, comes in > time related (tr) and energy related (er) forms, > with a stated voltage, usually 80% of breakdown. > It's a fixed capacitance that matches the FET's > charging time or energy consumption. Older FET > datasheets are missing these values. Anyway, > I have created an instrument to measure these > parameters and more, like Eoss vs drain voltage. > For schematic and pcb layout, see DropBox link: > https://www.dropbox.com/sh/0r75g7tzy1yuqw8/AACVeaFZds1jb19D_fEfdwMha?dl=0 > Non-proprietary, sharing is OK. Comments please.Do the Spice models properly model these "highly-nonlinear capacitances"? ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | The touchstone of liberalism is intolerance
Reply by ●April 12, 20162016-04-12
On Tue, 12 Apr 2016 12:56:05 -0700, Jim Thompson wrote:> Do the Spice models properly model these "highly-nonlinear > capacitances"? > >I very much doubt it.
Reply by ●April 12, 20162016-04-12
Tim Williams wrote...> > Cool!Thanks for your comments!> There are still other capacitance-measuring methods, > _none_ of which really apply: > "Energy equivalent" > "Time related equivalent" (by CCS) > "Time related equivalent" (by RC to 80%) > "Hard switching equivalent" [*] > (I think it's IR who uses the RC method.) > > Of course your circuit measures the energy parameter, > and by measuring the risetime of the event (rail to rail, > not 10-90%), you can get the CCS time equivalent as well. > That's half of them!I'm hoping CS RR gives close to the Coss(tr) value. But Coss(er) is more important.>[*] I don't think I've seen this anywhere. So I > guess I invented it.I long ago made an instrument like that, IIUC. Run half-bridge run 10kHz, etc, no load, just plug in two DUTs, measure the power drain. Simple, useful. But I wanted more detail.> Explanation: consider ... [ snip ]Just to point out right now my interest is not in switched inductors, but it's an important topic.> Anyway, I like the divider-cascoded-into-bottom > solution. U3A seems kind of overkill, but I > suppose a matched pair (Q16 plus a companion) > wouldn't be accurate enough.Correct, one current would be fixed, while the other drops to well below 1uA, so the opamp is necessary. It's important for low Vx values near 1.0V (10mV or so after dividing) to have low offset, because Coss changes so much near 0V.> (Hey what? That VR25000002005KA100 is only 10%! > and there's no trim..?!) Similarly elsewhere, > there's a lot of trim for offsets, but not for > divider tolerances, by the looks of it.Yep. I'll measure the caps before installing, thereby providing the necessary parasitic CAL data (opto-couplers, etc.). C0G doesn't have the DA soakage effect. I think a 1 or 2% measurement of the Vx voltage is more than good enough, provided the zero offset is low.> Huh, PCAD.. ancient! ;)My PC CAD files are all under my PCAAD folder, but I long ago migrated to full Altium Designer.> I don't suppose there's a color output mode, is > there? It's hard to follow all the text boxes, > net labels and component comments when they're > all the same size, and packed so tightly on one > sheet. (Alternately, can you do it on a bigger > e.g. B or C sheet? I don't mean redraw the > whole thing, just as a suggestion.)It's B-size, and prints better on 11x17 paper. My drawing is in color onscreen, with standard Protel colors (my PCB tech's original choice). I'll add a color version to the DropBox folder.> Like, what's the difference between "SIG" and > "Vx/150 SIG"Yes, it's easier to see the difference between the PCB net-names, and notes or connector names, etc., if you have color image.> (And obligatory "Sloman should love it because > it's got a 555". :^) Two of them even. A 556.)Yep! I like 555s, you get a flip flop, two comparators, and various other useful items. But I only use CMOS versions, thanks! Thanks --- Win>"Winfield Hill" wrote in message > news:nejbp1048g@drn.newsguy.com... >> >> Power MOSFETs have highly-nonlinear capacitances. >> For the new super-junction types, voltages 500V >> to 800V, nonlinearity can be severe, up to 100x. >> A new Coss spec, effective capacitance, comes in >> time related (tr) and energy related (er) forms, >> with a stated voltage, usually 80% of breakdown. >> It's a fixed capacitance that matches the FET's >> charging time or energy consumption. Older FET >> datasheets are missing these values. Anyway, >> I have created an instrument to measure these >> parameters and more, like Eoss vs drain voltage. >> For schematic and pcb layout, see DropBox link: >> https://www.dropbox.com/sh/0r75g7tzy1yuqw8/AACVeaFZds1jb19D_fEfdwMha?dl=0 >> Non-proprietary, sharing is OK. Comments please.-- Thanks, - Win
Reply by ●April 12, 20162016-04-12
Winfield Hill wrote...> Tim Williams wrote... > >> I don't suppose there's a color output ... > > I'll add a color version to the DropBox folder.Done. Note, the color version doesn't print well on BW printers. But it's good onscreen. -- Thanks, - Win
Reply by ●April 12, 20162016-04-12
Jim Thompson wrote...> > Winfield Hill wrote: > >> Power MOSFETs have highly-nonlinear capacitances. >> For the new super-junction types, voltages 500V >> to 800V, nonlinearity can be severe, up to 100x. > > Do the Spice models properly model these > "highly-nonlinear capacitances"?I would have said, no, but I found an example to the contrary. This Infineon link has a 49-page article by Anders Lind, with "support material". http://www.infineon.com/dgdl/Infineon-Application+Note+Detailed+MOSFET+Behavioral+Analysis-AN-v01_00-EN.zip?fileId=5546d4624e24005f014e2a32e3f86291 [What an insane link address!] In that you'll find a spreadsheet with 800 Coss data points for SPA11N80C3 super-junction MOSFET. These Coss data points were extracted into Excel from the part's SPICE model, and they look petty close to the datasheet plot. The article has details. The SPICE model will be in my next post. -- Thanks, - Win
Reply by ●April 12, 20162016-04-12
Winfield Hill wrote...> > I would have said, no, but I found an example to > the contrary. This Infineon link has a 49-page > article by Anders Lind, with "support material". >http://www.infineon.com/dgdl/Infineon-Application+Note+Detailed+MOSFET+Behavioral+Analysis-AN-v01_00-EN.zip?fileId=5546d4624e24005f014e2a32e3f86291 > > In that you'll find a spreadsheet with 800 Coss > data points for SPA11N80C3 super-junction MOSFET. > These Coss data points were extracted into Excel > from the part's SPICE model, and they look petty > close to the datasheet plot. The article has > details. The SPICE model will be in my next post.SPA11N80C3.txt from PSpice_CoolMOS-C3_800V.lib ****** .SUBCKT SPA11N80C3_L0 drain gate source Lg gate g1 7n Ld drain d1 3n Ls source s1 7n Rs s1 s2 1m Rg g1 g2 1 M1 d2 g2 s2 s2 DMOS L=1u W=1u .MODEL DMOS NMOS ( KP= 12.62 VTO=4 THETA=0 VMAX=1.5e5 ETA=0 LEVEL=3) Rd d2 d1a 0.356 TC=12m .MODEL MVDR NMOS (KP=35.15 VTO=-1 LAMBDA=0.1) Mr d1 d2a d1a d1a MVDR W=1u L=1u Rx d2a d1a 1m Cds1 s2 d2 33.9p Dbd s2 d2 Dbt .MODEL Dbt D(BV=800 M=0.55 CJO=1.75n VJ=0.5V) Dbody s2 21 DBODY .MODEL DBODY D(IS=0.7p N=1 RS=10u EG=1.12 TT=750n) Rdiode d1 21 12.9m TC=6m .MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) Maux g2 c a a sw Maux2 b d g2 g2 sw Eaux c a d2 g2 1 Eaux2 d g2 d2 g2 -1 Cox b d2 3.66n .MODEL DGD D(M=1.2 CJO=3.66n VJ=0.5) Rpar b d2 1Meg Dgd a d2 DGD Rpar2 d2 a 10Meg Cgs g2 s2 1.22n .ENDS SPA11N80C3_L0 ****** ********** .SUBCKT SPA11N80C3_L1 drain gate source PARAMS: dVth=0 dRdson=0 .PARAM Rs=1m Rg=1 Ls=7n Ld=3n Lg=7n .PARAM act=13.57 Inn=7.1 Unn=10 Rmax=450m X1 dd g s Tj Tj cool_800_c_var PARAMS: act={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} +Rmax={Rmax} Rs={Rs} heat=0 L_Ld drain dd {Ld} R_Ld drain dd 10 L_Ls source lsrs {Ls} R_Ls source lsrs 10 R_Rs s lsrs {Rs} L_Lg gate lgrg {Lg} R_Lg gate lgrg 10 R_Rg lgrg g {Rg} E1 Tj w VALUE={TEMP} R1 w 0 1u .ENDS ********** ********** .SUBCKT SPA11N80C3_L3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 Zthtype=0 .PARAM Rs=1m Rg=1 Ls=7n Ld=3n Lg=7n .PARAM act=13.57 Inn=7.1 Unn=10 Rmax=450m .PARAM lzth={limit(Zthtype,0,1)} X1 dd g s Tj 1 cool_800_c_var PARAMS: act={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} +Rmax={Rmax} Rs={Rs} heat=1 L_Ld drain dd {Ld} R_Ld drain dd 10 L_Ls source lsrs {Ls} R_Ls source lsrs 10 R_Rs s lsrs {Rs} L_Lg gate lgrg {Lg} R_Lg gate lgrg 10 R_Rg lgrg g {Rg} C_CZth1 Tj 0 130.543u C_CZth2 0 1 1.336m C_CZth3 0 2 1.19m C_CZth4 0 3 6.336m C_CZth5 0 4 19.064m C_CZth6 0 5 18m C_CZth7 0 6 500m C_CZth8 0 7 600m R_Rth1 Tj 1 {17.41m+lzth*4.51m} R_Rth2 1 2 {24.76m+lzth*6.42m} R_Rth3 2 3 {93.55m+lzth*24.25m} R_Rth4 3 4 {145.89m+lzth*31.95m} R_Rth5 4 5 {144.16m+lzth*29.69m} R_Rth6 5 6 400m R_Rth7 6 7 5 R_Rth8 5 Tcase {2.1+lzth*427.4m} .ENDS ********** .SUBCKT cool_800_c_var dd g s Tj t1 PARAMS: dVth=0 act=1 dR=0 dgfs=0 Inn=1u Unn=10 Rmax=1 Rs=1u heat=1 *control parameter: 1 if diode should store charge, 0 otherwise .PARAM enable_diode=1 .PARAM w0={0.5p+SQRT(act)*1p} w1={215p*act} w2={41p*act} x1=-1.39 x2=-139m Uoff=0.25 y1={exp(Uoff*x1)} .PARAM w3={150p*act} w4={45p*act} w5={200p*act} x3=-105.3m x4=0.5 x5=2 x6=1 x7=1 .PARAM w6={85p*act} w7={60p*act} sl={2p*act} .PARAM Cgs={90p*act} Cox={w0+w1+w2} .PARAM k14=-2 deltb=1 .PARAM L=2u g2=57.5m fpar1=90m fpar2=2 .PARAM Vth0=3.75 fpar29=300 Tref=273 fpar3=5.5m .PARAM fpar4=800m fpar5=100p fpar6=800 coxi=431.4u .PARAM Un=99.19u fpar7=207m W={148m*act} fpar9=5 .PARAM fpar10=2.4 g16=-27.24 ta=1u td=110n .PARAM fpar12=1 fpar13={5.169/act} fpar14={151m/act} fpar15=23 .PARAM fpar18=85.8u fpar19=-29 .PARAM fpar22={W*coxi*g2/L} .PARAM Vmin=2.75 Vmax=4.75 .PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} .PARAM p1={Unn-Inn*Rs-Vth0} .PARAM p2={(((p1-SQRT(p1**2-4*fpar2/fpar22*Inn*(1+fpar1*p1)))/fpar2*fpar12+1)**2-1)/(4*fpar12)} .PARAM p3={fpar15/(2*(Inn*(Inn*(Rmax-Rs)-p2)))} .PARAM Rlim={p3*(-fpar15+SQRT(fpar15**2+4*(Rmax*Inn)**2-8*Rmax*Inn*(Inn*Rs+p2)+(2*p2+2*Inn*Rs)**2))} .PARAM dRd={fpar13+if(dVth==0,limit(dR,0,1)*max(Rlim-fpar13,0),0)} .FUNC fpar24(Uee,p,pp,z1) {if(Uee>pp,(Uee-fpar2*z1)*z1,p*(pp-p)/fpar2*exp((Uee-pp)/p))} .FUNC fpar25(Uds,p,Uee,z1,Tjx) {(fpar22/(1+fpar1*Uee)*(fpar29/Tjx)**1.5)*fpar24(Uee,p,min(2*p,p+fpar2*Uds),z1)} .FUNC fpar28(Uds,Ugs,Tjx,p) {fpar25(Uds,p,Ugs-Vth+fpar3*(Tjx-fpar29),min(Uds,(Ugs-Vth+fpar3*(Tjx-fpar29))/(2*fpar2)),Tjx)} .FUNC fpar26(Uds,Tjx) {act*exp(min(fpar19+(Uds-fpar6-fpar4*(Tjx-fpar29))/fpar7,23))} .FUNC fpar27(Uds,Ugs,Tjx) {sgn(Uds)*fpar28((SQRT(1+4*fpar12*abs(Uds))-1)/2/fpar12,Ugs,Tjx,fpar9*fpar18*Tjx)} .FUNC fpar31(Tjx) {exp(min(g16+(Tjx/fpar29-1)*(1.12/(Un*Tjx)),23))*(Tjx/fpar29)**1.5} .FUNC Ird(Usd,Tjx) {act*(-fpar31(Tjx)+exp(min(log(fpar31(Tjx))+Usd/(Un*Tjx),23)))} .FUNC QCds(x,z) {w7*z-sl*z**2/2-w6*max((w7-w6)/sl-x,0)} G_G1 d s VALUE={fpar27(V(d,s),V(g,s),Tref+limit(V(Tj),-200,999))} R1 g s 2G Rd01 d s 500Meg G_G_Rd ldrd d VALUE {V(ldrd,d)/((dRd*0.5*(1+SQRT(1+4*(max(V(ldrd,d),0)/fpar15)**2))) + *((Tref+LIMIT(V(t1),-200,999))/fpar29)**fpar10)} R_R_ERd_g ldrd d 10k G_Rdiod ldrd dio2 VALUE { V(ldrd,dio2)/(fpar14*((Tref+LIMIT(V(t1),-200,999))/fpar29)**1.5)} R_Rdiod ldrd dio 500Meg V_sense dio dio2 0 G_diode s dio VALUE={Ird(V(s,dio),Tref+LIMIT(V(t1),-200,999))} Rd02 s dio2 500Meg G_diode2 s dio2 VALUE={LIMIT(I(V_sense2),-1k,1k)-fpar26(V(dio2,s),Tref+LIMIT(V(t1),-200,999))} C_pack dd g {w0} E_Edg1 d ox1 VALUE {V(d,g)-((exp(min((V(d,g)+Uoff)*x1,0))-y1)/x1+min((V(d,g)+Uoff),0))} C_Cdg1 ox1 g {w1} E_Edg2 d ox2 VALUE {V(d,g)-((exp(min(V(d,g)*x2,0))-1)/x2+min(V(d,g),0))} C_Cdg2 ox2 g {w2} E_Eds1 dio2 dEQJ1 VALUE {V(dio2,s)-(exp(min(V(dio2,s)*x3,0))-1)/x3+min(V(dio2,s),0)} C_Cds1 s dEQJ1 {w3} E_Eds2 d dEQJ2 VALUE {V(d,s)-2*(SQRT(x6*limit(x6+V(d,s),0,2*fpar6))-x6)} C_Cds2 s dEQJ2 {w4} E_Eds3 dio2 dEQJ3 VALUE {V(dio2,s)-1/(1-x5)*(x7**x5*limit(x7+V(dio2,s),1e-6,2*fpar6)**(1-x5)-x7)} C_Cds3 s dEQJ3 {w5} E_Eds4 d dEQJ4 VALUE {V(d,s)-(w7*limit(V(d,s),(w7-w6)/sl,w7/sl)-sl*limit(V(d,s), +(w7-w6)/sl,w7/sl)**2/2-w6*max((w7-w6)/sl-V(d,s),0))/w6} C_Cds4 s dEQJ4 {w6} E_Egs g sm VALUE {(0.5*((V(g,s)-k14)+SQRT((V(g,s)-k14)**2+deltb*0.3))-deltb*0.3)*Cox/(Cgs+Cox)} C_Cgs sm s {Cgs+Cox} V_Isense dd ldrd 0 G_G_Ptot_channel 0 Tj VALUE {heat*LIMIT(V(d,s)*I(V_Isense),0,100k) } G_G_Ptot_Epi 0 t1 VALUE {heat*LIMIT(V(ldrd,d)*I(V_Isense),0,100k) } *auxillary circuit for non-equilibirium diode charge C_C001 a 0 {ta*td/(ta+td)} R_R001 a b 1 V_sense2 b fpar2 0 E_E001 fpar2 0 VALUE {-enable_diode*ta/td*I(V_sense)} .ENDS *$ ************************ -- Thanks, - Win
Reply by ●April 12, 20162016-04-12
On 12 Apr 2016 17:29:49 -0700, Winfield Hill <hill@rowland.harvard.edu> wrote:>Winfield Hill wrote... >> >> I would have said, no, but I found an example to >> the contrary. This Infineon link has a 49-page >> article by Anders Lind, with "support material". >>http://www.infineon.com/dgdl/Infineon-Application+Note+Detailed+MOSFET+Behavioral+Analysis-AN-v01_00-EN.zip?fileId=5546d4624e24005f014e2a32e3f86291 >> >> In that you'll find a spreadsheet with 800 Coss >> data points for SPA11N80C3 super-junction MOSFET. >> These Coss data points were extracted into Excel >> from the part's SPICE model, and they look petty >> close to the datasheet plot. The article has >> details. The SPICE model will be in my next post. > >SPA11N80C3.txt > >from PSpice_CoolMOS-C3_800V.lib > >****** > >.SUBCKT SPA11N80C3_L0 drain gate source > >Lg gate g1 7n >Ld drain d1 3n >Ls source s1 7n[snip]>R_R001 a b 1 >V_sense2 b fpar2 0 >E_E001 fpar2 0 VALUE {-enable_diode*ta/td*I(V_sense)} > >.ENDS >*$ > >************************How well does that run on LTspice ?>:-} ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | The touchstone of liberalism is intolerance
