Tim Williams wrote...> > I put it all in a spreadsheet, but it's really rather > messy to release, so I'll speak to a screenshot instead:Very interesting. Thanks! -- Thanks, - Win
Tim Williams wrote...> > I put it all in a spreadsheet, but it's really rather > messy to release, so I'll speak to a screenshot instead:Very interesting. Thanks! -- Thanks, - Win
"Winfield Hill" <hill@rowland.harvard.edu> wrote in message news:nek3l40129c@drn.newsguy.com...>> Do the Spice models properly model these >> "highly-nonlinear capacitances"? > > I would have said, no, but I found an example to > the contrary. This Infineon link has a 49-page > article by Anders Lind, with "support material". > http://www.infineon.com/dgdl/Infineon-Application+Note+Detailed+MOSFET+Behavioral+Analysis-AN-v01_00-EN.zip?fileId=5546d4624e24005f014e2a32e3f86291 > > [What an insane link address!] > > In that you'll find a spreadsheet with 800 Coss > data points for SPA11N80C3 super-junction MOSFET. > These Coss data points were extracted into Excel > from the part's SPICE model, and they look petty > close to the datasheet plot. The article has > details. The SPICE model will be in my next post.I've got you one better ... if only in one specific case, I guess. Some time ago, I was looking at the STW70N60M2 and related parts in the family. I put it all in a spreadsheet, but it's really rather messy to release, so I'll speak to a screenshot instead: http://seventransistorlabs.com/Images/STW70N60_Capacitance_Worksheet.png My interest was to create a SPICE model of the '70. The '24 (24A class) was available. Surely it's a simple matter of scaling up the terminal currents proportionally -- more or less? So let's see how the 24 works. Hmm. Turns out, the SPICE model is in error by about 150%! This is illustrated as the blue curve in the energy plot (left middle), and the capacitance plot (right middle). Meanwhile, I used SPICE's junction capacitance formula to approximate Coss, on whatever basis I can fit it. This resulted in the blue curves on the top two plots: the energy is best-fit (by eye, to a screenshot of the model; I didn't bother with curve extraction at the time), while the capacitance is pretty reasonably close, except for that bizarre hiccup at 10-15V. What the hell is up with that? Do they *check* these plots? Aside: On a separate occasion, I've measured the STP19NM50N, http://seventransistorlabs.com/Images/STP19NM50N_Cdss_Overlay.jpg and here it's plotted over the datasheet graph. See how it tanks like that? Yeah, the real thing doesn't tank like that. I suspect it's a plotting error (bad use of Bezier objects??), but crap like this /shouldn't make it into datasheets/. So I suspect the energy curve isn't bad, and my model is probably a good fit to the real part. Back to the 24A part's SPICE model. I set up a SPICE "test bench" to directly read off E(V) and C(V), and compared my models (using diodes of appropriate CJO, M and VJ) to the SPICE models. This is where I obtained the 24's erroneous curves, and corrected them. In case you were curious, ST wasn't interested in my fix for their crummy model. ;-) Finally, the bottom two plots show charging curves. These are generated by taking 1000 points (it's a big spreadsheet..) and solving the difference equation for the appropriate equivalent circuit. The three sets of curves are for the '70 (hand-fitted), the '24 (from SPICE), and then the '70 model scaled to the '24's datasheet value (which is also the best-fit red curve in the middle graphs, so indeed this appears to be a geometry scaling only). The "R (us)" curves are the resistor-charge-to-80% value. As you can see, this starts much the same as the CCS method, but has a terribly long tail, so tends to unfairly weight the capacitance at high voltages, which will give a low estimate. The "CCS (us)" curves, of course, are simply by CCS alone. The OP circuit will generate this waveform, backwards of course. In fuchsia, "ramp (us)" was only computed for the '70, and uses a linear current ramp to approximate an inductance. As you can see, it's practically diode recovery: it sits there, below 20V, for a long-ass time, then bolts like a spooked horse! The final output numbers (from these curves) are given near the input parameters: Res = resistive equivalent (100kohm resistor to +600V; equivalent is based on the time taken to 80%, or 480V) CCS = constant current time equivalent Cdss E_eff = energy equivalent ramp eff = inductive hard switching equivalent (my method). As you can see, the equivalents are kind of all over the place; CCS makes the largest equivalent, while energy is the lowest. If you see one but not the other, you can probably guess a datasheet is trying to sell you something. The model data is also present here: Cpar is fixed capacitance, CJO, m and VJ are diode parameters, and both models have two diodes in parallel (allowing two VJ breakpoints). Obviously, the one that's 0nF doesn't count, so a good fit was had with just the one. The m values are quite large (ultrahyperabrupt?), whereas some SPICE engines limit it to 0.9 or something like that, for diodes. (Does anyone have any clue why? It's a completely arbitrary and superfluous limit!) So I also built a nonlinear dependent equivalent, which works fine on any SPICE. Tim -- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com
On 12 Apr 2016 19:29:11 -0700, Winfield Hill <hill@rowland.harvard.edu> wrote:>Jim Thompson wrote... >> >> I design on PSpice... by client requirements, >> my models must run on LTspice... > > Whao, cheap-ass clients!Actually not the _client_, the client's _customers_ use LTspice. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | The touchstone of liberalism is intolerance
Jim Thompson wrote...> > I design on PSpice... by client requirements, > my models must run on LTspice...Whao, cheap-ass clients! -- Thanks, - Win
On 12 Apr 2016 18:13:08 -0700, Winfield Hill <hill@rowland.harvard.edu> wrote:>Jim Thompson wrote... >> >> Winfield Hill wrote: >>> SPA11N80C3.txt >>> from PSpice_CoolMOS-C3_800V.lib >>> >>> ****** >>> .SUBCKT SPA11N80C3_L0 drain gate source >>> Lg gate g1 7n >>> Ld drain d1 3n >>> Ls source s1 7n >> [snip] >>> R_R001 a b 1 >>> V_sense2 b fpar2 0 >>> E_E001 fpar2 0 VALUE {-enable_diode*ta/td*I(V_sense)} >>> >>> .ENDS >>> *$ >>> ************************ >> >> How well does that run on LTspice ?>:-} > > Hah, I thought you had PSpice. I keep thinking > about getting a copy, given constant struggles.I design on PSpice... by client requirements, my models must run on LTspice... thus my back-handed comment >:-} ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | The touchstone of liberalism is intolerance
Jim Thompson wrote...> > Winfield Hill wrote: >> SPA11N80C3.txt >> from PSpice_CoolMOS-C3_800V.lib >> >> ****** >> .SUBCKT SPA11N80C3_L0 drain gate source >> Lg gate g1 7n >> Ld drain d1 3n >> Ls source s1 7n > [snip] >> R_R001 a b 1 >> V_sense2 b fpar2 0 >> E_E001 fpar2 0 VALUE {-enable_diode*ta/td*I(V_sense)} >> >> .ENDS >> *$ >> ************************ > > How well does that run on LTspice ?>:-}Hah, I thought you had PSpice. I keep thinking about getting a copy, given constant struggles. -- Thanks, - Win
On 12 Apr 2016 17:29:49 -0700, Winfield Hill <hill@rowland.harvard.edu> wrote:>Winfield Hill wrote... >> >> I would have said, no, but I found an example to >> the contrary. This Infineon link has a 49-page >> article by Anders Lind, with "support material". >>http://www.infineon.com/dgdl/Infineon-Application+Note+Detailed+MOSFET+Behavioral+Analysis-AN-v01_00-EN.zip?fileId=5546d4624e24005f014e2a32e3f86291 >> >> In that you'll find a spreadsheet with 800 Coss >> data points for SPA11N80C3 super-junction MOSFET. >> These Coss data points were extracted into Excel >> from the part's SPICE model, and they look petty >> close to the datasheet plot. The article has >> details. The SPICE model will be in my next post. > >SPA11N80C3.txt > >from PSpice_CoolMOS-C3_800V.lib > >****** > >.SUBCKT SPA11N80C3_L0 drain gate source > >Lg gate g1 7n >Ld drain d1 3n >Ls source s1 7n[snip]>R_R001 a b 1 >V_sense2 b fpar2 0 >E_E001 fpar2 0 VALUE {-enable_diode*ta/td*I(V_sense)} > >.ENDS >*$ > >************************How well does that run on LTspice ?>:-} ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | The touchstone of liberalism is intolerance
Winfield Hill wrote...> > I would have said, no, but I found an example to > the contrary. This Infineon link has a 49-page > article by Anders Lind, with "support material". >http://www.infineon.com/dgdl/Infineon-Application+Note+Detailed+MOSFET+Behavioral+Analysis-AN-v01_00-EN.zip?fileId=5546d4624e24005f014e2a32e3f86291 > > In that you'll find a spreadsheet with 800 Coss > data points for SPA11N80C3 super-junction MOSFET. > These Coss data points were extracted into Excel > from the part's SPICE model, and they look petty > close to the datasheet plot. The article has > details. The SPICE model will be in my next post.SPA11N80C3.txt from PSpice_CoolMOS-C3_800V.lib ****** .SUBCKT SPA11N80C3_L0 drain gate source Lg gate g1 7n Ld drain d1 3n Ls source s1 7n Rs s1 s2 1m Rg g1 g2 1 M1 d2 g2 s2 s2 DMOS L=1u W=1u .MODEL DMOS NMOS ( KP= 12.62 VTO=4 THETA=0 VMAX=1.5e5 ETA=0 LEVEL=3) Rd d2 d1a 0.356 TC=12m .MODEL MVDR NMOS (KP=35.15 VTO=-1 LAMBDA=0.1) Mr d1 d2a d1a d1a MVDR W=1u L=1u Rx d2a d1a 1m Cds1 s2 d2 33.9p Dbd s2 d2 Dbt .MODEL Dbt D(BV=800 M=0.55 CJO=1.75n VJ=0.5V) Dbody s2 21 DBODY .MODEL DBODY D(IS=0.7p N=1 RS=10u EG=1.12 TT=750n) Rdiode d1 21 12.9m TC=6m .MODEL sw NMOS(VTO=0 KP=10 LEVEL=1) Maux g2 c a a sw Maux2 b d g2 g2 sw Eaux c a d2 g2 1 Eaux2 d g2 d2 g2 -1 Cox b d2 3.66n .MODEL DGD D(M=1.2 CJO=3.66n VJ=0.5) Rpar b d2 1Meg Dgd a d2 DGD Rpar2 d2 a 10Meg Cgs g2 s2 1.22n .ENDS SPA11N80C3_L0 ****** ********** .SUBCKT SPA11N80C3_L1 drain gate source PARAMS: dVth=0 dRdson=0 .PARAM Rs=1m Rg=1 Ls=7n Ld=3n Lg=7n .PARAM act=13.57 Inn=7.1 Unn=10 Rmax=450m X1 dd g s Tj Tj cool_800_c_var PARAMS: act={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} +Rmax={Rmax} Rs={Rs} heat=0 L_Ld drain dd {Ld} R_Ld drain dd 10 L_Ls source lsrs {Ls} R_Ls source lsrs 10 R_Rs s lsrs {Rs} L_Lg gate lgrg {Lg} R_Lg gate lgrg 10 R_Rg lgrg g {Rg} E1 Tj w VALUE={TEMP} R1 w 0 1u .ENDS ********** ********** .SUBCKT SPA11N80C3_L3 drain gate source Tj Tcase PARAMS: dVth=0 dRdson=0 Zthtype=0 .PARAM Rs=1m Rg=1 Ls=7n Ld=3n Lg=7n .PARAM act=13.57 Inn=7.1 Unn=10 Rmax=450m .PARAM lzth={limit(Zthtype,0,1)} X1 dd g s Tj 1 cool_800_c_var PARAMS: act={act} dVth={dVth} dR={dRdson} Inn={Inn} Unn={Unn} +Rmax={Rmax} Rs={Rs} heat=1 L_Ld drain dd {Ld} R_Ld drain dd 10 L_Ls source lsrs {Ls} R_Ls source lsrs 10 R_Rs s lsrs {Rs} L_Lg gate lgrg {Lg} R_Lg gate lgrg 10 R_Rg lgrg g {Rg} C_CZth1 Tj 0 130.543u C_CZth2 0 1 1.336m C_CZth3 0 2 1.19m C_CZth4 0 3 6.336m C_CZth5 0 4 19.064m C_CZth6 0 5 18m C_CZth7 0 6 500m C_CZth8 0 7 600m R_Rth1 Tj 1 {17.41m+lzth*4.51m} R_Rth2 1 2 {24.76m+lzth*6.42m} R_Rth3 2 3 {93.55m+lzth*24.25m} R_Rth4 3 4 {145.89m+lzth*31.95m} R_Rth5 4 5 {144.16m+lzth*29.69m} R_Rth6 5 6 400m R_Rth7 6 7 5 R_Rth8 5 Tcase {2.1+lzth*427.4m} .ENDS ********** .SUBCKT cool_800_c_var dd g s Tj t1 PARAMS: dVth=0 act=1 dR=0 dgfs=0 Inn=1u Unn=10 Rmax=1 Rs=1u heat=1 *control parameter: 1 if diode should store charge, 0 otherwise .PARAM enable_diode=1 .PARAM w0={0.5p+SQRT(act)*1p} w1={215p*act} w2={41p*act} x1=-1.39 x2=-139m Uoff=0.25 y1={exp(Uoff*x1)} .PARAM w3={150p*act} w4={45p*act} w5={200p*act} x3=-105.3m x4=0.5 x5=2 x6=1 x7=1 .PARAM w6={85p*act} w7={60p*act} sl={2p*act} .PARAM Cgs={90p*act} Cox={w0+w1+w2} .PARAM k14=-2 deltb=1 .PARAM L=2u g2=57.5m fpar1=90m fpar2=2 .PARAM Vth0=3.75 fpar29=300 Tref=273 fpar3=5.5m .PARAM fpar4=800m fpar5=100p fpar6=800 coxi=431.4u .PARAM Un=99.19u fpar7=207m W={148m*act} fpar9=5 .PARAM fpar10=2.4 g16=-27.24 ta=1u td=110n .PARAM fpar12=1 fpar13={5.169/act} fpar14={151m/act} fpar15=23 .PARAM fpar18=85.8u fpar19=-29 .PARAM fpar22={W*coxi*g2/L} .PARAM Vmin=2.75 Vmax=4.75 .PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)} .PARAM p1={Unn-Inn*Rs-Vth0} .PARAM p2={(((p1-SQRT(p1**2-4*fpar2/fpar22*Inn*(1+fpar1*p1)))/fpar2*fpar12+1)**2-1)/(4*fpar12)} .PARAM p3={fpar15/(2*(Inn*(Inn*(Rmax-Rs)-p2)))} .PARAM Rlim={p3*(-fpar15+SQRT(fpar15**2+4*(Rmax*Inn)**2-8*Rmax*Inn*(Inn*Rs+p2)+(2*p2+2*Inn*Rs)**2))} .PARAM dRd={fpar13+if(dVth==0,limit(dR,0,1)*max(Rlim-fpar13,0),0)} .FUNC fpar24(Uee,p,pp,z1) {if(Uee>pp,(Uee-fpar2*z1)*z1,p*(pp-p)/fpar2*exp((Uee-pp)/p))} .FUNC fpar25(Uds,p,Uee,z1,Tjx) {(fpar22/(1+fpar1*Uee)*(fpar29/Tjx)**1.5)*fpar24(Uee,p,min(2*p,p+fpar2*Uds),z1)} .FUNC fpar28(Uds,Ugs,Tjx,p) {fpar25(Uds,p,Ugs-Vth+fpar3*(Tjx-fpar29),min(Uds,(Ugs-Vth+fpar3*(Tjx-fpar29))/(2*fpar2)),Tjx)} .FUNC fpar26(Uds,Tjx) {act*exp(min(fpar19+(Uds-fpar6-fpar4*(Tjx-fpar29))/fpar7,23))} .FUNC fpar27(Uds,Ugs,Tjx) {sgn(Uds)*fpar28((SQRT(1+4*fpar12*abs(Uds))-1)/2/fpar12,Ugs,Tjx,fpar9*fpar18*Tjx)} .FUNC fpar31(Tjx) {exp(min(g16+(Tjx/fpar29-1)*(1.12/(Un*Tjx)),23))*(Tjx/fpar29)**1.5} .FUNC Ird(Usd,Tjx) {act*(-fpar31(Tjx)+exp(min(log(fpar31(Tjx))+Usd/(Un*Tjx),23)))} .FUNC QCds(x,z) {w7*z-sl*z**2/2-w6*max((w7-w6)/sl-x,0)} G_G1 d s VALUE={fpar27(V(d,s),V(g,s),Tref+limit(V(Tj),-200,999))} R1 g s 2G Rd01 d s 500Meg G_G_Rd ldrd d VALUE {V(ldrd,d)/((dRd*0.5*(1+SQRT(1+4*(max(V(ldrd,d),0)/fpar15)**2))) + *((Tref+LIMIT(V(t1),-200,999))/fpar29)**fpar10)} R_R_ERd_g ldrd d 10k G_Rdiod ldrd dio2 VALUE { V(ldrd,dio2)/(fpar14*((Tref+LIMIT(V(t1),-200,999))/fpar29)**1.5)} R_Rdiod ldrd dio 500Meg V_sense dio dio2 0 G_diode s dio VALUE={Ird(V(s,dio),Tref+LIMIT(V(t1),-200,999))} Rd02 s dio2 500Meg G_diode2 s dio2 VALUE={LIMIT(I(V_sense2),-1k,1k)-fpar26(V(dio2,s),Tref+LIMIT(V(t1),-200,999))} C_pack dd g {w0} E_Edg1 d ox1 VALUE {V(d,g)-((exp(min((V(d,g)+Uoff)*x1,0))-y1)/x1+min((V(d,g)+Uoff),0))} C_Cdg1 ox1 g {w1} E_Edg2 d ox2 VALUE {V(d,g)-((exp(min(V(d,g)*x2,0))-1)/x2+min(V(d,g),0))} C_Cdg2 ox2 g {w2} E_Eds1 dio2 dEQJ1 VALUE {V(dio2,s)-(exp(min(V(dio2,s)*x3,0))-1)/x3+min(V(dio2,s),0)} C_Cds1 s dEQJ1 {w3} E_Eds2 d dEQJ2 VALUE {V(d,s)-2*(SQRT(x6*limit(x6+V(d,s),0,2*fpar6))-x6)} C_Cds2 s dEQJ2 {w4} E_Eds3 dio2 dEQJ3 VALUE {V(dio2,s)-1/(1-x5)*(x7**x5*limit(x7+V(dio2,s),1e-6,2*fpar6)**(1-x5)-x7)} C_Cds3 s dEQJ3 {w5} E_Eds4 d dEQJ4 VALUE {V(d,s)-(w7*limit(V(d,s),(w7-w6)/sl,w7/sl)-sl*limit(V(d,s), +(w7-w6)/sl,w7/sl)**2/2-w6*max((w7-w6)/sl-V(d,s),0))/w6} C_Cds4 s dEQJ4 {w6} E_Egs g sm VALUE {(0.5*((V(g,s)-k14)+SQRT((V(g,s)-k14)**2+deltb*0.3))-deltb*0.3)*Cox/(Cgs+Cox)} C_Cgs sm s {Cgs+Cox} V_Isense dd ldrd 0 G_G_Ptot_channel 0 Tj VALUE {heat*LIMIT(V(d,s)*I(V_Isense),0,100k) } G_G_Ptot_Epi 0 t1 VALUE {heat*LIMIT(V(ldrd,d)*I(V_Isense),0,100k) } *auxillary circuit for non-equilibirium diode charge C_C001 a 0 {ta*td/(ta+td)} R_R001 a b 1 V_sense2 b fpar2 0 E_E001 fpar2 0 VALUE {-enable_diode*ta/td*I(V_sense)} .ENDS *$ ************************ -- Thanks, - Win
Jim Thompson wrote...> > Winfield Hill wrote: > >> Power MOSFETs have highly-nonlinear capacitances. >> For the new super-junction types, voltages 500V >> to 800V, nonlinearity can be severe, up to 100x. > > Do the Spice models properly model these > "highly-nonlinear capacitances"?I would have said, no, but I found an example to the contrary. This Infineon link has a 49-page article by Anders Lind, with "support material". http://www.infineon.com/dgdl/Infineon-Application+Note+Detailed+MOSFET+Behavioral+Analysis-AN-v01_00-EN.zip?fileId=5546d4624e24005f014e2a32e3f86291 [What an insane link address!] In that you'll find a spreadsheet with 800 Coss data points for SPA11N80C3 super-junction MOSFET. These Coss data points were extracted into Excel from the part's SPICE model, and they look petty close to the datasheet plot. The article has details. The SPICE model will be in my next post. -- Thanks, - Win