"Robert Baer" <robertbaer@localnet.com> wrote in message news:libst.7203$Zv.1563@newsfe08.iad...> Martin Riddle wrote: >> "P E Schoen"<paul@peschoen.com> wrote in message >> news:kor080$vjd$1@dont-email.me... >>> For most of my projects I use either a 14.7456 MHz crystal >>> (57600*256) >>> or 20.000 MHz (for USB 96 MHz 24*f/5). The 20 MHz crystal I am using >>> specifies a 20 pF parallel load, but my boards have 12 pF >>> capacitors. >>> I just noticed this and I think the value had been selected for a >>> previous brand of crystal, but the oscillator frequencies measure >>> pretty close to the ideal value, as follows for five boards: >>> >>> Board 1: 20.00258 +0.013% 130PPM >>> Board 2: 20.00039 +0.002% 20PPM >>> Board 3: 20.00068 +0.003% 30PPM >>> Board 4: 20.00085 +0.004% 40PPM >>> Board 5: 20.00073 +0.004% 40PPM >>> >>> My specification is 0.02%, or 200 PPM, so all are within spec, but >>> perhaps with the 20 pF capacitors the frequency will be much closer >>> and variation will be positive and negative. But the application >>> notes >>> I found seem a bit confusing as to the correct way to figure the >>> load >>> capacitance: >>> >>> http://www.statek.com/pdf/tn33.pdf >>> http://www.foxonline.com/pdfs/xtaldesignnotes.pdf >>> http://www.oscilent.com/spec_pages/PNDescrpt/Load_Cap.htm >>> >>> It seems that the capacitance is determined by: >>> >>> CL = (CL1*CL2)/(CL1+CL2)+CS >>> >>> Where CL1 and CL2 are the load capacitors and CS is the stray >>> capacitance, generally figured about 5 pF. So with my 12 pF >>> capacitors >>> the actual CL = 11 pF and with 20 pF capacitors CL = 15 pF and with >>> 47 >>> pF capacitors (as I think I used at one time), CL = 28.5 pF. The >>> ideal >>> value appears to be 30 pF. I don't know the actual stray >>> capacitance, >>> but it is a double sided board with 0805 SMT capacitors and a >>> PIC18F4455 microcontroller in a TQFP-44 package. It has a value of >>> 15 >>> pF or the OSC2 pin but this is characterized for external clock >>> drive >>> into OSC1. >>> >>> I think the 12 pF capacitors are OK but I think I will try changing >>> to >>> 20 pF and see if the frequency comes in closer. The crystal itself >>> is >>> rated 30 PPM and 100 PPM over the temperature range. Except for >>> board >>> #1, I'm just about there. >>> >>> But the CL formula seems a bit strange. Usually, when I see product >>> over sum, its square root is taken, as for parallel resistors. And >>> if >>> one of the capacitors is zero, the other apparently has no effect, >>> and >>> that just seems wrong. >>> >>> Paul >> >> See appnote 949 >> >> <http://ww1.microchip.com/downloads/en/AppNotes/00949a.pdf> >> >> Cheers >> >> >> > Does NOT give any "spec" or useful value; very good on hand-waving, > tho. >Really, computer problems again? Cheers
Capacitance value for PIC crystal
Started by ●June 6, 2013
Reply by ●June 7, 20132013-06-07
Reply by ●June 7, 20132013-06-07
"Martin Riddle" wrote in message news:korkbr$mtc$1@dont-email.me...> "Robert Baer" <robertbaer@localnet.com> wrote in message=20 > news:libst.7203$Zv.1563@newsfe08.iad...>>> <http://ww1.microchip.com/downloads/en/AppNotes/00949a.pdf>>> Does NOT give any "spec" or useful value; very good on hand-waving, =>> tho.> Really, computer problems again?The app note is marginally useful, but I think the easiest method is to=20 start with something like 18-22 pF capacitors and measure the clock=20 frequency directly (or better, via a separate pin derived from the = clock).=20 At least that's what I plan to do. YMMV. At least I found that the load capacitance value given by the = manufacturer=20 is NOT the recommended value for the two capacitors to ground, although = it's=20 a reasonable starting point and probably OK for most purposes. Thanks, Paul=20
Reply by ●June 7, 20132013-06-07
Martin Riddle wrote:> > "Robert Baer"<robertbaer@localnet.com> wrote in message > news:libst.7203$Zv.1563@newsfe08.iad... >> Martin Riddle wrote: >>> "P E Schoen"<paul@peschoen.com> wrote in message >>> news:kor080$vjd$1@dont-email.me... >>>> For most of my projects I use either a 14.7456 MHz crystal >>>> (57600*256) >>>> or 20.000 MHz (for USB 96 MHz 24*f/5). The 20 MHz crystal I am using >>>> specifies a 20 pF parallel load, but my boards have 12 pF >>>> capacitors. >>>> I just noticed this and I think the value had been selected for a >>>> previous brand of crystal, but the oscillator frequencies measure >>>> pretty close to the ideal value, as follows for five boards: >>>> >>>> Board 1: 20.00258 +0.013% 130PPM >>>> Board 2: 20.00039 +0.002% 20PPM >>>> Board 3: 20.00068 +0.003% 30PPM >>>> Board 4: 20.00085 +0.004% 40PPM >>>> Board 5: 20.00073 +0.004% 40PPM >>>> >>>> My specification is 0.02%, or 200 PPM, so all are within spec, but >>>> perhaps with the 20 pF capacitors the frequency will be much closer >>>> and variation will be positive and negative. But the application >>>> notes >>>> I found seem a bit confusing as to the correct way to figure the >>>> load >>>> capacitance: >>>> >>>> http://www.statek.com/pdf/tn33.pdf >>>> http://www.foxonline.com/pdfs/xtaldesignnotes.pdf >>>> http://www.oscilent.com/spec_pages/PNDescrpt/Load_Cap.htm >>>> >>>> It seems that the capacitance is determined by: >>>> >>>> CL = (CL1*CL2)/(CL1+CL2)+CS >>>> >>>> Where CL1 and CL2 are the load capacitors and CS is the stray >>>> capacitance, generally figured about 5 pF. So with my 12 pF >>>> capacitors >>>> the actual CL = 11 pF and with 20 pF capacitors CL = 15 pF and with >>>> 47 >>>> pF capacitors (as I think I used at one time), CL = 28.5 pF. The >>>> ideal >>>> value appears to be 30 pF. I don't know the actual stray >>>> capacitance, >>>> but it is a double sided board with 0805 SMT capacitors and a >>>> PIC18F4455 microcontroller in a TQFP-44 package. It has a value of >>>> 15 >>>> pF or the OSC2 pin but this is characterized for external clock >>>> drive >>>> into OSC1. >>>> >>>> I think the 12 pF capacitors are OK but I think I will try changing >>>> to >>>> 20 pF and see if the frequency comes in closer. The crystal itself >>>> is >>>> rated 30 PPM and 100 PPM over the temperature range. Except for >>>> board >>>> #1, I'm just about there. >>>> >>>> But the CL formula seems a bit strange. Usually, when I see product >>>> over sum, its square root is taken, as for parallel resistors. And >>>> if >>>> one of the capacitors is zero, the other apparently has no effect, >>>> and >>>> that just seems wrong. >>>> >>>> Paul >>> >>> See appnote 949 >>> >>> <http://ww1.microchip.com/downloads/en/AppNotes/00949a.pdf> >>> >>> Cheers >>> >>> >>> >> Does NOT give any "spec" or useful value; very good on hand-waving, >> tho. >> > > Really, computer problems again? > > > > Cheers > > >Stupid! Read the PDF, i dare you.
Reply by ●June 7, 20132013-06-07
P E Schoen wrote:> "Martin Riddle" wrote in message news:korkbr$mtc$1@dont-email.me... > >> "Robert Baer" <robertbaer@localnet.com> wrote in message >> news:libst.7203$Zv.1563@newsfe08.iad... > >>>> <http://ww1.microchip.com/downloads/en/AppNotes/00949a.pdf> > >>> Does NOT give any "spec" or useful value; very good on hand-waving, tho. > >> Really, computer problems again? > > The app note is marginally useful, but I think the easiest method is to > start with something like 18-22 pF capacitors and measure the clock > frequency directly (or better, via a separate pin derived from the > clock). At least that's what I plan to do. YMMV. > > At least I found that the load capacitance value given by the > manufacturer is NOT the recommended value for the two capacitors to > ground, although it's a reasonable starting point and probably OK for > most purposes. > > Thanks, > > PaulEXACTLY!
Reply by ●June 7, 20132013-06-07
On Fri, 07 Jun 2013 09:04:02 -0800, Robert Baer <robertbaer@localnet.com> wrote:>P E Schoen wrote: >> "Martin Riddle" wrote in message news:korkbr$mtc$1@dont-email.me... >> >>> "Robert Baer" <robertbaer@localnet.com> wrote in message >>> news:libst.7203$Zv.1563@newsfe08.iad... >> >>>>> <http://ww1.microchip.com/downloads/en/AppNotes/00949a.pdf> >> >>>> Does NOT give any "spec" or useful value; very good on hand-waving, tho. >> >>> Really, computer problems again? >> >> The app note is marginally useful, but I think the easiest method is to >> start with something like 18-22 pF capacitors and measure the clock >> frequency directly (or better, via a separate pin derived from the >> clock). At least that's what I plan to do. YMMV. >> >> At least I found that the load capacitance value given by the >> manufacturer is NOT the recommended value for the two capacitors to >> ground, although it's a reasonable starting point and probably OK for >> most purposes. >> >> Thanks, >> >> Paul > EXACTLY!The two end caps plus their strays, calculated in series, should match the manufacturer-specified "load" capacitance. The ratio affects loop gain, and can be a handy way to avoid overdrive and spurs. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85140 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●June 7, 20132013-06-07
On Thu, 06 Jun 2013 19:10:19 -0800, Robert Baer <robertbaer@localnet.com> wrote:>Martin Riddle wrote: >> "P E Schoen"<paul@peschoen.com> wrote in message >> news:kor080$vjd$1@dont-email.me... >>> For most of my projects I use either a 14.7456 MHz crystal (57600*256) >>> or 20.000 MHz (for USB 96 MHz 24*f/5). The 20 MHz crystal I am using >>> specifies a 20 pF parallel load, but my boards have 12 pF capacitors. >>> I just noticed this and I think the value had been selected for a >>> previous brand of crystal, but the oscillator frequencies measure >>> pretty close to the ideal value, as follows for five boards: >>> >>> Board 1: 20.00258 +0.013% 130PPM >>> Board 2: 20.00039 +0.002% 20PPM >>> Board 3: 20.00068 +0.003% 30PPM >>> Board 4: 20.00085 +0.004% 40PPM >>> Board 5: 20.00073 +0.004% 40PPM >>> >>> My specification is 0.02%, or 200 PPM, so all are within spec, but >>> perhaps with the 20 pF capacitors the frequency will be much closer >>> and variation will be positive and negative. But the application notes >>> I found seem a bit confusing as to the correct way to figure the load >>> capacitance: >>> >>> http://www.statek.com/pdf/tn33.pdf >>> http://www.foxonline.com/pdfs/xtaldesignnotes.pdf >>> http://www.oscilent.com/spec_pages/PNDescrpt/Load_Cap.htm >>> >>> It seems that the capacitance is determined by: >>> >>> CL = (CL1*CL2)/(CL1+CL2)+CS >>> >>> Where CL1 and CL2 are the load capacitors and CS is the stray >>> capacitance, generally figured about 5 pF. So with my 12 pF capacitors >>> the actual CL = 11 pF and with 20 pF capacitors CL = 15 pF and with 47 >>> pF capacitors (as I think I used at one time), CL = 28.5 pF. The ideal >>> value appears to be 30 pF. I don't know the actual stray capacitance, >>> but it is a double sided board with 0805 SMT capacitors and a >>> PIC18F4455 microcontroller in a TQFP-44 package. It has a value of 15 >>> pF or the OSC2 pin but this is characterized for external clock drive >>> into OSC1. >>> >>> I think the 12 pF capacitors are OK but I think I will try changing to >>> 20 pF and see if the frequency comes in closer. The crystal itself is >>> rated 30 PPM and 100 PPM over the temperature range. Except for board >>> #1, I'm just about there. >>> >>> But the CL formula seems a bit strange. Usually, when I see product >>> over sum, its square root is taken, as for parallel resistors. And if >>> one of the capacitors is zero, the other apparently has no effect, and >>> that just seems wrong.It's just Cs = 1/(1/C1 + 1/C2) = C1*C2/(C1+C2) series capacitance.>>> Paul >> >> See appnote 949 >> >> <http://ww1.microchip.com/downloads/en/AppNotes/00949a.pdf> >> >> Cheers >> >> >> > Does NOT give any "spec" or useful value; very good on hand-waving, tho.For equal caps, multiply by two and subtract 5pF, round to the nearest 5% or 10% value and you'll be close enough for a microcontroller clock xtal. Eg. 17pF->34pF-5pF = 29pF. I'd use 27pF. Sometimes start-up is enhanced by using different values for the load caps, haven't had to do that for a while (mostly because the micros and such like tend to have PLLs and/or dividers in them that allow the use of crystals in the ~4MHz-25MHz range regardless of what frequency is actually required).
Reply by ●June 7, 20132013-06-07
On Thursday, June 6, 2013 5:55:17 PM UTC-4, P E Schoen wrote:> For most of my projects I use either a 14.7456 MHz crystal (57600*256) or==20>=20 > 20.000 MHz (for USB 96 MHz 24*f/5). The 20 MHz crystal I am using specifi=es=20>=20 > a 20 pF parallel load, but my boards have 12 pF capacitors. I just notice=d=20>=20 > this and I think the value had been selected for a previous brand of=20 >=20 > crystal, but the oscillator frequencies measure pretty close to the ideal==20>=20 > value, as follows for five boards: >=20 >=20 >=20 > Board 1: 20.00258 +0.013% 130PPM >=20 > Board 2: 20.00039 +0.002% 20PPM >=20 > Board 3: 20.00068 +0.003% 30PPM >=20 > Board 4: 20.00085 +0.004% 40PPM >=20 > Board 5: 20.00073 +0.004% 40PPM >=20 >=20 >=20 > My specification is 0.02%, or 200 PPM, so all are within spec, but perhap=s=20>=20 > with the 20 pF capacitors the frequency will be much closer and variation==20>=20 > will be positive and negative. But the application notes I found seem a b=it=20>=20 > confusing as to the correct way to figure the load capacitance: >=20 >=20 >=20 > http://www.statek.com/pdf/tn33.pdf >=20 > http://www.foxonline.com/pdfs/xtaldesignnotes.pdf >=20 > http://www.oscilent.com/spec_pages/PNDescrpt/Load_Cap.htm >=20 >=20 >=20 > It seems that the capacitance is determined by: >=20 >=20 >=20 > CL =3D (CL1*CL2)/(CL1+CL2)+CS >=20 >=20 >=20 > Where CL1 and CL2 are the load capacitors and CS is the stray capacitance=,=20>=20 > generally figured about 5 pF. So with my 12 pF capacitors the actual CL ==3D 11=20>=20 > pF and with 20 pF capacitors CL =3D 15 pF and with 47 pF capacitors (as I==20>=20 > think I used at one time), CL =3D 28.5 pF. The ideal value appears to be =30=20>=20 > pF. I don't know the actual stray capacitance, but it is a double sided==20>=20 > board with 0805 SMT capacitors and a PIC18F4455 microcontroller in a TQFP=-44=20>=20 > package. It has a value of 15 pF or the OSC2 pin but this is characterize=d=20>=20 > for external clock drive into OSC1. >=20 >=20 >=20 > I think the 12 pF capacitors are OK but I think I will try changing to 20=pF=20>=20 > and see if the frequency comes in closer. The crystal itself is rated 30 =PPM=20>=20 > and 100 PPM over the temperature range. Except for board #1, I'm just abo=ut=20>=20 > there. >=20 >=20 >=20 > But the CL formula seems a bit strange. Usually, when I see product over==20>=20 > sum, its square root is taken, as for parallel resistors. And if one of t=he=20>=20 > capacitors is zero, the other apparently has no effect, and that just see=ms=20>=20 > wrong. >=20 >=20 >=20 > PaulDoesn't that thing use the Pierce topology where you have the PIC buffer ou= tput driving a 90o phase shift RC that also limits the crystal power dissip= ation as well as attenuates spurious oscillation modes, then the specified = crystal capacitance is on the PIC buffer input to GND. Usually the 90o phas= e shift C is like more than 10x the crystal C and can be neglected. Also, t= he actual C used for the crystal accounts for the PIC buffer input capacita= nce ( is that 3-7 pF range?). Board stray is parallel to all this and adds = to the physical crystal capacitors. Maybe use a trimmer on a test board an= d measure its setting when you hit the magic number. I'm pretty sure you're= not going to get standard capacitors to within 0.02% .
Reply by ●June 7, 20132013-06-07
bloggs.fredbloggs.fred@gmail.com writes:> On Thursday, June 6, 2013 5:55:17 PM UTC-4, P E Schoen wrote: >> For most of my projects I use either a 14.7456 MHz crystal (57600*256) or >> 20.000 MHz (for USB 96 MHz 24*f/5). The 20 MHz crystal I am using specifies >> a 20 pF parallel load, but my boards have 12 pF capacitors. I just noticed >> this and I think the value had been selected for a previous brand of >> crystal, but the oscillator frequencies measure pretty close to the ideal >> value, as follows for five boards: >> >> Board 1: 20.00258 +0.013% 130PPM >> Board 2: 20.00039 +0.002% 20PPM >> Board 3: 20.00068 +0.003% 30PPM >> Board 4: 20.00085 +0.004% 40PPM >> Board 5: 20.00073 +0.004% 40PPM >> >> My specification is 0.02%, or 200 PPM, so all are within spec, but perhaps >> with the 20 pF capacitors the frequency will be much closer and variation >> will be positive and negative. But the application notes I found seem a bit >> confusing as to the correct way to figure the load capacitance: >> >> http://www.statek.com/pdf/tn33.pdf >> http://www.foxonline.com/pdfs/xtaldesignnotes.pdf >> http://www.oscilent.com/spec_pages/PNDescrpt/Load_Cap.htm >> >> It seems that the capacitance is determined by: >> >> CL = (CL1*CL2)/(CL1+CL2)+CS >> >> Where CL1 and CL2 are the load capacitors and CS is the stray capacitance, >> generally figured about 5 pF. So with my 12 pF capacitors the actual CL = 11 >> pF and with 20 pF capacitors CL = 15 pF and with 47 pF capacitors (as I >> think I used at one time), CL = 28.5 pF. The ideal value appears to be 30 >> pF. I don't know the actual stray capacitance, but it is a double sided >> board with 0805 SMT capacitors and a PIC18F4455 microcontroller in a TQFP-44 >> package. It has a value of 15 pF or the OSC2 pin but this is characterized >> for external clock drive into OSC1. >> >> I think the 12 pF capacitors are OK but I think I will try changing to 20 pF >> and see if the frequency comes in closer. The crystal itself is rated 30 PPM >> and 100 PPM over the temperature range. Except for board #1, I'm just about >> there. >> >> >> >> But the CL formula seems a bit strange. Usually, when I see product over >> sum, its square root is taken, as for parallel resistors. And if one of the >> capacitors is zero, the other apparently has no effect, and that just seems >> wrong. >> >> Paul(fixed useless double spacing of lines )> Doesn't that thing use the Pierce topology where you have the PIC > buffer output driving a 90o phase shift RC that also limits the > crystal power dissipation as well as attenuates spurious oscillation > modes, then the specified crystal capacitance is on the PIC buffer > input to GND. Usually the 90o phase shift C is like more than 10x the > crystal C and can be neglected. Also, the actual C used for the > crystal accounts for the PIC buffer input capacitance ( is that 3-7 pF > range?). Board stray is parallel to all this and adds to the physical > crystal capacitors. Maybe use a trimmer on a test board and measure > its setting when you hit the magic number. I'm pretty sure you're not > going to get standard capacitors to within 0.02% .He said 0.02% for the final frequency, not the capacitance tolerance! -- John Devereux
Reply by ●June 7, 20132013-06-07
On a sunny day (Fri, 07 Jun 2013 19:55:42 +0100) it happened John Devereux <john@devereux.me.uk> wrote in <87ip1piwcx.fsf@devereux.me.uk>:>He said 0.02% for the final frequency, not the capacitance tolerance!I am missing a temperature spec in all this. When I tried to calibrate my little PIC frequency counter against a Rubidium standard by adding caps, I found that a few degrees Celsius temperature change makes a lot of difference. Zero tc caps may help, trimmers are useful as others pointed out.
Reply by ●June 7, 20132013-06-07
Fred Bloggs wrote in message=20 news:1f760b8f-e8ea-448c-b934-0ab5056c8035@googlegroups.com...> Doesn't that thing use the Pierce topology where you have the PIC =buffer=20> output driving a 90o phase shift RC that also limits the crystal power => dissipation as well as attenuates spurious oscillation modes, then the => specified crystal capacitance is on the PIC buffer input to GND. =Usually=20> the 90o phase shift C is like more than 10x the crystal C and can be=20 > neglected. Also, the actual C used for the crystal accounts for the =PIC=20> buffer input capacitance ( is that 3-7 pF range?). Board stray is =parallel=20> to all this and adds to the physical crystal capacitors. Maybe use a=20 > trimmer on a test board and measure its setting when you hit the magic => number. I'm pretty sure you're not going to get standard capacitors to => within 0.02% .Yes, it uses a Pierce oscillator: http://en.wikipedia.org/wiki/Pierce_oscillator The value of the capacitors has relatively little effect on the = frequency,=20 so a change from the 12 pF I have in the circuit now, to 27 pF (more = than 2x=20 the value, and probably close to ideal), will most likely change the=20 frequency from an average of 20.00066 (boards 2-5) to the exact value of = 20.00000, which is a change of 0.0033% or 33 PPM. So the usual 5% = capacitor=20 tolerance will have no measureable effect on the frequency. It does appear that the proper point on the curve for specified parallel = resonance is on a fairly steep slope, where a change of 10 pF can have = as=20 much as 200 PPM of frequency shift. From 50 pF to 100 pF the shift is = only=20 about 100 PPM, and flattens out at higher capacitor values, probably as = it=20 approaches series resonance. The "pullability" as stated by Fox is = expressed=20 in PPM/pF by: S =3D (C1 * 1000000) / (2 * Ct^2) where Ct is sum of Co + CL. Thus for the specified CL of 20 pF and Co of 20 pF and C1 of 27 pF this = is=20 8400 PPM/pF but this does not seem right. The design note for Statek gives TS =3D C1 / (2 * (C0+CL)^2) which is 0.0084. If that is percent, then it = would=20 be 84 PPM/pF which still seems high. However, I don't really know the = value=20 of C0. The app note further states that disregard for the trim = capacitors=20 may result in errors as much as 0.1%, or 1000 PPM, and for capacitance = range=20 of 100 pF this is more like 10 PPM/pF, which seems reasonable and is=20 supported by the published curves. Perhaps C0 is much higher than 20 pF? Paul=20
