Capacitance value for PIC crystal

Jan Panteltje <pNaonStpealmtje@yahoo.com> writes:

> On a sunny day (Fri, 07 Jun 2013 19:55:42 +0100) it happened John Devereux
> <john@devereux.me.uk> wrote in <87ip1piwcx.fsf@devereux.me.uk>:
>
>>He said 0.02% for the final frequency, not the capacitance tolerance!
>
> I am missing a temperature spec in all this.
> When I tried to calibrate my little PIC frequency counter against a Rubidium standard by adding caps,
> I found that a few degrees Celsius temperature change makes a lot of difference.
> Zero tc caps may help, trimmers are useful as others pointed out.

Caps that value are usually "zero TC" anyway aren't they? (COG). I think
it's probably more the TC of the crystal itself.

-- 

John Devereux

On 07/06/2013 20:35, Jan Panteltje wrote:
> On a sunny day (Fri, 07 Jun 2013 19:55:42 +0100) it happened John
> Devereux <john@devereux.me.uk> wrote in
> <87ip1piwcx.fsf@devereux.me.uk>:
>
>> He said 0.02% for the final frequency, not the capacitance
>> tolerance!
>
> I am missing a temperature spec in all this. When I tried to
> calibrate my little PIC frequency counter against a Rubidium standard
> by adding caps, I found that a few degrees Celsius temperature change
> makes a lot of difference. Zero tc caps may help, trimmers are useful
> as others pointed out.
>

If its a genuine AT cut crystal then I would have hoped for a quite good
performance for just a small temperature change.

http://cfm.citizen.co.jp/english/product/cvo_character.html

-- 
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

"Mike Perkins"  wrote in message=20
news:etqdnZyoWrW73S_MnZ2dnUVZ7sWdnZ2d@bt.com...

> If its a genuine AT cut crystal then I would have hoped for a quite =
good
> performance for just a small temperature change.

> http://cfm.citizen.co.jp/english/product/cvo_character.html

The ECS crystals I'm using are 100 PPM over -40 to +85 C, with initial=20
tolerance of 30 PPM. Not bad for less than a dollar:
http://www.mouser.com/ds/2/122/hc-49usx-dn-16344.pdf

You can get them with as little as 10 PPM tolerance and stability, for =
about=20
$3 each:
http://www.mouser.com/ds/2/122/ecx-32-6206.pdf

And these are impressive for about $0.40:
http://www.mouser.com/ProductDetail/ECS/ECS-200-20-1X/?qs=3DsGAEpiMZZMsBj=
6bBr9Q9aWDZfF25lWfiUcdswAjCEnw%3d

Paul=20

On Fri, 07 Jun 2013 19:35:13 +0000, Jan Panteltje wrote:

> On a sunny day (Fri, 07 Jun 2013 19:55:42 +0100) it happened John
> Devereux <john@devereux.me.uk> wrote in <87ip1piwcx.fsf@devereux.me.uk>:
> 
>>He said 0.02% for the final frequency, not the capacitance tolerance!
> 
> I am missing a temperature spec in all this. When I tried to calibrate
> my little PIC frequency counter against a Rubidium standard by adding
> caps, I found that a few degrees Celsius temperature change makes a lot
> of difference. Zero tc caps may help, trimmers are useful as others
> pointed out.

What is "a lot of difference?"

The crystal frequency as well as the parasitic capacitance of both board 
and micro will change with temperature.  You'll do better with an 
external oscillator that's rated as being way accurate (the best ones are 
ovenized, which means they're big, expensive, and power hungry -- but 
then, for timing you pays your money and you gets what you paid for).

-- 
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

On Friday, June 7, 2013 3:55:19 PM UTC-4, P E Schoen wrote:
> Fred Bloggs wrote in message=20
>=20
> news:1f760b8f-e8ea-448c-b934-0ab5056c8035@googlegroups.com...
>=20
>=20
>=20
> > Doesn't that thing use the Pierce topology where you have the PIC buffe=
r=20
>=20
> > output driving a 90o phase shift RC that also limits the crystal power=
=20
>=20
> > dissipation as well as attenuates spurious oscillation modes, then the=
=20
>=20
> > specified crystal capacitance is on the PIC buffer input to GND. Usuall=
y=20
>=20
> > the 90o phase shift C is like more than 10x the crystal C and can be=20
>=20
> > neglected. Also, the actual C used for the crystal accounts for the PIC=
=20
>=20
> > buffer input capacitance ( is that 3-7 pF range?). Board stray is paral=
lel=20
>=20
> > to all this and adds to the physical crystal capacitors.  Maybe use a=
=20
>=20
> > trimmer on a test board and measure its setting when you hit the magic=
=20
>=20
> > number. I'm pretty sure you're not going to get standard capacitors to=
=20
>=20
> > within 0.02% .
>=20
>=20
>=20
> Yes, it uses a Pierce oscillator:
>=20
> http://en.wikipedia.org/wiki/Pierce_oscillator
>=20
>=20
>=20
> The value of the capacitors has relatively little effect on the frequency=
,=20
>=20
> so a change from the 12 pF I have in the circuit now, to 27 pF (more than=
 2x=20
>=20
> the value, and probably close to ideal), will most likely change the=20
>=20
> frequency from an average of 20.00066 (boards 2-5) to the exact value of=
=20
>=20
> 20.00000, which is a change of 0.0033% or 33 PPM. So the usual 5% capacit=
or=20
>=20
> tolerance will have no measureable effect on the frequency.
>=20
>=20
>=20
> It does appear that the proper point on the curve for specified parallel=
=20
>=20
> resonance is on a fairly steep slope, where a change of 10 pF can have as=
=20
>=20
> much as 200 PPM of frequency shift. From 50 pF to 100 pF the shift is onl=
y=20
>=20
> about 100 PPM, and flattens out at higher capacitor values, probably as i=
t=20
>=20
> approaches series resonance. The "pullability" as stated by Fox is expres=
sed=20
>=20
> in PPM/pF by:
>=20
>=20
>=20
> S =3D (C1 * 1000000) / (2 * Ct^2) where Ct is sum of Co + CL.
>=20
>=20
>=20
> Thus for the specified CL of 20 pF and Co of 20 pF and C1 of 27 pF this i=
s=20
>=20
> 8400 PPM/pF but this does not seem right.
>=20
>=20
>=20
> The design note for Statek gives
>=20
>=20
>=20
> TS =3D C1 / (2 * (C0+CL)^2) which is 0.0084. If that is percent, then it =
would=20
>=20
> be 84 PPM/pF which still seems high. However, I don't really know the val=
ue=20
>=20
> of C0. The app note further states that disregard for the trim capacitors=
=20
>=20
> may result in errors as much as 0.1%, or 1000 PPM, and for capacitance ra=
nge=20
>=20
> of 100 pF this is more like 10 PPM/pF, which seems reasonable and is=20
>=20
> supported by the published curves. Perhaps C0 is much higher than 20 pF?
>=20
>=20
>=20
> Paul

Another consideration is the phase delay introduced by the gates internal t=
o the PIC. If these are running at say 10ns, that is 10/50 x 360=3D72o in a=
ddition to the 180o inversion. The Pierce allows for 90o from the crystal a=
nd points forward, so with the additional 72o, that leaves just 18o shift f=
rom the crystal. As the PIC gate Tpd moves around with temperature ( a minu=
scule amount), so does the phase shift across the crystal, and so does the =
loop frequency. If you model the crystal as series LC , all paralleled with=
 load C, with assumed Q and look at phase versus delta-f/fo, that is chnage=
 in phase as a function of ratio of frequency perturbation to resonant freq=
uency ( the most popular plot), that will give an idea of how the oscillato=
r loop frequency pulls  with its phase shift.=20
I think Co in that manufacturer's pulling equation is also called header ca=
pacitance, or the net capacitance between the metalization of the crystal a=
nd the conductive housing.

On Friday, June 7, 2013 2:55:42 PM UTC-4, John Devereux wrote:
> bloggs.fredbloggs.fred@gmail.com writes:
> 
> 
> 
> > On Thursday, June 6, 2013 5:55:17 PM UTC-4, P E Schoen wrote:
> 
> >> For most of my projects I use either a 14.7456 MHz crystal (57600*256) or 
> 
> >> 20.000 MHz (for USB 96 MHz 24*f/5). The 20 MHz crystal I am using specifies 
> 
> >> a 20 pF parallel load, but my boards have 12 pF capacitors. I just noticed 
> 
> >> this and I think the value had been selected for a previous brand of 
> 
> >> crystal, but the oscillator frequencies measure pretty close to the ideal 
> 
> >> value, as follows for five boards:
> 
> >> 
> 
> >> Board 1: 20.00258 +0.013% 130PPM
> 
> >> Board 2: 20.00039 +0.002%  20PPM
> 
> >> Board 3: 20.00068 +0.003%  30PPM
> 
> >> Board 4: 20.00085 +0.004%  40PPM
> 
> >> Board 5: 20.00073 +0.004%  40PPM
> 
> >> 
> 
> >> My specification is 0.02%, or 200 PPM, so all are within spec, but perhaps 
> 
> >> with the 20 pF capacitors the frequency will be much closer and variation 
> 
> >> will be positive and negative. But the application notes I found seem a bit 
> 
> >> confusing as to the correct way to figure the load capacitance:
> 
> >> 
> 
> >> http://www.statek.com/pdf/tn33.pdf
> 
> >> http://www.foxonline.com/pdfs/xtaldesignnotes.pdf
> 
> >> http://www.oscilent.com/spec_pages/PNDescrpt/Load_Cap.htm
> 
> >> 
> 
> >> It seems that the capacitance is determined by:
> 
> >> 
> 
> >> CL = (CL1*CL2)/(CL1+CL2)+CS
> 
> >> 
> 
> >> Where CL1 and CL2 are the load capacitors and CS is the stray capacitance, 
> 
> >> generally figured about 5 pF. So with my 12 pF capacitors the actual CL = 11 
> 
> >> pF and with 20 pF capacitors CL = 15 pF and with 47 pF capacitors (as I 
> 
> >> think I used at one time), CL = 28.5 pF. The ideal value appears to be 30 
> 
> >> pF. I don't know the actual stray capacitance, but it is a double sided 
> 
> >> board with 0805 SMT capacitors and a PIC18F4455 microcontroller in a TQFP-44 
> 
> >> package. It has a value of 15 pF or the OSC2 pin but this is characterized 
> 
> >> for external clock drive into OSC1.
> 
> >> 
> 
> >> I think the 12 pF capacitors are OK but I think I will try changing to 20 pF 
> 
> >> and see if the frequency comes in closer. The crystal itself is rated 30 PPM 
> 
> >> and 100 PPM over the temperature range. Except for board #1, I'm just about 
> 
> >> there.
> 
> >> 
> 
> >> 
> 
> >> 
> 
> >> But the CL formula seems a bit strange. Usually, when I see product over 
> 
> >> sum, its square root is taken, as for parallel resistors. And if one of the 
> 
> >> capacitors is zero, the other apparently has no effect, and that just seems 
> 
> >> wrong.
> 
> >> 
> 
> >> Paul
> 
> 
> 
> (fixed useless double spacing of lines )
> 
> 
> 
> > Doesn't that thing use the Pierce topology where you have the PIC
> 
> > buffer output driving a 90o phase shift RC that also limits the
> 
> > crystal power dissipation as well as attenuates spurious oscillation
> 
> > modes, then the specified crystal capacitance is on the PIC buffer
> 
> > input to GND. Usually the 90o phase shift C is like more than 10x the
> 
> > crystal C and can be neglected. Also, the actual C used for the
> 
> > crystal accounts for the PIC buffer input capacitance ( is that 3-7 pF
> 
> > range?). Board stray is parallel to all this and adds to the physical
> 
> > crystal capacitors.  Maybe use a trimmer on a test board and measure
> 
> > its setting when you hit the magic number. I'm pretty sure you're not
> 
> > going to get standard capacitors to within 0.02% .
> 
> 
> 
> He said 0.02% for the final frequency, not the capacitance tolerance!
> 
> 
> 
> -- 
> 
> 
> 
> John Devereux

Right , IIRC the frequency shift relative capacitance shift is desensitized by sqrt(Q)- not going to do a bunch of algebra right now.

On a sunny day (Fri, 7 Jun 2013 17:19:06 -0400) it happened "P E Schoen"
<paul@peschoen.com> wrote in <kotig8$l2a$1@dont-email.me>:

>"Mike Perkins"  wrote in message 
>news:etqdnZyoWrW73S_MnZ2dnUVZ7sWdnZ2d@bt.com...
>
>> If its a genuine AT cut crystal then I would have hoped for a quite =
>good
>> performance for just a small temperature change.
>
>> http://cfm.citizen.co.jp/english/product/cvo_character.html
>
>The ECS crystals I'm using are 100 PPM over -40 to +85 C, with initial 
>tolerance of 30 PPM. Not bad for less than a dollar:
>http://www.mouser.com/ds/2/122/hc-49usx-dn-16344.pdf
>
>You can get them with as little as 10 PPM tolerance and stability, for =
>about 
>$3 each:
>http://www.mouser.com/ds/2/122/ecx-32-6206.pdf

I was actually referring to the temperature coefficient of the caps, not the crystal.
And not sure how stable input capacitance of PIC is versus temperature.
Try heating and lowering your setup 10 degrees and see if it still meets spec.

On a sunny day (Fri, 07 Jun 2013 20:59:27 +0100) it happened John Devereux
<john@devereux.me.uk> wrote in <87ehcditeo.fsf@devereux.me.uk>:

>Jan Panteltje <pNaonStpealmtje@yahoo.com> writes:
>
>> On a sunny day (Fri, 07 Jun 2013 19:55:42 +0100) it happened John Devereux
>> <john@devereux.me.uk> wrote in <87ip1piwcx.fsf@devereux.me.uk>:
>>
>>>He said 0.02% for the final frequency, not the capacitance tolerance!
>>
>> I am missing a temperature spec in all this.
>> When I tried to calibrate my little PIC frequency counter against a Rubidium standard by adding caps,
>> I found that a few degrees Celsius temperature change makes a lot of difference.
>> Zero tc caps may help, trimmers are useful as others pointed out.
>
>Caps that value are usually "zero TC" anyway aren't they?

No no, the small disk ceramics of a few pF drift a lot.

Jan Panteltje <pNaonStpealmtje@yahoo.com> writes:

> On a sunny day (Fri, 07 Jun 2013 20:59:27 +0100) it happened John Devereux
> <john@devereux.me.uk> wrote in <87ehcditeo.fsf@devereux.me.uk>:
>
>>Jan Panteltje <pNaonStpealmtje@yahoo.com> writes:
>>
>>> On a sunny day (Fri, 07 Jun 2013 19:55:42 +0100) it happened John Devereux
>>> <john@devereux.me.uk> wrote in <87ip1piwcx.fsf@devereux.me.uk>:
>>>
>>>>He said 0.02% for the final frequency, not the capacitance tolerance!
>>>
>>> I am missing a temperature spec in all this.
>>> When I tried to calibrate my little PIC frequency counter against a Rubidium standard by adding caps,
>>> I found that a few degrees Celsius temperature change makes a lot of difference.
>>> Zero tc caps may help, trimmers are useful as others pointed out.
>>
>>Caps that value are usually "zero TC" anyway aren't they?
>
> No no, the small disk ceramics of a few pF drift a lot.

Oh, you mean those things with the wires, poking through holes in the
board!  Like they used in olden times?

-- 

John Devereux

On a sunny day (Sat, 08 Jun 2013 10:19:11 +0100) it happened John Devereux
<john@devereux.me.uk> wrote in <87a9n1hsds.fsf@devereux.me.uk>:

>Jan Panteltje <pNaonStpealmtje@yahoo.com> writes:
>
>> On a sunny day (Fri, 07 Jun 2013 20:59:27 +0100) it happened John Devereux
>> <john@devereux.me.uk> wrote in <87ehcditeo.fsf@devereux.me.uk>:
>>
>>>Jan Panteltje <pNaonStpealmtje@yahoo.com> writes:
>>>
>>>> On a sunny day (Fri, 07 Jun 2013 19:55:42 +0100) it happened John Devereux
>>>> <john@devereux.me.uk> wrote in <87ip1piwcx.fsf@devereux.me.uk>:
>>>>
>>>>>He said 0.02% for the final frequency, not the capacitance tolerance!
>>>>
>>>> I am missing a temperature spec in all this.
>>>> When I tried to calibrate my little PIC frequency counter against a Rubidium standard by adding caps,
>>>> I found that a few degrees Celsius temperature change makes a lot of difference.
>>>> Zero tc caps may help, trimmers are useful as others pointed out.
>>>
>>>Caps that value are usually "zero TC" anyway aren't they?
>>
>> No no, the small disk ceramics of a few pF drift a lot.
>
>Oh, you mean those things with the wires, poking through holes in the
>board!  Like they used in olden times?

Yep, as I used here:
 http://panteltje.com/panteltje/pic/freq_pic/frequency_meter_before_closing_case_img_1536.jpg