On Tue, 22 Mar 2011 13:12:11 -0700 (PDT), john1987 <conphiloso@hotmail.com> wrote:>Hi, > >Can you advice schematic or a sketch? > >JohnAfter a while. Right now I must do some fabric marking for SWMBO'd ;-) ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Remember: Once you go over the hill, you pick up speed
PSoC or FPGA?
Started by ●March 20, 2011
Reply by ●March 22, 20112011-03-22
Reply by ●March 22, 20112011-03-22
On 03/22/2011 11:40 AM, john1987 wrote:> Hi, > > Please check the following link > > http://img138.imageshack.us/img138/271/62661460.jpg > > or > > http://img138.imageshack.us/i/62661460.jpg/ > > The thing is that I got only two wires coming out of the 7805 and I > want to power up the circuit with it and than also want to charge the > 12 volt battery throught the same two wires.Offcourse the circuit or > the charger, only one will be connected at one time. They will not be > connected together at the same time. But I need to avoid 7805. Can a > four diode bridge work, if yes than how?So, that's exactly what Dave has provided you a circuit to do. What don't you like about it? I might have put D2 between the output of U1 and the common between D1 and the connector -- that would be the most conservative way to make sure you don't damage the regulator, and if you're concerned about the diode drop you can fix it with a diode in the ground lead of the regulator. But I think Dave's circuit should work -- check your device data sheet to see if it says anything about the reverse voltage between Vout and Vin. This is, by the way, an incredibly inefficient way to power electronics from a battery. You'd be much better off with a switching regulator instead of the 7805; with just a bit of care you could configure it to turn off altogether when Vout raises above 5V after which power would go to your charging circuit. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●March 22, 20112011-03-22
On 03/22/2011 01:18 PM, whit3rd wrote:> On Monday, March 21, 2011 1:44:16 PM UTC-7, john1987 wrote: > >> I need to connect a 12 volts DC lead acid battery to a circuit. The >> circuit draws 100mA and works at 3.3V. ... The >> Circuit and the battery charger both have same input power connector >> on them and the battery has the mating connector for both of them. > > If the battery (12V) connects to a charger (12 to 15V) on the identical > connector that a 3.3V circuit uses, you ought to redesign the system > so those are NOT possible to interconnect. > > Or, maybe your '3.3V circuit' includes all the necessary stepdown > regulators to safely connect to higher voltages?Well, he's got something like a female connector on the battery and male connectors on both the circuit and the charger, so it's not that bad. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●March 22, 20112011-03-22
john1987 wrote:> Hi, > > I need to connect a 12 volts DC lead acid battery to a circuit. The > circuit draws 100mA and works at 3.3V. I am planning to use 7805 to > drop the voltage from 12 to 5 volts. > > The first thing is that how can I bypass the 7805 while charging the > battery? > > The thing is that I also needs to recharge the battery too. The > Circuit and the battery charger both have same input power connector > on them and the battery has the mating connector for both of them. > > > > Thanks > John,dump the 7805 and use a zener diode
Reply by ●March 22, 20112011-03-22
On Tue, 22 Mar 2011 10:14:37 GMT, Jan Panteltje <pNaonStpealmtje@yahoo.com> wrote:>On a sunny day (Mon, 21 Mar 2011 18:13:19 -0500) it happened >izzzzzzzzzzzzzzzzzzzzzzzz> wrote: >>Wow! You got that right. I don't WRITE CODE, > >Yea, that was clear already. >Moron, I'm hardware engineer. Software is for dweebs.
Reply by ●March 22, 20112011-03-22
On Tue, 22 Mar 2011 03:09:44 -0700, Jon Kirwan <jonk@infinitefactors.org> wrote:>On Tue, 22 Mar 2011 07:20:06 +0100, Frank Buss ><fb@frank-buss.de> wrote: > >>Jon Kirwan wrote: >> >>> That's good. What about the tools needed to load, modify, >>> and recompile with it? It looks like the EDS is free: >>> >>> http://www.altera.com/products/ip/processors/nios2/tools/ni2-development_tools.html >>> >>> But have you gone through the steps? Is the Eclipse IDE also >>> free? (I'm not sure yet from a quick scan, but need to spend >>> more time I suppose.) >> >>Yes, I have tested it with my old T-Rex board and it works. I can create >>a NIOS II CPU with the free NIOS II EDS is and Quartus II Web Edition. >>The economy version is not crypted anymore, so you can see all the >>generated VHDL code for the CPU (doesn't look good, as usual for >>generated code) and the peripherals. If you choose the larger NIOS II >>CPU models, it will be crypted and time limited and you have to buy a >>license. > >Okay. I'll take a crack at it. I've an older xilinx 4000 >series board I used to learn VHDL and _some_ floorplanning >skills for fun. Been a while, though. It is worth another >go. (Never did try verilog, yet.) > >I enjoyed struggling to develop a tiny cpu and achieved some >modest success -- succeeded on a reasonably useful ALU and >learned a little about carry forward vs ripple carry and >about booth's divider, for example.That stuff is interesting in itself but not of much use when designing with FPGAs. FPGA architecture favors certain types of adders. It's rare that you'll beat synthesis for an ALU. As far as more complex functions like multipliers and dividers, the manufacturer's libraries are also going to be hard to beat.>This sounds like still more cheap fun, though I wonder if >each cell in the Altera devices are as fancy as the xilinx >4000 cells were.Modern devices are *way* beyond where the Xilinx 4Ks were. The Altera and Xilinx FPGA logic elements are pretty similar (their CPLDs are quite different).>Question is, do I have time right now? Maybe.Always a good question. Priorities. <...>
Reply by ●March 22, 20112011-03-22
On 23/03/2011 4:40 AM, john1987 wrote:> Hi, > > Please check the following link > > http://img138.imageshack.us/img138/271/62661460.jpg > > or > > http://img138.imageshack.us/i/62661460.jpg/ > > The thing is that I got only two wires coming out of the 7805 and I > want to power up the circuit with it and than also want to charge the > 12 volt battery throught the same two wires.Offcourse the circuit or > the charger, only one will be connected at one time. They will not be > connected together at the same time. But I need to avoid 7805. Can a > four diode bridge work, if yes than how? > > Thanks > Johnjust replace d2,d3,x1 in my schematic with short circuits.
Reply by ●March 22, 20112011-03-22
john1987 wrote:> The battery has a connector A on it. The circuit and the battery > charger has connector B on them. Connector A is a mate of connector B. > The battery is 12 volts goes into 7805 the out put of the > 7805( connector A) goes into the circuit that has the voltage > regulator that outputs 3.3 volts. > > Now , I want the user to plug in the battery into the circuit and when > battery gets dischagred he / she can plug the batter into its charger. > but 7805 is there now in the middle of the battery and the battery > charger. So, how to solve this problem. > > Thanks > John+-------------|<------------+ | | +--------[in7805out]--->|---+ ------- | Gnd | | | + | | +---A B---|Charger| [Batt] | +---A B---| | - | | | ------- | | | +-------------+-------------+ That's the "standard" way to protect a 3 terminal regulator that might see a voltage coming in to its output terminal. Ed
Reply by ●March 22, 20112011-03-22
On Tue, 22 Mar 2011 18:24:14 -0500, "krw@att.bizzzzzzzzzzzz" <krw@att.bizzzzzzzzzzzz> wrote:>On Tue, 22 Mar 2011 03:09:44 -0700, Jon Kirwan <jonk@infinitefactors.org> >wrote: > >>On Tue, 22 Mar 2011 07:20:06 +0100, Frank Buss >><fb@frank-buss.de> wrote: >> >>>Jon Kirwan wrote: >>> >>>> That's good. What about the tools needed to load, modify, >>>> and recompile with it? It looks like the EDS is free: >>>> >>>> http://www.altera.com/products/ip/processors/nios2/tools/ni2-development_tools.html >>>> >>>> But have you gone through the steps? Is the Eclipse IDE also >>>> free? (I'm not sure yet from a quick scan, but need to spend >>>> more time I suppose.) >>> >>>Yes, I have tested it with my old T-Rex board and it works. I can create >>>a NIOS II CPU with the free NIOS II EDS is and Quartus II Web Edition. >>>The economy version is not crypted anymore, so you can see all the >>>generated VHDL code for the CPU (doesn't look good, as usual for >>>generated code) and the peripherals. If you choose the larger NIOS II >>>CPU models, it will be crypted and time limited and you have to buy a >>>license. >> >>Okay. I'll take a crack at it. I've an older xilinx 4000 >>series board I used to learn VHDL and _some_ floorplanning >>skills for fun. Been a while, though. It is worth another >>go. (Never did try verilog, yet.) >> >>I enjoyed struggling to develop a tiny cpu and achieved some >>modest success -- succeeded on a reasonably useful ALU and >>learned a little about carry forward vs ripple carry and >>about booth's divider, for example. > >That stuff is interesting in itself but not of much use when designing with >FPGAs. FPGA architecture favors certain types of adders. It's rare that >you'll beat synthesis for an ALU. As far as more complex functions like >multipliers and dividers, the manufacturer's libraries are also going to be >hard to beat.I am doing none of this for professional work -- I just enjoy learning, a lot. I want to know how to do things simply because I enjoy the process. Which means that I'd love to learn from the libraries of others, but I also need to learn to walk, first, so that I can place what I learn from professionals into a better contextual frame. In any case, this kind of thing is pure joy to me.>>This sounds like still more cheap fun, though I wonder if >>each cell in the Altera devices are as fancy as the xilinx >>4000 cells were. > >Modern devices are *way* beyond where the Xilinx 4Ks were. The Altera and >Xilinx FPGA logic elements are pretty similar (their CPLDs are quite >different).I need to revisit, obviously.>>Question is, do I have time right now? Maybe. > >Always a good question. Priorities.Hehe. Jon
Reply by ●March 22, 20112011-03-22
On Tue, 22 Mar 2011 17:51:01 -0700, Jon Kirwan <jonk@infinitefactors.org> wrote:>On Tue, 22 Mar 2011 18:24:14 -0500, "krw@att.bizzzzzzzzzzzz" ><krw@att.bizzzzzzzzzzzz> wrote: > >>On Tue, 22 Mar 2011 03:09:44 -0700, Jon Kirwan <jonk@infinitefactors.org> >>wrote: >> >>>On Tue, 22 Mar 2011 07:20:06 +0100, Frank Buss >>><fb@frank-buss.de> wrote: >>> >>>>Jon Kirwan wrote: >>>> >>>>> That's good. What about the tools needed to load, modify, >>>>> and recompile with it? It looks like the EDS is free: >>>>> >>>>> http://www.altera.com/products/ip/processors/nios2/tools/ni2-development_tools.html >>>>> >>>>> But have you gone through the steps? Is the Eclipse IDE also >>>>> free? (I'm not sure yet from a quick scan, but need to spend >>>>> more time I suppose.) >>>> >>>>Yes, I have tested it with my old T-Rex board and it works. I can create >>>>a NIOS II CPU with the free NIOS II EDS is and Quartus II Web Edition. >>>>The economy version is not crypted anymore, so you can see all the >>>>generated VHDL code for the CPU (doesn't look good, as usual for >>>>generated code) and the peripherals. If you choose the larger NIOS II >>>>CPU models, it will be crypted and time limited and you have to buy a >>>>license. >>> >>>Okay. I'll take a crack at it. I've an older xilinx 4000 >>>series board I used to learn VHDL and _some_ floorplanning >>>skills for fun. Been a while, though. It is worth another >>>go. (Never did try verilog, yet.) >>> >>>I enjoyed struggling to develop a tiny cpu and achieved some >>>modest success -- succeeded on a reasonably useful ALU and >>>learned a little about carry forward vs ripple carry and >>>about booth's divider, for example. >> >>That stuff is interesting in itself but not of much use when designing with >>FPGAs. FPGA architecture favors certain types of adders. It's rare that >>you'll beat synthesis for an ALU. As far as more complex functions like >>multipliers and dividers, the manufacturer's libraries are also going to be >>hard to beat. > >I am doing none of this for professional work -- I just enjoy >learning, a lot. I want to know how to do things simply >because I enjoy the process. Which means that I'd love to >learn from the libraries of others, but I also need to learn >to walk, first, so that I can place what I learn from >professionals into a better contextual frame.Understood, I just wanted to make the point that while this stuff is useful to know, it doesn't have much application in FPGAs. ASIC design is a whole 'nuther kettle. FPGA, in this way, are much more restrictive.>In any case, this kind of thing is pure joy to me.It's even more fun when you can get someone to pay you to do it. ;-)>>>This sounds like still more cheap fun, though I wonder if >>>each cell in the Altera devices are as fancy as the xilinx >>>4000 cells were. >> >>Modern devices are *way* beyond where the Xilinx 4Ks were. The Altera and >>Xilinx FPGA logic elements are pretty similar (their CPLDs are quite >>different). > >I need to revisit, obviously.Indeed. The first time I saw carry chains, I said "yech, carry chains?". I finally had to suck it up and admit that a ripple counter was faster than the fancier counters, so why knock myself out. Besides, the carry chains are quite hand for other functions. ;-)>>>Question is, do I have time right now? Maybe. >> >>Always a good question. Priorities. > >Hehe.;-)
