torsdag den 4. januar 2024 kl. 03.10.48 UTC+1 skrev Anthony William Sloman:> On Thursday, January 4, 2024 at 10:57:28 AM UTC+11, Lasse Langwadt Christensen wrote: > > torsdag den 4. januar 2024 kl. 00.42.02 UTC+1 skrev john larkin: > > > On Wed, 3 Jan 2024 12:44:24 -0800 (PST), Lasse Langwadt Christensen > > > <lang...@fonz.dk> wrote: onsdag den 3. januar 2024 kl. 20.29.19 UTC+1 skrev john larkin: > > > >> There is a new-to-me power supply architecture, an H-bridge driving a > > > >> load, but with the phases on the two sides slid around to control > > > >> delivered power. TI does that in some chips, like UCC2895. I may have > > > >> seen the architecture first in this ng. > > > >> > > > >> Anyhow, I was thinking about a high-voltage power supply with the > > > >> phase-shifted bridge driving a series-resonant transformer. > > > >> > > > >> https://www.dropbox.com/scl/fi/tbiioti0gt2emknjc61p7/Res_HV_Supply.jpg?rlkey=f1gryr8vr4jdu2y46wsz6ch2k&raw=1 > > > >> > > > >> I wonder if one of the cores of an RP2040 could do this without an > > > >> FPGA. It would of course need a voltage feedback loop in software too. > > > > > > > >should easily do that with the PIOs > > > If I did a 2-channel HV supply, that would need, I guess, three square > > > waves. On as the "reference" side of both supplies, and then a phase > > > shiftable square wave for each supply. > > > > > > The frequency might be, say, 50 to 100 KHz and I'd want to shift the > > > phases with 10s of ns resolution. Probably needs an FPGA. > > PIOs run at the full up to 133MHz pico clock > https://www.onsemi.com/pdf/datasheet/mc100ep196-d.pdf > > offers up to 10.6nsec digitally tunable in steps of 10ps and is analog fine tunable below that. Similar parts from Motorola date back to about the early 1990's. The delay has some temperature drift, but if you are fine tuning for a specific output voltage the feedback loop can take that out. >and what would you use that for?
HV power supply maybe
Started by ●January 3, 2024
Reply by ●January 4, 20242024-01-04
Reply by ●January 4, 20242024-01-04
On Thu, 4 Jan 2024 01:16:01 -0800 (PST), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>torsdag den 4. januar 2024 kl. 03.10.48 UTC+1 skrev Anthony William Sloman: >> On Thursday, January 4, 2024 at 10:57:28?AM UTC+11, Lasse Langwadt Christensen wrote: >> > torsdag den 4. januar 2024 kl. 00.42.02 UTC+1 skrev john larkin: >> > > On Wed, 3 Jan 2024 12:44:24 -0800 (PST), Lasse Langwadt Christensen >> > > <lang...@fonz.dk> wrote: onsdag den 3. januar 2024 kl. 20.29.19 UTC+1 skrev john larkin: >> > > >> There is a new-to-me power supply architecture, an H-bridge driving a >> > > >> load, but with the phases on the two sides slid around to control >> > > >> delivered power. TI does that in some chips, like UCC2895. I may have >> > > >> seen the architecture first in this ng. >> > > >> >> > > >> Anyhow, I was thinking about a high-voltage power supply with the >> > > >> phase-shifted bridge driving a series-resonant transformer. >> > > >> >> > > >> https://www.dropbox.com/scl/fi/tbiioti0gt2emknjc61p7/Res_HV_Supply.jpg?rlkey=f1gryr8vr4jdu2y46wsz6ch2k&raw=1 >> > > >> >> > > >> I wonder if one of the cores of an RP2040 could do this without an >> > > >> FPGA. It would of course need a voltage feedback loop in software too. >> > > > >> > > >should easily do that with the PIOs >> > > If I did a 2-channel HV supply, that would need, I guess, three square >> > > waves. On as the "reference" side of both supplies, and then a phase >> > > shiftable square wave for each supply. >> > > >> > > The frequency might be, say, 50 to 100 KHz and I'd want to shift the >> > > phases with 10s of ns resolution. Probably needs an FPGA. >> > PIOs run at the full up to 133MHz pico clock >> https://www.onsemi.com/pdf/datasheet/mc100ep196-d.pdf >> >> offers up to 10.6nsec digitally tunable in steps of 10ps and is analog fine tunable below that. Similar parts from Motorola date back to about the early 1990's. The delay has some temperature drift, but if you are fine tuning for a specific output voltage the feedback loop can take that out. >> > >and what would you use that for?The idea of using a bunch of obsolete ECL glue logic is, well, unreasonable. Those old ECL delay lines were terrible anyhow. That one costs about 20x an RP2040 and uses more power. Can an RP2040 timer block run at 130 MHz? I should look that up. They are pretty fancy. I don't think that even a dedicated CPU core could make my phase shifted bridge drives with code bit-banging ports.
Reply by ●January 4, 20242024-01-04
torsdag den 4. januar 2024 kl. 00.54.19 UTC+1 skrev john larkin:> On Wed, 3 Jan 2024 15:41:57 -0800 (PST), Lasse Langwadt Christensen > <lang...@fonz.dk> wrote: > > >onsdag den 3. januar 2024 kl. 20.29.19 UTC+1 skrev john larkin: > >> There is a new-to-me power supply architecture, an H-bridge driving a > >> load, but with the phases on the two sides slid around to control > >> delivered power. TI does that in some chips, like UCC2895. I may have > >> seen the architecture first in this ng. > >> > >> Anyhow, I was thinking about a high-voltage power supply with the > >> phase-shifted bridge driving a series-resonant transformer. > >> > >> https://www.dropbox.com/scl/fi/tbiioti0gt2emknjc61p7/Res_HV_Supply.jpg?rlkey=f1gryr8vr4jdu2y46wsz6ch2k&raw=1 > >> > >> I wonder if one of the cores of an RP2040 could do this without an > >> FPGA. It would of course need a voltage feedback loop in software too. > > > >I wonder if regular pwm into an FF clocked by raising and one FF clocked by falling give you the two signals? > Yeah, the RP2040 has some fancy counter-timers. Maybe they can do it, > possibly with a little help.afaict from skimming the manual the PWM peripheral can do it directly if you an do it with a pwm clock less that sysclk (125MHz) and only changing the phase by one cycle at a time set two PWM slices to 50% duty cycle, each with the same clock divider. enable both simultaneously using the PH_ADV and PH_RET bits in one of the slices that slice can then be advanced/retarded in steps by adding/skipping a clock cycle into the divider
Reply by ●January 4, 20242024-01-04
On Wednesday 3 January 2024 at 20:29:19 UTC+1, john larkin wrote:> There is a new-to-me power supply architecture, an H-bridge driving a > load, but with the phases on the two sides slid around to control > delivered power. TI does that in some chips, like UCC2895. I may have > seen the architecture first in this ng. > > Anyhow, I was thinking about a high-voltage power supply with the > phase-shifted bridge driving a series-resonant transformer. > > https://www.dropbox.com/scl/fi/tbiioti0gt2emknjc61p7/Res_HV_Supply.jpg?rlkey=f1gryr8vr4jdu2y46wsz6ch2k&raw=1 > > I wonder if one of the cores of an RP2040 could do this without an > FPGA. It would of course need a voltage feedback loop in software too.The phase shifted halfbridge has some quirks. Voltage and current rating needs to be higher, but since this is akin to an LLC, that would need to be checked anyway. Also, beware of startup conditions, since device stresses are much larger if you are not careful about how you start. As far as I remember, for resonant switching, the phase shifted bridge needs more time for the magnetising inductance to freewheel the switch node voltage.
Reply by ●January 5, 20242024-01-05
On Thursday, January 4, 2024 at 8:16:06 PM UTC+11, Lasse Langwadt Christensen wrote:> torsdag den 4. januar 2024 kl. 03.10.48 UTC+1 skrev Anthony William Sloman: > > On Thursday, January 4, 2024 at 10:57:28 AM UTC+11, Lasse Langwadt Christensen wrote: > > > torsdag den 4. januar 2024 kl. 00.42.02 UTC+1 skrev john larkin: > > > > On Wed, 3 Jan 2024 12:44:24 -0800 (PST), Lasse Langwadt Christensen > > > > <lang...@fonz.dk> wrote: onsdag den 3. januar 2024 kl. 20.29.19 UTC+1 skrev john larkin: > > > > >> There is a new-to-me power supply architecture, an H-bridge driving a > > > > >> load, but with the phases on the two sides slid around to control > > > > >> delivered power. TI does that in some chips, like UCC2895. I may have > > > > >> seen the architecture first in this ng. > > > > >> > > > > >> Anyhow, I was thinking about a high-voltage power supply with the > > > > >> phase-shifted bridge driving a series-resonant transformer. > > > > >> > > > > >> https://www.dropbox.com/scl/fi/tbiioti0gt2emknjc61p7/Res_HV_Supply.jpg?rlkey=f1gryr8vr4jdu2y46wsz6ch2k&raw=1 > > > > >> > > > > >> I wonder if one of the cores of an RP2040 could do this without an > > > > >> FPGA. It would of course need a voltage feedback loop in software too. > > > > > > > > > >should easily do that with the PIOs > > > > If I did a 2-channel HV supply, that would need, I guess, three square > > > > waves. On as the "reference" side of both supplies, and then a phase > > > > shiftable square wave for each supply. > > > > > > > > The frequency might be, say, 50 to 100 KHz and I'd want to shift the > > > > phases with 10s of ns resolution. Probably needs an FPGA. > > > PIOs run at the full up to 133MHz pico clock > > https://www.onsemi.com/pdf/datasheet/mc100ep196-d.pdf > > > > offers up to 10.6nsec digitally tunable in steps of 10ps and is analog fine tunable below that. Similar parts from Motorola date back to about the early 1990's. The delay has some temperature drift, but if you are fine tuning for a specific output voltage the feedback loop can take that out. > > > and what would you use that for?Fine control of the male-to-space ratio. I did think that was obvious. -- Bill Sloman, Sydney
Reply by ●January 5, 20242024-01-05
On a sunny day (Wed, 03 Jan 2024 11:29:02 -0800) it happened john larkin <jl@650pot.com> wrote in <olcbpihia58uugpv9g3ptumif14qru2007@4ax.com>:> >There is a new-to-me power supply architecture, an H-bridge driving a >load, but with the phases on the two sides slid around to control >delivered power. TI does that in some chips, like UCC2895. I may have >seen the architecture first in this ng. > >Anyhow, I was thinking about a high-voltage power supply with the >phase-shifted bridge driving a series-resonant transformer. > >https://www.dropbox.com/scl/fi/tbiioti0gt2emknjc61p7/Res_HV_Supply.jpg?rlkey=f1gryr8vr4jdu2y46wsz6ch2k&raw=1Is it not much simpler to drive a capacitor with L to ground from a complementary output stage? + | T1 | C1 D1 |------||-------|>|---------- | | | T2 L1 === | | --- C2 : | | /// /// /// Now Q of C1 L1 and load sets the voltage, no transformer needed. Simple PIC micro can drive that.>I wonder if one of the cores of an RP2040 could do this without an >FPGA. It would of course need a voltage feedback loop in software too.PIC micro. Has hardware PWM generator and comparators that can directly switch the PWM off. Used many times.
Reply by ●January 5, 20242024-01-05
On Fri, 05 Jan 2024 04:18:40 GMT, Jan Panteltje <pNaonStpealmtje@yahoo.com> wrote:>On a sunny day (Wed, 03 Jan 2024 11:29:02 -0800) it happened john larkin ><jl@650pot.com> wrote in <olcbpihia58uugpv9g3ptumif14qru2007@4ax.com>: > >> >>There is a new-to-me power supply architecture, an H-bridge driving a >>load, but with the phases on the two sides slid around to control >>delivered power. TI does that in some chips, like UCC2895. I may have >>seen the architecture first in this ng. >> >>Anyhow, I was thinking about a high-voltage power supply with the >>phase-shifted bridge driving a series-resonant transformer. >> >>https://www.dropbox.com/scl/fi/tbiioti0gt2emknjc61p7/Res_HV_Supply.jpg?rlkey=f1gryr8vr4jdu2y46wsz6ch2k&raw=1 > >Is it not much simpler to drive a capacitor with L to ground from a complementary output stage? > > + > | > T1 > | C1 D1 > |------||-------|>|---------- > | | | > T2 L1 === > | | --- C2 > : | | >/// /// /// > >Now Q of C1 L1 and load sets the voltage, no transformer needed. >Simple PIC micro can drive that.The transformer provides step-up and isolation. I kind of like the full-bridge drive, to put 48 volts p-p into the transformer primary circuit.> >>I wonder if one of the cores of an RP2040 could do this without an >>FPGA. It would of course need a voltage feedback loop in software too. > >PIC micro. >Has hardware PWM generator and comparators that can directly switch the PWM off. >Used many times.I'm plannng to use RP2040 in this product line.
Reply by ●January 5, 20242024-01-05
On 5/01/2024 4:17 am, John Larkin wrote:> On Thu, 4 Jan 2024 01:16:01 -0800 (PST), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > >> torsdag den 4. januar 2024 kl. 03.10.48 UTC+1 skrev Anthony William Sloman: >>> On Thursday, January 4, 2024 at 10:57:28?AM UTC+11, Lasse Langwadt Christensen wrote: >>>> torsdag den 4. januar 2024 kl. 00.42.02 UTC+1 skrev john larkin: >>>>> On Wed, 3 Jan 2024 12:44:24 -0800 (PST), Lasse Langwadt Christensen >>>>> <lang...@fonz.dk> wrote: onsdag den 3. januar 2024 kl. 20.29.19 UTC+1 skrev john larkin: >>>>>>> There is a new-to-me power supply architecture, an H-bridge driving a >>>>>>> load, but with the phases on the two sides slid around to control >>>>>>> delivered power. TI does that in some chips, like UCC2895. I may have >>>>>>> seen the architecture first in this ng. >>>>>>> >>>>>>> Anyhow, I was thinking about a high-voltage power supply with the >>>>>>> phase-shifted bridge driving a series-resonant transformer. >>>>>>> >>>>>>> https://www.dropbox.com/scl/fi/tbiioti0gt2emknjc61p7/Res_HV_Supply.jpg?rlkey=f1gryr8vr4jdu2y46wsz6ch2k&raw=1 >>>>>>> >>>>>>> I wonder if one of the cores of an RP2040 could do this without an >>>>>>> FPGA. It would of course need a voltage feedback loop in software too. >>>>>> >>>>>> should easily do that with the PIOs >>>>> If I did a 2-channel HV supply, that would need, I guess, three square >>>>> waves. On as the "reference" side of both supplies, and then a phase >>>>> shiftable square wave for each supply. >>>>> >>>>> The frequency might be, say, 50 to 100 KHz and I'd want to shift the >>>>> phases with 10s of ns resolution. Probably needs an FPGA. >>>> PIOs run at the full up to 133MHz pico clock >>> https://www.onsemi.com/pdf/datasheet/mc100ep196-d.pdf >>> >>> offers up to 10.6nsec digitally tunable in steps of 10ps and is analog fine tunable below that. Similar parts from Motorola date back to about the early 1990's. The delay has some temperature drift, but if you are fine tuning for a specific output voltage the feedback loop can take that out. >>> >> >> and what would you use that for?Fine control of the mark-to-space ratio, as should have been obvious.> The idea of using a bunch of obsolete ECL glue logic is, well, > unreasonable.The MC100EP196 is a clock timing control part - not "glue logic" - and Mouser have 493 in stock so it doesn't seem to be obsolete.> > Those old ECL delay lines were terrible anyhow. That one costs about 20x an RP2040 and uses more power.But they can drive properly terminated transmission lines, and if you are relying on fine control of mark-to-space ratio you don't want reflections moving the switching edges around.> Can an RP2040 timer block run at 130 MHz? I should look that up. They > are pretty fancy. I don't think that even a dedicated CPU core could > make my phase shifted bridge drives with code bit-banging ports.But even at 130MHz a counter-based timer has a granularity of 7.7nsec. The MC100EP195 gets that down to 10psec. -- Bill Sloman, Sydney
Reply by ●January 5, 20242024-01-05
On a sunny day (Thu, 04 Jan 2024 20:59:16 -0800) it happened John Larkin <jl@997PotHill.com> wrote in <in2fpitju1b2163tpb5qhmhs97qeufvu4m@4ax.com>:>On Fri, 05 Jan 2024 04:18:40 GMT, Jan Panteltje ><pNaonStpealmtje@yahoo.com> wrote: > >>On a sunny day (Wed, 03 Jan 2024 11:29:02 -0800) it happened john larkin >><jl@650pot.com> wrote in <olcbpihia58uugpv9g3ptumif14qru2007@4ax.com>: >> >>> >>>There is a new-to-me power supply architecture, an H-bridge driving a >>>load, but with the phases on the two sides slid around to control >>>delivered power. TI does that in some chips, like UCC2895. I may have >>>seen the architecture first in this ng. >>> >>>Anyhow, I was thinking about a high-voltage power supply with the >>>phase-shifted bridge driving a series-resonant transformer. >>> >>>https://www.dropbox.com/scl/fi/tbiioti0gt2emknjc61p7/Res_HV_Supply.jpg?rlkey=f1gryr8vr4jdu2y46wsz6ch2k&raw=1 >> >>Is it not much simpler to drive a capacitor with L to ground from a complementary output stage? >> >> + >> | >> T1 >> | C1 D1 >> |------||-------|>|---------- >> | | | >> T2 L1 === >> | | --- C2 >> : | | >>/// /// /// >> >>Now Q of C1 L1 and load sets the voltage, no transformer needed. >>Simple PIC micro can drive that. > >The transformer provides step-up and isolation.That circuit has both sides connected to ground? Or is that not a ground on V1 negative supply?>I kind of like the >full-bridge drive, to put 48 volts p-p into the transformer primary >circuit.Yes, all depends on the amount of power needed...>> >>>I wonder if one of the cores of an RP2040 could do this without an >>>FPGA. It would of course need a voltage feedback loop in software too. >> >>PIC micro. >>Has hardware PWM generator and comparators that can directly switch the PWM off. >>Used many times. > >I'm plannng to use RP2040 in this product line.If more tasks are needed and that RP2040 has a hardware facility to make PWM yes If not using a PIC is simple, interrupt increments a counter, sets a pin, again counter resets a pin. Or use the build in PWM generator. Main routine reads ADCs sets counter values. drives an LCD, etc... The 18F14K22 has 4 ADCs, a hardware comparator (for cycle by cycle current liming for example), 64 MHz internal PLL clock.. This uses the PIC's PWM generator: https://panteltje.online/panteltje/pic/pwr_pic/power_box_diagram_img_1817.jpg use ctrl+ in browser to enlarge and read circuit diagram. I use a current transformer to sense transistor current and trigger the PIC hardware comparator making the cycle by cycle urrent protection. The PIC ADCs read current and voltage and display it on an LCD, no interrupst anywhere needed. http://panteltje.online/panteltje/pic/pwr_pic/ You could reduce diode voltage drop, think I got the idea here in this group? https://panteltje.online/pub/power_pic/power_pic_synchronous_rectifier_diagram_img_0968.jpg https://panteltje.online/pub/power_pic/power_pic_synchronous_rectifier_working_img_0965.jpg
Reply by ●January 5, 20242024-01-05
On Wed, 03 Jan 2024 11:29:02 -0800, john larkin <jl@650pot.com> wrote:> >There is a new-to-me power supply architecture, an H-bridge driving a >load, but with the phases on the two sides slid around to control >delivered power. TI does that in some chips, like UCC2895. I may have >seen the architecture first in this ng. > >Anyhow, I was thinking about a high-voltage power supply with the >phase-shifted bridge driving a series-resonant transformer. > >https://www.dropbox.com/scl/fi/tbiioti0gt2emknjc61p7/Res_HV_Supply.jpg?rlkey=f1gryr8vr4jdu2y46wsz6ch2k&raw=1 > >I wonder if one of the cores of an RP2040 could do this without an >FPGA. It would of course need a voltage feedback loop in software too. >If you're driving a load, you'll be dealing with large common-mode components. If you're driving an isolation transformer, this won't be a major issue. RL
