On 2022-11-06 22:48, Lamont Cranston wrote:> On Sunday, November 6, 2022 at 2:59:07 PM UTC-6, Leo Baumann wrote: >> Am 06.11.2022 um 21:54 schrieb Lamont Cranston: >>> Because there is no data on the BF256C, and this fellow says there is a 17 x attenuation, >>> that would make it 5.1pf of gate capacitance. >> The gate-capacitance of a sFET BF256C is about 0.8 pF. > > Do you have a reference for that? > > I get 15.4 attenuation ratio, input to the source of the fet @1MHz. > https://www.dropbox.com/s/5oud5mbdu45o73i/Kleijer%27s%20input%20circuit.jpg?dl=0 > The fet source goes to a 100nF cap and about 500Ω to ground. > Mikek >I see no reason why this wouldn't work, if constructed correctly. It's a source follower followed by an emitter follower, so we expect a gain a little below unity. The gate is biased to 9V or so, but you shouldn't try to measure that directly because the DC impedance is too high. The source should be a little above that, 11v maybe, and the NPN emitter about 0.7V below that. You *can* measure that: The impedance there is low enough. The drain resistor drops about 11V, same as the source resistor, so that Vds ends up about 8V, a tad high, but acceptable. There's 200mW dissipated in the NPN, so it will get hot, probably too hot. Increasing the emitter resistor would help. Adding a resistor in the collector lead would help too. Bypass the collector to GND if you do that. With a 30V overall supply voltage, I'd probably make it rise gently, to prevent transients stressing the semiconductors. The two capacitors going back from the NPN emitter are bootstraps, the top one reducing the effect of Cgd of the JFET, and the bottom one increasing the effective impedance of the gate resistor. I'd expect the input impedance to be in the 100 MOhm ballpark in parallel with a fraction of a pF. Any additional capacitive stuff hanging on the input, tracks, pads, connectors, cables, whatnot, adds to that, of course. It should easily reach a -3dB bandwidth of a few tens of MHz, though of course, beyond a few kHz, the input impedance is dominated by the input capacitance. Jeroen Belleman
Help with high input impedance amp.
Started by ●November 5, 2022
Reply by ●November 6, 20222022-11-06
Reply by ●November 6, 20222022-11-06
Jeroen Belleman wrote: ------------------------------------> > The two capacitors going back from the NPN emitter are bootstraps, > the top one reducing the effect of Cgd of the JFET, and the bottom > one increasing the effective impedance of the gate resistor. > > I'd expect the input impedance to be in the 100 MOhm ballpark in > parallel with a fraction of a pF. Any additional capacitive stuff > hanging on the input, tracks, pads, connectors, cables, whatnot, > adds to that, of course. > > It should easily reach a -3dB bandwidth of a few tens of MHz, > though of course, beyond a few kHz, the input impedance is > dominated by the input capacitance. >** Bootstrapping the gate resistor on a JFET might seem like a neat way to get a very high input resistance. A common application for such is a pre-amp for a condenser mic capsule - which is essentially a charged 50pF capacitor. Flat response down to below 20Hz means the input resistance needs to be about 500Mohms. Back in the day I tried the idea out in practice and found a major drawback - noise ! Positive feedback adds lots of it to the boostrapped resistor. Secondly, compared to using a 500M or 1Gohm resistor, the capacitance of the capsule cannot attenuate noise at the JFET gate near as well. Though thermal noise increases with resistor value, the -6dB / oct attenuation by a parallel capacitor attenuates it more. ..... Phil
Reply by ●November 7, 20222022-11-07
On 06/11/2022 14:22, Lamont Cranston wrote:> On Sunday, November 6, 2022 at 7:22:24 AM UTC-6, Fred Bloggs wrote: >> On Saturday, November 5, 2022 at 8:59:49 PM UTC-4, Lamont Cranston wrote: >>> Years ago on this group, someone worked this circuit out for me and I have finally built it. It has two problems. The input impedance is about 30kΩ not 500MΩ, and it rolls of way to early. >>> I may have created the problems, I don't have the FET and transistor recommended, 2N4416 and MMBTH10. I used a BF256C and a MPSH10 through hole parts. Although I doubt that created the low input impedance. >>> https://www.dropbox.com/s/kdwhcxmbk53ugqm/Dagmar%27s%20Fast%20high%20Imp%20amp%20with%20voltage%20labelsand%20RF%20voltages.jpg?dl=0 >>> Anyone care to tell me why such low input impedance and how to make the frequency flat to 30MHz? >>> Mikek >> You have something in the drain of T1 introducing excessive negative feedback on the gate drive. That's only way to explain the combination low input impedance and low frequency gain rolloff. If you can't do better with your layout, install a high frequency decoupling capacitor at T1 drain to ground there. > > I installed a small cap right at the drain to ground, no change. > I'm posting a picture of the PCB, to learn, not for harassment. :-) Tempted to shrink the the picture, but no. > Note: I have changed semi conductors about 6 times. > https://www.dropbox.com/s/w8psnbud9b6z2se/PCB.jpg?dl=0 > I have had the A, B, and C dc voltages vary over the various T1, Q2 changes, as I write I get A=2.4, B= 6.5 and C=5.8. > My first dc measurements were A=1.48 B=8.55 and C=7.83. I have also had A=1.0, B= 5.24, and C=4.63. (A is altered by the 10MΩ meter impedance.) > This doesn't have much effect on Gain.You can avoid getting silly numbers for the reading at A by comparing it with a reference voltage taken off a potentiometer in the classic bridge fashion. No current flows (= no voltage difference) when Vref = Vtest. Why do you actually want a very high impedance front end amplifier if your signal source is 50ohm? -- Regards, Martin Brown
Reply by ●November 7, 20222022-11-07
On Monday, November 7, 2022 at 4:30:30 AM UTC-6, Martin Brown wrote:> Why do you actually want a very high impedance front end amplifier if > your signal source is 50ohm? > > -- > Regards, > Martin BrownI just did* the math and it works out. 20MΩ in series with the 10MΩ meter is 30MΩ, the is in parallel with 2.2MΩ, so 2.081MΩ. So, we have a 10MΩ, 2.081MΩ voltage divider with a 24.91V supply, has 4.291V at the node. Now we have a 4.291V source feeding a series 20MΩ and 10MΩ meter. Again a voltage divider with 4.291V source feeding 20MΩ and 10MΩ, that leaves 1.43V at the node. If I recall correctly, I posted 1.5V and my notes say 1.48V. Close enough. The 50Ω source is just for testing. Mikek *did the math, I use online calculators, https://www.digikey.com/en/resources/conversion-calculators/conversion-calculator-parallel-and-series-resistor https://ohmslawcalculator.com/voltage-divider-calculator
Reply by ●November 7, 20222022-11-07
On Sunday, November 6, 2022 at 5:06:22 PM UTC-6, Jeroen Belleman wrote:> On 2022-11-06 22:48, Lamont Cranston wrote: > > On Sunday, November 6, 2022 at 2:59:07 PM UTC-6, Leo Baumann wrote: > >> Am 06.11.2022 um 21:54 schrieb Lamont Cranston: > >>> Because there is no data on the BF256C, and this fellow says there is a 17 x attenuation, > >>> that would make it 5.1pf of gate capacitance. > >> The gate-capacitance of a sFET BF256C is about 0.8 pF. > > > > Do you have a reference for that? > > > > I get 15.4 attenuation ratio, input to the source of the fet @1MHz. > > https://www.dropbox.com/s/5oud5mbdu45o73i/Kleijer%27s%20input%20circuit.jpg?dl=0 > > The fet source goes to a 100nF cap and about 500Ω to ground. > > Mikek > > > I see no reason why this wouldn't work, if constructed correctly. > It's a source follower followed by an emitter follower, so we > expect a gain a little below unity. The gate is biased to 9V > or so, but you shouldn't try to measure that directly because > the DC impedance is too high. > > The source should be a little above that, 11v maybe, and the NPN > emitter about 0.7V below that. You *can* measure that: The impedance > there is low enough. The drain resistor drops about 11V, same as the > source resistor, so that Vds ends up about 8V, a tad high, but > acceptable. There's 200mW dissipated in the NPN, so it will get hot, > probably too hot. Increasing the emitter resistor would help. > Adding a resistor in the collector lead would help too. Bypass the > collector to GND if you do that. > > With a 30V overall supply voltage, I'd probably make it rise gently, > to prevent transients stressing the semiconductors. > > The two capacitors going back from the NPN emitter are bootstraps, > the top one reducing the effect of Cgd of the JFET, and the bottom > one increasing the effective impedance of the gate resistor. > > I'd expect the input impedance to be in the 100 MOhm ballpark in > parallel with a fraction of a pF. Any additional capacitive stuff > hanging on the input, tracks, pads, connectors, cables, whatnot, > adds to that, of course. > > It should easily reach a -3dB bandwidth of a few tens of MHz, > though of course, beyond a few kHz, the input impedance is > dominated by the input capacitance. > > Jeroen BellemanI'm assuming the schematic is drawn correctly and the transistor is an NPN. Can I use aluminum polarized 1uf capacitors? If not, what would I use. Should both caps have the positive terminal connected to the emitter of the transistor? Seems kinda close, but what happens when it starts swinging? Maybe I should I have non-polarised 1uF caps. What kind? The schematic, https://www.dropbox.com/s/6n78s84gd9kaouu/High%20impedance%20input%20-%20Copy.jpg?dl=0 Thanks, Mikek
Reply by ●November 7, 20222022-11-07
On 2022-11-07 18:43, Lamont Cranston wrote:> On Sunday, November 6, 2022 at 5:06:22 PM UTC-6, Jeroen Belleman wrote: >> On 2022-11-06 22:48, Lamont Cranston wrote: >>> On Sunday, November 6, 2022 at 2:59:07 PM UTC-6, Leo Baumann wrote: >>>> Am 06.11.2022 um 21:54 schrieb Lamont Cranston: >>>>> Because there is no data on the BF256C, and this fellow says there is a 17 x attenuation, >>>>> that would make it 5.1pf of gate capacitance. >>>> The gate-capacitance of a sFET BF256C is about 0.8 pF. >>> >>> Do you have a reference for that? >>> >>> I get 15.4 attenuation ratio, input to the source of the fet @1MHz. >>> https://www.dropbox.com/s/5oud5mbdu45o73i/Kleijer%27s%20input%20circuit.jpg?dl=0 >>> The fet source goes to a 100nF cap and about 500Ω to ground. >>> Mikek >>> >> I see no reason why this wouldn't work, if constructed correctly. >> It's a source follower followed by an emitter follower, so we >> expect a gain a little below unity. The gate is biased to 9V >> or so, but you shouldn't try to measure that directly because >> the DC impedance is too high. >> >> The source should be a little above that, 11v maybe, and the NPN >> emitter about 0.7V below that. You *can* measure that: The impedance >> there is low enough. The drain resistor drops about 11V, same as the >> source resistor, so that Vds ends up about 8V, a tad high, but >> acceptable. There's 200mW dissipated in the NPN, so it will get hot, >> probably too hot. Increasing the emitter resistor would help. >> Adding a resistor in the collector lead would help too. Bypass the >> collector to GND if you do that. >> >> With a 30V overall supply voltage, I'd probably make it rise gently, >> to prevent transients stressing the semiconductors. >> >> The two capacitors going back from the NPN emitter are bootstraps, >> the top one reducing the effect of Cgd of the JFET, and the bottom >> one increasing the effective impedance of the gate resistor. >> >> I'd expect the input impedance to be in the 100 MOhm ballpark in >> parallel with a fraction of a pF. Any additional capacitive stuff >> hanging on the input, tracks, pads, connectors, cables, whatnot, >> adds to that, of course. >> >> It should easily reach a -3dB bandwidth of a few tens of MHz, >> though of course, beyond a few kHz, the input impedance is >> dominated by the input capacitance. >> >> Jeroen Belleman > > I'm assuming the schematic is drawn correctly and the transistor is an NPN. > Can I use aluminum polarized 1uf capacitors? If not, what would I use. > Should both caps have the positive terminal connected to the emitter of the transistor? > Seems kinda close, but what happens when it starts swinging? Maybe I should I have non-polarised 1uF caps. > What kind? > The schematic, > https://www.dropbox.com/s/6n78s84gd9kaouu/High%20impedance%20input%20-%20Copy.jpg?dl=0 > > Thanks, Mikek >There are no 1uF capacitors in that schematic. They are 0.1uF, but the decimal dot is all but vanishing. It wouldn't make much difference though. Either should work. If you really want to use polarized capacitors, the NPN emitter has the lowest DC potential of the three junctions, so the negative terminals of the caps should be connected there. For AC, the three nodes swing the same way, near enough, thanks to those two capacitors. That's what bootstraps are *intended* to do. That said, it's about time you Americans drop the silly .1u. Dots *do* vanish. Use 100n. This schematic breaks the point, if you'll excuse me the pun. The schematic is otherwise correct, it's an NPN alright. Jeroen Belleman
Reply by ●November 7, 20222022-11-07
On 07/11/2022 5:43 pm, Lamont Cranston wrote:> On Sunday, November 6, 2022 at 5:06:22 PM UTC-6, Jeroen Belleman wrote: >> On 2022-11-06 22:48, Lamont Cranston wrote: >>> On Sunday, November 6, 2022 at 2:59:07 PM UTC-6, Leo Baumann wrote: >>>> Am 06.11.2022 um 21:54 schrieb Lamont Cranston: >>>>> Because there is no data on the BF256C, and this fellow says there is a 17 x attenuation, >>>>> that would make it 5.1pf of gate capacitance. >>>> The gate-capacitance of a sFET BF256C is about 0.8 pF. >>> >>> Do you have a reference for that? >>> >>> I get 15.4 attenuation ratio, input to the source of the fet @1MHz. >>> https://www.dropbox.com/s/5oud5mbdu45o73i/Kleijer%27s%20input%20circuit.jpg?dl=0 >>> The fet source goes to a 100nF cap and about 500Ω to ground. >>> Mikek >>> >> I see no reason why this wouldn't work, if constructed correctly. >> It's a source follower followed by an emitter follower, so we >> expect a gain a little below unity. The gate is biased to 9V >> or so, but you shouldn't try to measure that directly because >> the DC impedance is too high. >> >> The source should be a little above that, 11v maybe, and the NPN >> emitter about 0.7V below that. You *can* measure that: The impedance >> there is low enough. The drain resistor drops about 11V, same as the >> source resistor, so that Vds ends up about 8V, a tad high, but >> acceptable. There's 200mW dissipated in the NPN, so it will get hot, >> probably too hot. Increasing the emitter resistor would help. >> Adding a resistor in the collector lead would help too. Bypass the >> collector to GND if you do that. >> >> With a 30V overall supply voltage, I'd probably make it rise gently, >> to prevent transients stressing the semiconductors. >> >> The two capacitors going back from the NPN emitter are bootstraps, >> the top one reducing the effect of Cgd of the JFET, and the bottom >> one increasing the effective impedance of the gate resistor. >> >> I'd expect the input impedance to be in the 100 MOhm ballpark in >> parallel with a fraction of a pF. Any additional capacitive stuff >> hanging on the input, tracks, pads, connectors, cables, whatnot, >> adds to that, of course. >> >> It should easily reach a -3dB bandwidth of a few tens of MHz, >> though of course, beyond a few kHz, the input impedance is >> dominated by the input capacitance. >> >> Jeroen Belleman > > I'm assuming the schematic is drawn correctly and the transistor is an NPN. > Can I use aluminum polarized 1uf capacitors? If not, what would I use. > Should both caps have the positive terminal connected to the emitter of the transistor? > Seems kinda close, but what happens when it starts swinging? Maybe I should I have non-polarised 1uF caps. > What kind? > The schematic, > https://www.dropbox.com/s/6n78s84gd9kaouu/High%20impedance%20input%20-%20Copy.jpg?dl=0 > > Thanks, MikekThe BJT is a jelly bean NPN, I suspect typo for the once popular 2N3643 (I found some in my junk box even!). Use 2N3904 or 2N2222 or BC548 whatever. The BF256 you used in the first version should be a fine substitute for 2N4416 - they are both listed as process 50 parts. 1uF is crazy too big unless do infrasound. Electrolytic leakage would be terrible at the front end. For the gate bias bootstrap even 1nF is massive, you can probably omit that part since even 10meg from the unbootstrapped resistor is more than you are aiming at. For the drain bootstrap a capacitor of 0.01uF would be OK down to a few kHz. I think your range is 0.5-30MHz? Everything between your Zin input test resistance and the gate should have minimal stray capacity - i.e. built up in the air a few mm above the board. piglet
Reply by ●November 7, 20222022-11-07
On Monday, November 7, 2022 at 1:11:45 PM UTC-6, Jeroen Belleman wrote:> > Thanks, Mikek > > > There are no 1uF capacitors in that schematic. They are 0.1uF, but the decimal > dot is all but vanishing. It wouldn't make much difference though. Either should > work. If you really want to use polarized capacitors, the NPN emitter has the > lowest DC potential of the three junctions, so the negative terminals of the > caps should be connected there. For AC, the three nodes swing the same way, > near enough, thanks to those two capacitors. That's what bootstraps are > *intended* to do. > > That said, it's about time you Americans drop the silly .1u. Dots *do* vanish. > Use 100n. This schematic breaks the point, if you'll excuse me the pun. > > The schematic is otherwise correct, it's an NPN alright. > > Jeroen BellemanWe have success! I laid out a pcb in Paint last night and etched it this morning. https://www.dropbox.com/s/fu53nx078daub2u/Linear%20high%20input%20impedance%20complete%20pcb.jpg?dl=0 No ground plane under the parts on either side. I used the 1uF, may have to change them, but it works, flat down to 1kHz, maybe lower I didn't test. AND, it is flat to 17MHz, then the output has a slight increase in level at 32Mhz (10%, 1.415Vpp to 1.565Vpp) although it has a peak at 29Mhz that is 15%. The output cap is a 0.1uF WITH A 1kΩ load. I need to add a couple of bypass caps I forgot about. It goes all the way to 90MHz before it starts to drop again. Any thought about knocking down the gain a little from 17MHz to 30MHz? I left the semi conductor leads long, any reason the shorten them. Thanks for the help, Mikek
Reply by ●November 7, 20222022-11-07
On Monday, November 7, 2022 at 1:37:09 PM UTC-6, erichp...@hotmail.com wrote:> > Thanks, Mikek > The BJT is a jelly bean NPN, I suspect typo for the once popular 2N3643 > (I found some in my junk box even!). Use 2N3904 or 2N2222 or BC548 > whatever. The BF256 you used in the first version should be a fine > substitute for 2N4416 - they are both listed as process 50 parts. > > 1uF is crazy too big unless do infrasound. Electrolytic leakage would be > terrible at the front end. For the gate bias bootstrap even 1nF is > massive, you can probably omit that part since even 10meg from the > unbootstrapped resistor is more than you are aiming at. For the drain > bootstrap a capacitor of 0.01uF would be OK down to a few kHz. I think > your range is 0.5-30MHz? > > Everything between your Zin input test resistance and the gate should > have minimal stray capacity - i.e. built up in the air a few mm above > the board. > > pigletIf you haven't read my previous post, IT WORKS! I used the BF256C and MPHS10. I understand the 1uF is wrong, and it should be 0.1uF. I'll be changing both. I had some internal debate, on how to place the 2.2MΩ, 1MΩ voltage divider that drives the 10MΩ gate resistor. So, I ended up running the input under the 2.2MΩ resistor, I have removed the ground plane from both sides of the pcb in that area. Thank, Mikek
Reply by ●November 7, 20222022-11-07
On 2022-11-07 21:53, Lamont Cranston wrote:> On Monday, November 7, 2022 at 1:11:45 PM UTC-6, Jeroen Belleman wrote: > >>> Thanks, Mikek >>> >> There are no 1uF capacitors in that schematic. They are 0.1uF, but the decimal >> dot is all but vanishing. It wouldn't make much difference though. Either should >> work. If you really want to use polarized capacitors, the NPN emitter has the >> lowest DC potential of the three junctions, so the negative terminals of the >> caps should be connected there. For AC, the three nodes swing the same way, >> near enough, thanks to those two capacitors. That's what bootstraps are >> *intended* to do. >> >> That said, it's about time you Americans drop the silly .1u. Dots *do* vanish. >> Use 100n. This schematic breaks the point, if you'll excuse me the pun. >> >> The schematic is otherwise correct, it's an NPN alright. >> >> Jeroen Belleman > > We have success! > I laid out a pcb in Paint last night and etched it this morning. > https://www.dropbox.com/s/fu53nx078daub2u/Linear%20high%20input%20impedance%20complete%20pcb.jpg?dl=0 > No ground plane under the parts on either side. > I used the 1uF, may have to change them, but it works, flat down to 1kHz, maybe lower I didn't test. > AND, it is flat to 17MHz, then the output has a slight increase in level at 32Mhz (10%, 1.415Vpp to 1.565Vpp) > although it has a peak at 29Mhz that is 15%. > The output cap is a 0.1uF WITH A 1kΩ load. > I need to add a couple of bypass caps I forgot about. > It goes all the way to 90MHz before it starts to drop again. > Any thought about knocking down the gain a little from 17MHz to 30MHz? > I left the semi conductor leads long, any reason the shorten them. > Thanks for the help, Mikek >Good! Congratulations. First finish adding the bypass caps. Followers with even slightly capacitive loads can have a region with negative input resistance. Maybe you're getting close to such conditions.Try a ferrite bead in the gate lead, maybe. You may also try out what happens if you remove either or both of the bootstraps. Shortening the leads of parts, making the circuit more compact, might help too. Jeroen Belleman
