On Tue, 25 Oct 2022 21:56:32 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>Joe Gwinn wrote: >> On Tue, 25 Oct 2022 18:01:17 -0400, Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >>> Joe Gwinn wrote: >>>> On Tue, 25 Oct 2022 07:56:38 -0700, John Larkin >>>> <jlarkin@highlandSNIPMEtechnology.com> wrote: >>>> >>>>> On Tue, 25 Oct 2022 10:43:18 -0400, bitrex <user@example.net> wrote: >>>>> >>>>>> On 10/24/2022 4:16 PM, John Larkin wrote: >>>>>>> We have some sims that run absurdly slow. What are your favorite >>>>>>> speedups? >>>>>>> >>>>>>> In LT spice, I have arbitrarily done >>>>>>> >>>>>>> .opt reltol=.002 >>>>>>> >>>>>>> .opt abstol=5n >>>>>>> >>>>>>> .opt trtol=5 >>>>>>> >>>>>>> but that's just guessing. It may work with my parts but mess up an >>>>>>> encrypted model that I have no visibility into. >>>>>>> >>>>>>> Sometimes one solver is unaccountably better than another. >>>>>>> >>>>>> >>>>>> Using a RAM drive for waveform storage is one, but I guess I don't >>>>>> regularly run sims complex enough that it causes a Ryzen 5600 to chug >>>>>> badly enough to make me frustrated. Have you upgraded your CPU lately? >>>>> >>>>> The guy running this for me has a pretty good, fairly new PC. But the >>>>> sim takes hours to simulate 10s of milliseconds, so we don't want a >>>>> modest speedup. >>>>> >>>>> TI software, TI models, runs for hours. That's silly. >>>> >>>> My recollection from my power-system colleagues is that this can be >>>> caused by often parasitic sub circuits with very short time constants >>>> (compared to the core circuit), so the approach was to model only the >>>> core circuit at first, then start to decorate it. >>>> >>>> Joe Gwinn >>>> >>> The Gear integrator is specifically designed for problems like that. >>> ("stiff systems"). >> >> Yes, but sometimes one must also simplify. >> >> I've also been bitten by MATLAB handling an overdetermined system by >> endless iteration. Had to reformulate the problem to evade that. >> >> Joe Gwinn >> > >A stiff system is one whose largest and smallest eigenvalues are very >different, in some not-too-well-defined mathematical notion of "very >different". ;)Yes. In a realistic power-supply circuit models, the parasitic subcircuits will have eigen frequencies far higher than the core circuits, so the overall system is stiff.>An overdetermined system is another animal--usually a benevolent one >IME. With a bit of work, it's often possible to get a least-squares >optimum solution plus an internal error estimate.Yes, solving inherently overdetermined systems can be quite useful. The problem we had was that the sim was running a factor of about a hundred slower than needed to permit the required sim runs to be made in time, and the over determination was an accident of how the simulation was structured. It was expressed in a block-and-wire model (Simulink, no programming needed!), and looked clean and simple on paper. Oops.>Fifth- and higher-order Runge-Kutta methods for ODEs are an example I >recall, and of course closure phase in interferometry.Oh, yes. What I also recall using was implicit numerical integration, like Backward Euler: .<https://en.wikipedia.org/wiki/Explicit_and_implicit_methods> The advantage being that the simple implicit methods were not all that fussy. Joe Gwinn
favorite Spice speedups
Started by ●October 24, 2022
Reply by ●October 26, 20222022-10-26
Reply by ●October 26, 20222022-10-26
On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown <'''newspam'''@nonad.co.uk> wrote:>On 26/10/2022 04:41, John Larkin wrote: >> On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown >> <'''newspam'''@nonad.co.uk> wrote: >> > >>> Chances are one or more of the equations is stiff and the time step is >>> becoming infinitessimal on one of the rapid transitions. Adding a bit of >>> spurious dissipation 1M to ground here and there might take the edge off >>> whatever is making it so stiff. >> >> We are running TI's Cadence sim and TI's encrypted switcher chip >> models. >> >> We just discovered that their TPS562208 model runs about 50x faster >> than the TPS54302 model. They are very similar chips. We have both in >> our power supply design, one 54302 pre-regulating for three of the >> 562208's. > >It might be worth building one to see if it really is inclined to squeg >in real circuits. The sim could be telling you something important.If we can't reasonably sim it, we'll build it. I can imagine the three secondary switchers, negative impedance loads, making the first one oscillate. That's not a risk we want on our new delay generator. Each reg needs output caps of unknown value, and feedforward caps in its fedback divider. May as well get all that right.> > >>> We once did some awkward PDE's in a computer solution and on a Tektronix >>> vector display monitor they looked fine so sent them off to the plotter. >>> The job came back part done with an apologetic note from the sysop "your >>> job was cancelled because the red pen began to work loose". >>> >>> Careful examination of the plot file showed some of the vector steps >>> were just Angstroms long! >> >> Sometimes a Spice sim takes femtosecond steps all afternoon. For some >> reason the Spice programs allow us to set the max time step but not >> the min. > >Usually if a simulation goes to insanely short steps it is because it >cannot achieve the specified accuracy any other way (or is buggy). That >sort of behaviour is characteristic of stiff equations where it is >fighting hard to prevent the solution diverging in some bad way. > >Parasitic things with ridiculously high Q can ring if provoked which is >why adding the odd spurious dissipative resistor to certain key nodes >sometimes helps instil good behaviour. Jeroen has made the same point.I wish TI knew all that.
Reply by ●October 26, 20222022-10-26
John Larkin wrote:> On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown > <'''newspam'''@nonad.co.uk> wrote: > >> On 26/10/2022 04:41, John Larkin wrote: >>> On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown >>> <'''newspam'''@nonad.co.uk> wrote: >>> >> >>>> Chances are one or more of the equations is stiff and the time step is >>>> becoming infinitessimal on one of the rapid transitions. Adding a bit of >>>> spurious dissipation 1M to ground here and there might take the edge off >>>> whatever is making it so stiff. >>> >>> We are running TI's Cadence sim and TI's encrypted switcher chip >>> models. >>> >>> We just discovered that their TPS562208 model runs about 50x faster >>> than the TPS54302 model. They are very similar chips. We have both in >>> our power supply design, one 54302 pre-regulating for three of the >>> 562208's. >> >> It might be worth building one to see if it really is inclined to squeg >> in real circuits. The sim could be telling you something important. > > If we can't reasonably sim it, we'll build it. I can imagine the three > secondary switchers, negative impedance loads, making the first one > oscillate. That's not a risk we want on our new delay generator. > > Each reg needs output caps of unknown value, and feedforward caps in > its fedback divider. May as well get all that right. > > > >> >> >>>> We once did some awkward PDE's in a computer solution and on a Tektronix >>>> vector display monitor they looked fine so sent them off to the plotter. >>>> The job came back part done with an apologetic note from the sysop "your >>>> job was cancelled because the red pen began to work loose". >>>> >>>> Careful examination of the plot file showed some of the vector steps >>>> were just Angstroms long! >>> >>> Sometimes a Spice sim takes femtosecond steps all afternoon. For some >>> reason the Spice programs allow us to set the max time step but not >>> the min. >> >> Usually if a simulation goes to insanely short steps it is because it >> cannot achieve the specified accuracy any other way (or is buggy). That >> sort of behaviour is characteristic of stiff equations where it is >> fighting hard to prevent the solution diverging in some bad way. >> >> Parasitic things with ridiculously high Q can ring if provoked which is >> why adding the odd spurious dissipative resistor to certain key nodes >> sometimes helps instil good behaviour. Jeroen has made the same point. > > I wish TI knew all that. >I suspect they give their modelers tight budgets for how many hours they can spend per model. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Reply by ●October 26, 20222022-10-26
On Wed, 26 Oct 2022 15:29:06 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>John Larkin wrote: >> On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown >> <'''newspam'''@nonad.co.uk> wrote: >> >>> On 26/10/2022 04:41, John Larkin wrote: >>>> On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown >>>> <'''newspam'''@nonad.co.uk> wrote: >>>> >>> >>>>> Chances are one or more of the equations is stiff and the time step is >>>>> becoming infinitessimal on one of the rapid transitions. Adding a bit of >>>>> spurious dissipation 1M to ground here and there might take the edge off >>>>> whatever is making it so stiff. >>>> >>>> We are running TI's Cadence sim and TI's encrypted switcher chip >>>> models. >>>> >>>> We just discovered that their TPS562208 model runs about 50x faster >>>> than the TPS54302 model. They are very similar chips. We have both in >>>> our power supply design, one 54302 pre-regulating for three of the >>>> 562208's. >>> >>> It might be worth building one to see if it really is inclined to squeg >>> in real circuits. The sim could be telling you something important. >> >> If we can't reasonably sim it, we'll build it. I can imagine the three >> secondary switchers, negative impedance loads, making the first one >> oscillate. That's not a risk we want on our new delay generator. >> >> Each reg needs output caps of unknown value, and feedforward caps in >> its fedback divider. May as well get all that right. >> >> >> >>> >>> >>>>> We once did some awkward PDE's in a computer solution and on a Tektronix >>>>> vector display monitor they looked fine so sent them off to the plotter. >>>>> The job came back part done with an apologetic note from the sysop "your >>>>> job was cancelled because the red pen began to work loose". >>>>> >>>>> Careful examination of the plot file showed some of the vector steps >>>>> were just Angstroms long! >>>> >>>> Sometimes a Spice sim takes femtosecond steps all afternoon. For some >>>> reason the Spice programs allow us to set the max time step but not >>>> the min. >>> >>> Usually if a simulation goes to insanely short steps it is because it >>> cannot achieve the specified accuracy any other way (or is buggy). That >>> sort of behaviour is characteristic of stiff equations where it is >>> fighting hard to prevent the solution diverging in some bad way. >>> >>> Parasitic things with ridiculously high Q can ring if provoked which is >>> why adding the odd spurious dissipative resistor to certain key nodes >>> sometimes helps instil good behaviour. Jeroen has made the same point. >> >> I wish TI knew all that. >> > >I suspect they give their modelers tight budgets for how many hours they >can spend per model. > >Cheers > >Phil HobbsOne of my guys managed to get the TI switchers to run in LT Spice. Then managed to speed it up. As in, add a milliohm of ESR to the bootstrap cap. Things like that.
Reply by ●October 26, 20222022-10-26
John Larkin wrote:> On Wed, 26 Oct 2022 15:29:06 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> John Larkin wrote: >>> On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown >>> <'''newspam'''@nonad.co.uk> wrote: >>> >>>> On 26/10/2022 04:41, John Larkin wrote: >>>>> On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown >>>>> <'''newspam'''@nonad.co.uk> wrote: >>>>> >>>> >>>>>> Chances are one or more of the equations is stiff and the time step is >>>>>> becoming infinitessimal on one of the rapid transitions. Adding a bit of >>>>>> spurious dissipation 1M to ground here and there might take the edge off >>>>>> whatever is making it so stiff. >>>>> >>>>> We are running TI's Cadence sim and TI's encrypted switcher chip >>>>> models. >>>>> >>>>> We just discovered that their TPS562208 model runs about 50x faster >>>>> than the TPS54302 model. They are very similar chips. We have both in >>>>> our power supply design, one 54302 pre-regulating for three of the >>>>> 562208's. >>>> >>>> It might be worth building one to see if it really is inclined to squeg >>>> in real circuits. The sim could be telling you something important. >>> >>> If we can't reasonably sim it, we'll build it. I can imagine the three >>> secondary switchers, negative impedance loads, making the first one >>> oscillate. That's not a risk we want on our new delay generator. >>> >>> Each reg needs output caps of unknown value, and feedforward caps in >>> its fedback divider. May as well get all that right. >>> >>> >>> >>>> >>>> >>>>>> We once did some awkward PDE's in a computer solution and on a Tektronix >>>>>> vector display monitor they looked fine so sent them off to the plotter. >>>>>> The job came back part done with an apologetic note from the sysop "your >>>>>> job was cancelled because the red pen began to work loose". >>>>>> >>>>>> Careful examination of the plot file showed some of the vector steps >>>>>> were just Angstroms long! >>>>> >>>>> Sometimes a Spice sim takes femtosecond steps all afternoon. For some >>>>> reason the Spice programs allow us to set the max time step but not >>>>> the min. >>>> >>>> Usually if a simulation goes to insanely short steps it is because it >>>> cannot achieve the specified accuracy any other way (or is buggy). That >>>> sort of behaviour is characteristic of stiff equations where it is >>>> fighting hard to prevent the solution diverging in some bad way. >>>> >>>> Parasitic things with ridiculously high Q can ring if provoked which is >>>> why adding the odd spurious dissipative resistor to certain key nodes >>>> sometimes helps instil good behaviour. Jeroen has made the same point. >>> >>> I wish TI knew all that. >>> >> >> I suspect they give their modelers tight budgets for how many hours they >> can spend per model. >> >> Cheers >> >> Phil Hobbs > > One of my guys managed to get the TI switchers to run in LT Spice. > > Then managed to speed it up. As in, add a milliohm of ESR to the > bootstrap cap. Things like that. >Sounds super useful. Get him to post it at the LTspice group. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Reply by ●October 26, 20222022-10-26
Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>> Then managed to speed it up. As in, add a milliohm of ESR to the >> bootstrap cap. Things like that. >> > > Sounds super useful. Get him to post it at the LTspice group. > > Cheers > > Phil HobbsIt's worth noting that LTspice adds 1 milliohm of series resistance to inductors. You can change it, of course. The trick is it doesn't add any series resistance to capacitors. This traps most people who are not aware of the difference, and some wild simulations result. -- MRM
Reply by ●October 26, 20222022-10-26
On Thursday, October 27, 2022 at 1:18:34 PM UTC+11, Mike Monett VE3BTI wrote:> Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote: > > >> Then managed to speed it up. As in, add a milliohm of ESR to the > >> bootstrap cap. Things like that. > >> > > > > Sounds super useful. Get him to post it at the LTspice group. > > It's worth noting that LTspice adds 1 milliohm of series resistance to > inductors. You can change it, of course. > > The trick is it doesn't add any series resistance to capacitors. This traps > most people who are not aware of the difference, and some wild simulations > result.Capacitors range from 1pF to hundred of uF. It's a large range and one size wouldn't fit all. -- Bill Sloman, Sydney
Reply by ●October 26, 20222022-10-26
Mike Monett VE3BTI <spamme@not.com> wrote:> The trick is it doesn't add any series resistance to capacitors. This > traps most people who are not aware of the difference, and some wild > simulations result.The moral of the story is always, always add series resistance to capacitors, and adjust the inductor series resistance to the appropriate value. This gets complicated if skin effect is involved, since it changes with frequency. But there are various models for skin effect that can be used. -- MRM
Reply by ●October 27, 20222022-10-27
On Wed, 26 Oct 2022 21:00:14 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>John Larkin wrote: >> On Wed, 26 Oct 2022 15:29:06 -0400, Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >>> John Larkin wrote: >>>> On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown >>>> <'''newspam'''@nonad.co.uk> wrote: >>>> >>>>> On 26/10/2022 04:41, John Larkin wrote: >>>>>> On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown >>>>>> <'''newspam'''@nonad.co.uk> wrote: >>>>>> >>>>> >>>>>>> Chances are one or more of the equations is stiff and the time step is >>>>>>> becoming infinitessimal on one of the rapid transitions. Adding a bit of >>>>>>> spurious dissipation 1M to ground here and there might take the edge off >>>>>>> whatever is making it so stiff. >>>>>> >>>>>> We are running TI's Cadence sim and TI's encrypted switcher chip >>>>>> models. >>>>>> >>>>>> We just discovered that their TPS562208 model runs about 50x faster >>>>>> than the TPS54302 model. They are very similar chips. We have both in >>>>>> our power supply design, one 54302 pre-regulating for three of the >>>>>> 562208's. >>>>> >>>>> It might be worth building one to see if it really is inclined to squeg >>>>> in real circuits. The sim could be telling you something important. >>>> >>>> If we can't reasonably sim it, we'll build it. I can imagine the three >>>> secondary switchers, negative impedance loads, making the first one >>>> oscillate. That's not a risk we want on our new delay generator. >>>> >>>> Each reg needs output caps of unknown value, and feedforward caps in >>>> its fedback divider. May as well get all that right. >>>> >>>> >>>> >>>>> >>>>> >>>>>>> We once did some awkward PDE's in a computer solution and on a Tektronix >>>>>>> vector display monitor they looked fine so sent them off to the plotter. >>>>>>> The job came back part done with an apologetic note from the sysop "your >>>>>>> job was cancelled because the red pen began to work loose". >>>>>>> >>>>>>> Careful examination of the plot file showed some of the vector steps >>>>>>> were just Angstroms long! >>>>>> >>>>>> Sometimes a Spice sim takes femtosecond steps all afternoon. For some >>>>>> reason the Spice programs allow us to set the max time step but not >>>>>> the min. >>>>> >>>>> Usually if a simulation goes to insanely short steps it is because it >>>>> cannot achieve the specified accuracy any other way (or is buggy). That >>>>> sort of behaviour is characteristic of stiff equations where it is >>>>> fighting hard to prevent the solution diverging in some bad way. >>>>> >>>>> Parasitic things with ridiculously high Q can ring if provoked which is >>>>> why adding the odd spurious dissipative resistor to certain key nodes >>>>> sometimes helps instil good behaviour. Jeroen has made the same point. >>>> >>>> I wish TI knew all that. >>>> >>> >>> I suspect they give their modelers tight budgets for how many hours they >>> can spend per model. >>> >>> Cheers >>> >>> Phil Hobbs >> >> One of my guys managed to get the TI switchers to run in LT Spice. >> >> Then managed to speed it up. As in, add a milliohm of ESR to the >> bootstrap cap. Things like that. >> > >Sounds super useful. Get him to post it at the LTspice group. > >Cheers > >Phil HobbsI'll clean it up some and post here at least. The TPS54302 sim runs at bearable speed, but efficiency is mediocre. It's pulling 6T amps on the +12 input.
Reply by ●October 27, 20222022-10-27
On 26/10/2022 20:29, Phil Hobbs wrote:> John Larkin wrote: >> On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown >> <'''newspam'''@nonad.co.uk> wrote: >> >>> On 26/10/2022 04:41, John Larkin wrote: >>>> On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown >>>> <'''newspam'''@nonad.co.uk> wrote: >>>> >>> >>>>> Chances are one or more of the equations is stiff and the time step is >>>>> becoming infinitessimal on one of the rapid transitions. Adding a >>>>> bit of >>>>> spurious dissipation 1M to ground here and there might take the >>>>> edge off >>>>> whatever is making it so stiff. >>>> >>>> We are running TI's Cadence sim and TI's encrypted switcher chip >>>> models. >>>> >>>> We just discovered that their TPS562208 model runs about 50x faster >>>> than the TPS54302 model. They are very similar chips. We have both in >>>> our power supply design, one 54302 pre-regulating for three of the >>>> 562208's. >>> >>> It might be worth building one to see if it really is inclined to squeg >>> in real circuits. The sim could be telling you something important. >> >> If we can't reasonably sim it, we'll build it. I can imagine the three >> secondary switchers, negative impedance loads, making the first one >> oscillate. That's not a risk we want on our new delay generator. >> >> Each reg needs output caps of unknown value, and feedforward caps in >> its fedback divider. May as well get all that right.What might break the deadlock for computation is add a small series resistance to the capacitance after the first regulator to low pass filter it. The trick will be to find something modest enough to not affect the predictions much but sufficient to compute it more easily. You might have to do something like that IRL too. I expect they never expected you to daisy chain them back to back like that and the output of the first one really doesn't like facing the negative impedance dynamic load. Classic way to make an oscillator.>>> Parasitic things with ridiculously high Q can ring if provoked which is >>> why adding the odd spurious dissipative resistor to certain key nodes >>> sometimes helps instil good behaviour. Jeroen has made the same point. >> >> I wish TI knew all that. >> > > I suspect they give their modelers tight budgets for how many hours they > can spend per model.And that they never considered the output of one driving the inputs of several others. -- Regards, Martin Brown
