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strange LT Spice s/h behavior

Started by John Larkin ●August 12, 2022
Reply by legg ●August 15, 20222022-08-15
On Fri, 12 Aug 2022 21:19:06 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:


>On Fri, 12 Aug 2022 12:47:59 -0700, John Larkin
><jjlarkin@highlandtechnology.com> wrote:
>
>>I figured that I could bootstrap an LT Spice sample/hold to make a
>>stairstep waveform.
>>
>>Without the RC, the output jumps to +10 volts at the first clock edge.
>>And the RC has to be right to get a proper stairstep.
>>

<snip>

>>TEXT -216 8 Left 2 ;S/H Stairstep
>>TEXT -224 56 Left 2 ;JL Aug 12 2022
>
>Even the RC is dicey. The best thing is to add a delay line at the s/h
>input.


LTspice group on io says the sample is instantaneous without internal 
delays - that direct gain is possible. Uncommented defaulkt output Z
is iK. A Td statement will have no effect.

Says not to worry - you can't buy one of these anyways.

RL
Reply by ●August 15, 20222022-08-15
On Mon, 15 Aug 2022 11:17:03 -0400, legg <legg@nospam.magma.ca> wrote:


>On Fri, 12 Aug 2022 21:19:06 -0700, John Larkin
><jjlarkin@highlandtechnology.com> wrote:
>
>>On Fri, 12 Aug 2022 12:47:59 -0700, John Larkin
>><jjlarkin@highlandtechnology.com> wrote:
>>
>>>I figured that I could bootstrap an LT Spice sample/hold to make a
>>>stairstep waveform.
>>>
>>>Without the RC, the output jumps to +10 volts at the first clock edge.
>>>And the RC has to be right to get a proper stairstep.
>>>
><snip>
>>>TEXT -216 8 Left 2 ;S/H Stairstep
>>>TEXT -224 56 Left 2 ;JL Aug 12 2022
>>
>>Even the RC is dicey. The best thing is to add a delay line at the s/h
>>input.
>
>LTspice group on io says the sample is instantaneous without internal 
>delays - that direct gain is possible. Uncommented defaulkt output Z
>is iK. A Td statement will have no effect.


It's still very weird. 


>
>Says not to worry - you can't buy one of these anyways.
>
>RL


A few people used to make analog s/h chips, but I think they are gone.
Reply by John Larkin ●August 15, 20222022-08-15
On Mon, 15 Aug 2022 09:14:48 -0700, jlarkin@highlandsniptechnology.com
wrote:


>On Mon, 15 Aug 2022 11:17:03 -0400, legg <legg@nospam.magma.ca> wrote:
>
>>On Fri, 12 Aug 2022 21:19:06 -0700, John Larkin
>><jjlarkin@highlandtechnology.com> wrote:
>>
>>>On Fri, 12 Aug 2022 12:47:59 -0700, John Larkin
>>><jjlarkin@highlandtechnology.com> wrote:
>>>
>>>>I figured that I could bootstrap an LT Spice sample/hold to make a
>>>>stairstep waveform.
>>>>
>>>>Without the RC, the output jumps to +10 volts at the first clock edge.
>>>>And the RC has to be right to get a proper stairstep.
>>>>
>><snip>
>>>>TEXT -216 8 Left 2 ;S/H Stairstep
>>>>TEXT -224 56 Left 2 ;JL Aug 12 2022
>>>
>>>Even the RC is dicey. The best thing is to add a delay line at the s/h
>>>input.
>>
>>LTspice group on io says the sample is instantaneous without internal 
>>delays - that direct gain is possible. Uncommented defaulkt output Z
>>is iK. A Td statement will have no effect.
>
>It's still very weird. 
>
>>
>>Says not to worry - you can't buy one of these anyways.
>>
>>RL
>
>A few people used to make analog s/h chips, but I think they are gone.


Actually, there are some.

https://www.mouser.com/c/semiconductors/amplifier-ics/sample-hold-amplifiers/?gclid=EAIaIQobChMI4anyg-zJ-QIVWRatBh0xXQHuEAAYAiAAEgLP4vD_BwE
Reply by legg ●August 16, 20222022-08-16
On Mon, 15 Aug 2022 15:01:03 -0700, John Larkin
<jlarkin@highland_atwork_technology.com> wrote:


>On Mon, 15 Aug 2022 09:14:48 -0700, jlarkin@highlandsniptechnology.com
>wrote:
>
>>On Mon, 15 Aug 2022 11:17:03 -0400, legg <legg@nospam.magma.ca> wrote:
>>
>>>On Fri, 12 Aug 2022 21:19:06 -0700, John Larkin
>>><jjlarkin@highlandtechnology.com> wrote:
>>>
>>>>On Fri, 12 Aug 2022 12:47:59 -0700, John Larkin
>>>><jjlarkin@highlandtechnology.com> wrote:
>>>>
>>>>>I figured that I could bootstrap an LT Spice sample/hold to make a
>>>>>stairstep waveform.
>>>>>
>>>>>Without the RC, the output jumps to +10 volts at the first clock edge.
>>>>>And the RC has to be right to get a proper stairstep.
>>>>>
>>><snip>
>>>>>TEXT -216 8 Left 2 ;S/H Stairstep
>>>>>TEXT -224 56 Left 2 ;JL Aug 12 2022
>>>>
>>>>Even the RC is dicey. The best thing is to add a delay line at the s/h
>>>>input.
>>>
>>>LTspice group on io says the sample is instantaneous without internal 
>>>delays - that direct gain is possible. Uncommented defaulkt output Z
>>>is iK. A Td statement will have no effect.
>>
>>It's still very weird. 
>>
>>>
>>>Says not to worry - you can't buy one of these anyways.
>>>
>>>RL
>>
>>A few people used to make analog s/h chips, but I think they are gone.
>
>Actually, there are some.
>
>https://www.mouser.com/c/semiconductors/amplifier-ics/sample-hold-amplifiers/?gclid=EAIaIQobChMI4anyg-zJ-QIVWRatBh0xXQHuEAAYAiAAEgLP4vD_BwE


The 'sample' subcircuit is not a model of any of these 
parts, hence the purchasing non-information.

RL