I figured that I could bootstrap an LT Spice sample/hold to make a stairstep waveform. Without the RC, the output jumps to +10 volts at the first clock edge. And the RC has to be right to get a proper stairstep. Version 4 SHEET 1 880 680 WIRE 144 -128 32 -128 WIRE 240 -128 144 -128 WIRE 448 -128 320 -128 WIRE 144 -80 144 -128 WIRE 448 0 448 -128 WIRE 144 16 144 -16 WIRE 32 96 32 -128 WIRE 192 96 32 96 WIRE 192 128 32 128 WIRE 448 144 448 80 WIRE 448 144 368 144 WIRE 576 144 448 144 WIRE 32 160 32 128 WIRE 192 160 96 160 WIRE 96 208 96 160 WIRE 96 320 96 288 FLAG 96 320 0 FLAG 32 160 0 FLAG 144 16 0 SYMBOL SpecialFunctions\\sample 272 128 R0 WINDOW 0 -16 -113 Left 2 WINDOW 3 -56 -83 Left 2 SYMATTR InstName A1 SYMATTR Value ROUT=1m SYMBOL voltage 96 192 R0 WINDOW 0 48 76 Left 2 WINDOW 3 21 110 Left 2 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 1 10u 1n 1n 500n 1u 1e6) SYMBOL voltage 448 -16 R0 WINDOW 0 57 42 Left 2 WINDOW 3 49 76 Left 2 SYMATTR InstName V2 SYMATTR Value 500m SYMBOL res 336 -144 R90 WINDOW 0 77 55 VBottom 2 WINDOW 3 85 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL cap 128 -80 R0 WINDOW 0 -56 19 Left 2 WINDOW 3 -59 49 Left 2 SYMATTR InstName C1 SYMATTR Value 10p TEXT -200 112 Left 2 !.tran 100u TEXT -216 8 Left 2 ;S/H Stairstep TEXT -224 56 Left 2 ;JL Aug 12 2022 -- John Larkin Highland Technology, Inc trk The cork popped merrily, and Lord Peter rose to his feet. "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"
strange LT Spice s/h behavior
Started by ●August 12, 2022
Reply by ●August 12, 20222022-08-12
John Larkin wrote:> I figured that I could bootstrap an LT Spice sample/hold to make a > stairstep waveform. > > Without the RC, the output jumps to +10 volts at the first clock edge. > And the RC has to be right to get a proper stairstep. >Didn't try it out, but did you use the vanilla trap solver or the tricky one? Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Reply by ●August 12, 20222022-08-12
On Fri, 12 Aug 2022 16:05:46 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>John Larkin wrote: >> I figured that I could bootstrap an LT Spice sample/hold to make a >> stairstep waveform. >> >> Without the RC, the output jumps to +10 volts at the first clock edge. >> And the RC has to be right to get a proper stairstep. >> > >Didn't try it out, but did you use the vanilla trap solver or the tricky >one? > >Cheers > >Phil HobbsMod trap, alternate. I'll try something else.
Reply by ●August 12, 20222022-08-12
On Fri, 12 Aug 2022 13:16:07 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:>On Fri, 12 Aug 2022 16:05:46 -0400, Phil Hobbs ><pcdhSpamMeSenseless@electrooptical.net> wrote: > >>John Larkin wrote: >>> I figured that I could bootstrap an LT Spice sample/hold to make a >>> stairstep waveform. >>> >>> Without the RC, the output jumps to +10 volts at the first clock edge. >>> And the RC has to be right to get a proper stairstep. >>> >> >>Didn't try it out, but did you use the vanilla trap solver or the tricky >>one? >> >>Cheers >> >>Phil Hobbs > >Mod trap, alternate. I'll try something else.Control panel, spice, reset to default (mod trap, normal solver) it behaves the same.
Reply by ●August 12, 20222022-08-12
On Fri, 12 Aug 2022 12:47:59 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:>I figured that I could bootstrap an LT Spice sample/hold to make a >stairstep waveform. > >Without the RC, the output jumps to +10 volts at the first clock edge. >And the RC has to be right to get a proper stairstep. >So it works with the RC - suggests a linear condition is permitted at the sampling time. Perhaps the internal gates aren't timed to prevent signal shoot-through. RL
Reply by ●August 12, 20222022-08-12
On Fri, 12 Aug 2022 20:28:14 -0400, legg <legg@nospam.magma.ca> wrote:>On Fri, 12 Aug 2022 12:47:59 -0700, John Larkin ><jjlarkin@highlandtechnology.com> wrote: > >>I figured that I could bootstrap an LT Spice sample/hold to make a >>stairstep waveform. >> >>Without the RC, the output jumps to +10 volts at the first clock edge. >>And the RC has to be right to get a proper stairstep. >> > >So it works with the RC - suggests a linear condition is >permitted at the sampling time. Perhaps the internal >gates aren't timed to prevent signal shoot-through. > >RLI can't understand it. Even 1K and 1 fF allows it to make a staircase. But 1K and 0 fF doesn't. Obviously something is goofy inside the s/h model, but I wouldn't know how to accomplish that. I can do what I want to do, by adding an RC, but I don't understand it.
Reply by ●August 13, 20222022-08-13
On Fri, 12 Aug 2022 12:47:59 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:>I figured that I could bootstrap an LT Spice sample/hold to make a >stairstep waveform. > >Without the RC, the output jumps to +10 volts at the first clock edge. >And the RC has to be right to get a proper stairstep. > > > >Version 4 >SHEET 1 880 680 >WIRE 144 -128 32 -128 >WIRE 240 -128 144 -128 >WIRE 448 -128 320 -128 >WIRE 144 -80 144 -128 >WIRE 448 0 448 -128 >WIRE 144 16 144 -16 >WIRE 32 96 32 -128 >WIRE 192 96 32 96 >WIRE 192 128 32 128 >WIRE 448 144 448 80 >WIRE 448 144 368 144 >WIRE 576 144 448 144 >WIRE 32 160 32 128 >WIRE 192 160 96 160 >WIRE 96 208 96 160 >WIRE 96 320 96 288 >FLAG 96 320 0 >FLAG 32 160 0 >FLAG 144 16 0 >SYMBOL SpecialFunctions\\sample 272 128 R0 >WINDOW 0 -16 -113 Left 2 >WINDOW 3 -56 -83 Left 2 >SYMATTR InstName A1 >SYMATTR Value ROUT=1m >SYMBOL voltage 96 192 R0 >WINDOW 0 48 76 Left 2 >WINDOW 3 21 110 Left 2 >WINDOW 123 0 0 Left 0 >WINDOW 39 0 0 Left 0 >SYMATTR InstName V1 >SYMATTR Value PULSE(0 1 10u 1n 1n 500n 1u 1e6) >SYMBOL voltage 448 -16 R0 >WINDOW 0 57 42 Left 2 >WINDOW 3 49 76 Left 2 >SYMATTR InstName V2 >SYMATTR Value 500m >SYMBOL res 336 -144 R90 >WINDOW 0 77 55 VBottom 2 >WINDOW 3 85 56 VTop 2 >SYMATTR InstName R1 >SYMATTR Value 1k >SYMBOL cap 128 -80 R0 >WINDOW 0 -56 19 Left 2 >WINDOW 3 -59 49 Left 2 >SYMATTR InstName C1 >SYMATTR Value 10p >TEXT -200 112 Left 2 !.tran 100u >TEXT -216 8 Left 2 ;S/H Stairstep >TEXT -224 56 Left 2 ;JL Aug 12 2022Even the RC is dicey. The best thing is to add a delay line at the s/h input.
Reply by ●August 13, 20222022-08-13
On Fri, 12 Aug 2022 18:41:32 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:>On Fri, 12 Aug 2022 20:28:14 -0400, legg <legg@nospam.magma.ca> wrote: > >>On Fri, 12 Aug 2022 12:47:59 -0700, John Larkin >><jjlarkin@highlandtechnology.com> wrote: >> >>>I figured that I could bootstrap an LT Spice sample/hold to make a >>>stairstep waveform. >>> >>>Without the RC, the output jumps to +10 volts at the first clock edge. >>>And the RC has to be right to get a proper stairstep. >>> >> >>So it works with the RC - suggests a linear condition is >>permitted at the sampling time. Perhaps the internal >>gates aren't timed to prevent signal shoot-through. >> >>RL > >I can't understand it. Even 1K and 1 fF allows it to make a staircase. >But 1K and 0 fF doesn't. > >Obviously something is goofy inside the s/h model, but I wouldn't know >how to accomplish that. > >I can do what I want to do, by adding an RC, but I don't understand >it.Stick 50R in series with the SH inputs and look at the voltages on each side of the resistor. This shouldn't normally 'break' a S/H, should it? RL
Reply by ●August 13, 20222022-08-13
On Fri, 12 Aug 2022 18:41:32 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:>On Fri, 12 Aug 2022 20:28:14 -0400, legg <legg@nospam.magma.ca> wrote: > >>On Fri, 12 Aug 2022 12:47:59 -0700, John Larkin >><jjlarkin@highlandtechnology.com> wrote: >> >>>I figured that I could bootstrap an LT Spice sample/hold to make a >>>stairstep waveform. >>> >>>Without the RC, the output jumps to +10 volts at the first clock edge. >>>And the RC has to be right to get a proper stairstep. >>> >> >>So it works with the RC - suggests a linear condition is >>permitted at the sampling time. Perhaps the internal >>gates aren't timed to prevent signal shoot-through. >> >>RL > >I can't understand it. Even 1K and 1 fF allows it to make a staircase. >But 1K and 0 fF doesn't. > >Obviously something is goofy inside the s/h model, but I wouldn't know >how to accomplish that. > >I can do what I want to do, by adding an RC, but I don't understand >it.The S/H input has no current flow. Perhaps the modeler forgot a default zin. RL
Reply by ●August 13, 20222022-08-13
On Fri, 12 Aug 2022 18:41:32 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:>On Fri, 12 Aug 2022 20:28:14 -0400, legg <legg@nospam.magma.ca> wrote: > >>On Fri, 12 Aug 2022 12:47:59 -0700, John Larkin >><jjlarkin@highlandtechnology.com> wrote: >> >>>I figured that I could bootstrap an LT Spice sample/hold to make a >>>stairstep waveform. >>> >>>Without the RC, the output jumps to +10 volts at the first clock edge. >>>And the RC has to be right to get a proper stairstep. >>> >> >>So it works with the RC - suggests a linear condition is >>permitted at the sampling time. Perhaps the internal >>gates aren't timed to prevent signal shoot-through. >> >>RL > >I can't understand it. Even 1K and 1 fF allows it to make a staircase. >But 1K and 0 fF doesn't. > >Obviously something is goofy inside the s/h model, but I wouldn't know >how to accomplish that. > >I can do what I want to do, by adding an RC, but I don't understand >it.In a sim where the staircase ends prematurely (C1<=1f), C1 has no current during the final, out-sized signal rise, though it shows well defined values in previous 'normal' steps. RL
