On 19/06/2021 04:55, Bill Sloman wrote:> On Tuesday, June 15, 2021 at 6:54:02 PM UTC+10, Bill Sloman wrote: >> On Tuesday, June 15, 2021 at 6:36:19 PM UTC+10, timo.k...@ibtk.de wrote: >>> Bill Sloman schrieb am Dienstag, 15. Juni 2021 um 08:40:23 UTC+2: > > <snip> > >>> Thank you for your effort! It's still very interesting! :) > > I hope this is a bit more interesting. I've just up-dated my copy of LT Spice 17, so I hope that components will now stay where I put them. > > This is about as simple as the circuit can get. The MOSFets are driven by a centre-tapped 6-turn winding (L5 and L6) and the EFD55-8 former has only got eight pins, which means that on a real circuit you'd have to improvise a bit. > > For the circuit to start the bias voltage on the centre tap has to be just high enough for both MOSFets to be turned on, which is a bit too high to let the circuit work properly once it running as intended. The network around D6, D7 and D8 lets bias voltage get pulled down to the point where the circuit will work correctly, once it is operating as intended. > > With values chosen, each of D7 and D8 is pulling current out of the bias node for about a quartrer the time, and I imagine that that will probably work over the tolerance range for the MOSFets M1 and M2 - Siliconix Si3.440DV parts which happened to be in the LT Spice component range. > > R8 damps the 2.5MHz parastic oscillation driven by the switching transients. A more complex design could have smaller switching transients, but it wouldn't be worth posting here. > > L14 is a totally dummy part - it exists to create the waveform V(cancelingV) which is there to make it easier to explain what L8 an L9 were put in to do. If you plot V(n009) + V(cancellingv) or V(n018) - V(cancellingv) you get pretty close to flat +200V and -200V traces, which are a lot easier to filter than the voltage coming out of the rectifiers. > > The circuit seems to deliver 4mA at +200V and -200V - 1.6 Watt - and draw 81mA at 24V - 1.95 Watt, which 82% efficiency. Two mA of the current drawn is setting up bias voltages. The inductor resistances aren't properly worked out, so this isn't all that reliable. > > I've been swapping e-mails with a couple of expert friends and the idea doesn't seem to be easy to get across. > > Version 4 > SHEET 1 1944 1284 > WIRE -1200 -848 -1312 -848 > WIRE -1088 -848 -1136 -848 > WIRE -944 -848 -1088 -848 > WIRE 0 -848 -944 -848 > WIRE 832 -848 0 -848 > WIRE 1712 -848 832 -848 > WIRE -944 -784 -944 -848 > WIRE 0 -704 0 -848 > WIRE -944 -672 -944 -704 > WIRE 832 -624 832 -848 > WIRE -656 -464 -704 -464 > WIRE -272 -464 -656 -464 > WIRE 96 -464 -208 -464 > WIRE 464 -464 176 -464 > WIRE 624 -464 464 -464 > WIRE -944 -368 -944 -608 > WIRE -544 -368 -944 -368 > WIRE -384 -368 -544 -368 > WIRE -704 -304 -704 -464 > WIRE -672 -304 -704 -304 > WIRE -384 -304 -384 -368 > WIRE -384 -304 -592 -304 > WIRE -240 -304 -384 -304 > WIRE 624 -304 624 -464 > WIRE 624 -304 -160 -304 > WIRE 832 -288 832 -544 > WIRE 1872 -288 832 -288 > WIRE 1872 -224 1872 -288 > WIRE 352 -160 -496 -160 > WIRE 464 -160 352 -160 > WIRE 704 -160 544 -160 > WIRE 832 -160 832 -288 > WIRE 832 -160 768 -160 > WIRE -1312 -112 -1312 -848 > WIRE 832 -80 832 -160 > WIRE -496 -64 -496 -160 > WIRE 352 -64 352 -160 > WIRE -1088 144 -1088 -848 > WIRE -400 176 -624 176 > WIRE 960 176 -320 176 > WIRE 1072 176 960 176 > WIRE 1200 176 1136 176 > WIRE 1280 176 1200 176 > WIRE 1424 176 1360 176 > WIRE 1584 176 1488 176 > WIRE 1792 176 1584 176 > WIRE -624 288 -624 176 > WIRE -400 288 -624 288 > WIRE -288 288 -400 288 > WIRE 912 288 -208 288 > WIRE 1072 288 912 288 > WIRE 1200 288 1200 176 > WIRE 1200 288 1136 288 > WIRE -944 384 -944 -368 > WIRE 1792 384 1792 176 > WIRE 624 400 624 -304 > WIRE -704 448 -704 -304 > WIRE 0 480 0 -624 > WIRE 240 480 0 480 > WIRE 352 480 352 0 > WIRE 352 480 320 480 > WIRE 432 480 352 480 > WIRE 576 480 512 480 > WIRE 1584 480 1584 176 > WIRE -944 512 -944 448 > WIRE -608 528 -656 528 > WIRE -496 528 -496 0 > WIRE -496 528 -528 528 > WIRE -288 528 -496 528 > WIRE -112 528 -208 528 > WIRE 0 528 0 480 > WIRE 0 528 -112 528 > WIRE 0 688 0 528 > WIRE 0 688 -240 688 > WIRE -240 768 -240 688 > WIRE 0 816 0 688 > WIRE -1312 976 -1312 -32 > WIRE -1088 976 -1088 208 > WIRE -1088 976 -1312 976 > WIRE -944 976 -944 576 > WIRE -944 976 -1088 976 > WIRE -704 976 -704 544 > WIRE -704 976 -944 976 > WIRE -400 976 -400 288 > WIRE -400 976 -704 976 > WIRE -240 976 -240 832 > WIRE -240 976 -400 976 > WIRE 0 976 0 896 > WIRE 0 976 -240 976 > WIRE 624 976 624 496 > WIRE 624 976 0 976 > WIRE 832 976 832 -16 > WIRE 832 976 624 976 > WIRE 1264 976 1264 592 > WIRE 1264 976 832 976 > WIRE 1584 976 1584 544 > WIRE 1584 976 1264 976 > WIRE 1664 976 1584 976 > WIRE 1792 976 1792 464 > WIRE 1792 976 1664 976 > WIRE 1824 976 1792 976 > WIRE 1872 976 1872 -160 > WIRE 1872 976 1824 976 > WIRE 1920 976 1872 976 > WIRE -1312 1008 -1312 976 > WIRE 1664 1024 1664 976 > WIRE 1824 1072 1824 976 > WIRE 960 1104 960 176 > WIRE 1104 1104 960 1104 > WIRE 1296 1104 1168 1104 > WIRE 912 1232 912 288 > WIRE 1104 1232 912 1232 > WIRE 1296 1232 1296 1104 > WIRE 1296 1232 1168 1232 > WIRE 1376 1232 1296 1232 > WIRE 1504 1232 1456 1232 > WIRE 1664 1232 1664 1088 > WIRE 1664 1232 1568 1232 > WIRE 1824 1232 1824 1152 > WIRE 1824 1232 1664 1232 > FLAG -1312 1008 0 > FLAG -544 -368 Vct > FLAG -656 -464 tank- > FLAG 1264 512 CancellingV > FLAG 464 -464 tank+ > FLAG -112 528 Bias > SYMBOL ind2 -688 -288 R270 > WINDOW 0 32 56 VTop 2 > WINDOW 3 4 56 VBottom 2 > SYMATTR InstName L1 > SYMATTR Value 0.176m > SYMATTR Type ind > SYMATTR SpiceLine Rser=0.088 Cpar=10p > SYMBOL ind2 -256 -288 R270 > WINDOW 0 32 56 VTop 2 > WINDOW 3 4 56 VBottom 2 > SYMATTR InstName L2 > SYMATTR Value 0.176m > SYMATTR Type ind > SYMATTR SpiceLine Rser=0.022 > SYMBOL cap -208 -480 R90 > WINDOW 0 0 32 VBottom 2 > WINDOW 3 46 32 VTop 2 > SYMATTR InstName C1 > SYMATTR Value 2.2n > SYMBOL res 464 480 M90 > WINDOW 0 -26 11 VBottom 2 > WINDOW 3 22 8 VTop 2 > SYMATTR InstName R1 > SYMATTR Value 10 > SYMBOL nmos 576 400 R0 > SYMATTR InstName M1 > SYMATTR Value Si3440DV > SYMBOL nmos -656 448 M0 > SYMATTR InstName M2 > SYMATTR Value Si3440DV > SYMBOL res -576 528 M90 > WINDOW 0 -18 21 VBottom 2 > WINDOW 3 19 15 VTop 2 > SYMATTR InstName R2 > SYMATTR Value 10 > SYMBOL ind2 -960 -800 R0 > SYMATTR InstName L7 > SYMATTR Value 2.2m > SYMATTR SpiceLine Ipk=5A Rser=0.8 Rpar=100k Cpar=10p > SYMBOL diode 1072 192 R270 > WINDOW 0 32 32 VTop 2 > WINDOW 3 0 32 VBottom 2 > SYMATTR InstName D1 > SYMATTR Value RFU02VS8S > SYMBOL diode 1072 304 R270 > WINDOW 0 32 32 VTop 2 > WINDOW 3 0 32 VBottom 2 > SYMATTR InstName D2 > SYMATTR Value RFU02VS8S > SYMBOL diode 1168 1088 R90 > WINDOW 0 0 32 VBottom 2 > WINDOW 3 32 32 VTop 2 > SYMATTR InstName D3 > SYMATTR Value RFU02VS8S > SYMBOL diode 1168 1216 R90 > WINDOW 0 0 32 VBottom 2 > WINDOW 3 32 32 VTop 2 > SYMATTR InstName D4 > SYMATTR Value RFU02VS8S > SYMBOL cap 1568 480 R0 > SYMATTR InstName C2 > SYMATTR Value 10n > SYMBOL cap 1648 1024 R0 > WINDOW 3 17 75 Left 2 > SYMATTR Value 10n > SYMATTR InstName C3 > SYMBOL res 1792 416 R0 > SYMATTR InstName R4 > SYMATTR Value 47k > SYMBOL res 1824 1104 R0 > SYMATTR InstName R5 > SYMATTR Value 47k > SYMBOL cap -1104 144 R0 > SYMATTR InstName C4 > SYMATTR Value 1µ > SYMBOL res 0 848 R0 > WINDOW 3 21 18 Left 2 > SYMATTR Value 4k3 > SYMATTR InstName R11 > SYMBOL ind2 -416 192 R270 > WINDOW 0 32 56 VTop 2 > WINDOW 3 4 56 VBottom 2 > SYMATTR InstName L4 > SYMATTR Value 12.2m > SYMATTR Type ind > SYMATTR SpiceLine Rser=10 Cpar=10p > SYMBOL ind2 -192 272 R90 > WINDOW 0 4 56 VBottom 2 > WINDOW 3 32 56 VTop 2 > SYMATTR InstName L3 > SYMATTR Value 12.2m > SYMATTR Type ind > SYMATTR SpiceLine Rser=10 Cpar=10p > SYMBOL zener -928 448 R180 > WINDOW 0 24 64 Left 2 > WINDOW 3 24 0 Left 2 > SYMATTR InstName D5 > SYMATTR Value 1N5371B > SYMBOL FerriteBead -944 544 R180 > SYMATTR InstName L15 > SYMATTR Value 12µ > SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p > SYMBOL ind2 1360 1248 R270 > WINDOW 0 32 56 VTop 2 > WINDOW 3 -6 69 VBottom 2 > SYMATTR InstName L9 > SYMATTR Value 153m > SYMATTR SpiceLine Rser=1 Cpar=10p > SYMBOL voltage -1312 -128 R0 > WINDOW 123 0 0 Left 0 > WINDOW 39 24 44 Left 2 > SYMATTR SpiceLine Rser=1 > SYMATTR InstName V1 > SYMATTR Value 24 > SYMBOL ind2 1376 160 R90 > WINDOW 0 4 56 VBottom 2 > WINDOW 3 48 56 VTop 2 > SYMATTR InstName L8 > SYMATTR Value 153m > SYMATTR SpiceLine Rser=1 Cpar=10p > SYMBOL FerriteBead 1456 176 R90 > WINDOW 0 -16 0 VBottom 2 > SYMATTR InstName L11 > SYMATTR Value 12µ > SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f > SYMBOL FerriteBead 1536 1232 R90 > WINDOW 0 -16 0 VBottom 2 > SYMATTR InstName L12 > SYMATTR Value 12µ > SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f mfg="Würth Elektronik" pn="74275010 WE-UKW 6050" > SYMBOL FerriteBead -944 -640 R180 > SYMATTR InstName L16 > SYMATTR Value 12µ > SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p > SYMBOL FerriteBead -1168 -848 R90 > WINDOW 0 -16 0 VBottom 2 > SYMATTR InstName L13 > SYMATTR Value 12µ > SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f > SYMBOL ind2 1248 496 R0 > SYMATTR InstName L14 > SYMATTR Value 153m > SYMBOL ind2 -192 512 R90 > WINDOW 0 4 56 VBottom 2 > WINDOW 3 32 56 VTop 2 > SYMATTR InstName L5 > SYMATTR Value 7.02µ > SYMBOL ind2 336 464 R90 > WINDOW 0 4 56 VBottom 2 > WINDOW 3 32 56 VTop 2 > SYMATTR InstName L6 > SYMATTR Value 7.02µ > SYMBOL res 0 -672 R0 > WINDOW 3 21 18 Left 2 > SYMATTR Value 18k > SYMATTR InstName R3 > SYMBOL cap -256 768 R0 > SYMATTR InstName C5 > SYMATTR Value 100n > SYMBOL res 832 -592 R0 > WINDOW 3 21 18 Left 2 > SYMATTR Value 15k > SYMATTR InstName R6 > SYMBOL diode -480 0 R180 > WINDOW 0 24 64 Left 2 > WINDOW 3 24 0 Left 2 > SYMATTR InstName D7 > SYMATTR Value 1N4148 > SYMBOL diode 368 0 R180 > WINDOW 0 24 64 Left 2 > WINDOW 3 24 0 Left 2 > SYMATTR InstName D8 > SYMATTR Value 1N4148 > SYMBOL res 512 -160 R90 > WINDOW 0 0 56 VBottom 2 > WINDOW 3 32 56 VTop 2 > SYMATTR InstName R7 > SYMATTR Value 820 > SYMBOL cap 1856 -224 R0 > SYMATTR InstName C6 > SYMATTR Value 100n > SYMBOL zener 848 -16 R180 > WINDOW 0 24 64 Left 2 > WINDOW 3 24 0 Left 2 > SYMATTR InstName D6 > SYMATTR Value BZX84C10L > SYMBOL res 128 -464 M90 > WINDOW 0 -18 21 VBottom 2 > WINDOW 3 19 15 VTop 2 > SYMATTR InstName R8 > SYMATTR Value 33 > SYMBOL FerriteBead 736 -160 R90 > WINDOW 0 -16 0 VBottom 2 > SYMATTR InstName L10 > SYMATTR Value 12µ > SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f > TEXT -1232 1032 Left 2 !.tran 0 10m 0m 10n > TEXT -1232 1096 Left 2 !K1 L1 L2 L3 L4 L5 L6 0.99 > TEXT -856 1032 Left 2 !.ic I(L7=1u) I(L1=1u) V(Bias)=3.824 > TEXT -848 1096 Left 2 !K2 L7 L8 L9 L14 0.99 >About half the resistors in that ASC schematic came misplaced and needed editting back onto their wires. I don't see the point of those ferrite beads. It works well. Looks to me like you have re-invented the Weinberg converter! piglet
Low noise, high bias voltage on picoAmp TIA's input, howto?
Started by ●May 21, 2021
Reply by ●June 19, 20212021-06-19
Reply by ●June 19, 20212021-06-19
On Saturday, June 19, 2021 at 5:37:42 PM UTC+10, piglet wrote:> On 19/06/2021 04:55, Bill Sloman wrote: > > On Tuesday, June 15, 2021 at 6:54:02 PM UTC+10, Bill Sloman wrote: > >> On Tuesday, June 15, 2021 at 6:36:19 PM UTC+10, timo.k...@ibtk.de wrote: > >>> Bill Sloman schrieb am Dienstag, 15. Juni 2021 um 08:40:23 UTC+2: > > > > <snip> > > > >>> Thank you for your effort! It's still very interesting! :) > > > > I hope this is a bit more interesting. I've just up-dated my copy of LT Spice 17, so I hope that components will now stay where I put them.<snip>> About half the resistors in that ASC schematic came misplaced and needed > editing back onto their wires.That's disappointing.> I don't see the point of those ferrite beads.Ferrite beads don't have much parallel capacitance. Wound components do. Ferrite beads tend to be cheap and compact, which helps. They do block fast current spikes, which cuts down radiated high frequency noise, which won't worry you until you put the board next to something sensitive, which always happens at the wrost possible moment.> It works well. Looks to me like you have re-invented the Weinberg converter!Wrong, if the Texas Instrument text about the Weinberg converter is anything to go by. https://www.ti.com/seclit/ug/slyu036/slyu036.pdf What I've described is a resonant converter, and it's unique selling point is that its rectified DC output doesn't look like a series of half-sine pulses, but has had that AC component cancelled out You may need to pay closer attention. As I said, "I've been swapping e-mails with a couple of expert friends and the idea doesn't seem to be easy to get across." Cursitor Doom would probably explain to me that this is because it isn't much of an idea, but he'd say that even if were a stroke of genius (which is unlikely to be any more correct). -- Bill Slona, Sydney
Reply by ●June 20, 20212021-06-20
On 19/06/2021 12:30, Bill Sloman wrote:> > Ferrite beads don't have much parallel capacitance. Wound components do. Ferrite beads tend to be cheap and compact, which helps. They do block fast current spikes, which cuts down radiated high frequency noise, which won't worry you until you put the board next to something sensitive, which always happens at the wrost possible moment. >Well, L10 is probably not doing much seeing as it is in series with 820 ohms R7?>> It works well. Looks to me like you have re-invented the Weinberg converter! > > Wrong, if the Texas Instrument text about the Weinberg converter is anything to go by. > > https://www.ti.com/seclit/ug/slyu036/slyu036.pdf > > What I've described is a resonant converter, and it's unique selling point is that its rectified DC output doesn't look like a series of half-sine pulses, but has had that AC component cancelled out > > You may need to pay closer attention. As I said, "I've been swapping e-mails with a couple of expert friends and the idea doesn't seem to be easy to get across." >I don't see why it should be hard to explain, the ripple cancellation scheme seems sound enough. I still contend it is conceptually broadly similar to Weinberg's low noise converter of ca 50 years ago. However I am worried that the parasitics of your simulated coils may be too low to be realizable easily in real life. For instance the 153mH L8 L9 were only given 10pF shunt capacitance. The secondary windings L3 L4 would probably be bifilar or at least share the same bobbin section but you gave them no end-to-end interwinding capacitance. The moment larger strays are included the rectifier current waveform changes radically. While the ripple cancellation scheme could be great at higher powers I think at this low power good enough results could be got using single coil off the peg discrete inductors for primary center-tap feed and choke input rectifiers. That also reduces primary side-secondary side capacitance as only one transformer is needed. BJTs can be easier to bias at these low powers. Here is my bastardization of your circuit, using off-the-shelf L7 L8 L9 inductors and a brute force second stage RC output filter to get 9mV p-p ripple. Version 4 SHEET 1 1944 1284 WIRE -128 -320 -592 -320 WIRE -32 -320 -128 -320 WIRE -32 -160 -32 -320 WIRE -128 -112 -128 -320 WIRE -592 -96 -592 -320 WIRE 384 -80 320 -80 WIRE 528 -80 464 -80 WIRE 640 -80 528 -80 WIRE 704 -80 640 -80 WIRE 816 -80 768 -80 WIRE 864 -80 816 -80 WIRE 1104 -80 944 -80 WIRE 1152 -80 1104 -80 WIRE 1280 -80 1232 -80 WIRE 1344 -80 1280 -80 WIRE 528 -48 528 -80 WIRE 1104 16 1104 -80 WIRE 320 32 320 -80 WIRE 384 32 320 32 WIRE 528 32 528 16 WIRE 528 32 464 32 WIRE 592 32 528 32 WIRE 704 32 592 32 WIRE 816 32 816 -80 WIRE 816 32 768 32 WIRE -32 64 -32 -80 WIRE 1280 144 1280 -80 WIRE -288 160 -320 160 WIRE -32 160 -32 64 WIRE -32 160 -208 160 WIRE 96 160 -32 160 WIRE 240 160 176 160 WIRE 640 160 640 -80 WIRE 592 256 592 32 WIRE 1104 288 1104 80 WIRE 1280 288 1280 208 WIRE 1280 288 1104 288 WIRE -320 336 -320 160 WIRE -272 336 -320 336 WIRE -16 336 -272 336 WIRE 112 336 48 336 WIRE 240 336 240 160 WIRE 240 336 192 336 WIRE 592 400 592 320 WIRE 640 400 640 224 WIRE 640 400 592 400 WIRE 688 400 640 400 WIRE 816 400 768 400 WIRE 848 400 816 400 WIRE 1008 400 928 400 WIRE 1040 400 1008 400 WIRE 1056 400 1040 400 WIRE 1344 400 1344 -80 WIRE 1008 432 1008 400 WIRE -320 448 -320 336 WIRE -272 448 -320 448 WIRE 240 448 240 336 WIRE 240 448 -208 448 WIRE 1056 448 1056 400 WIRE -320 544 -320 448 WIRE 240 544 240 448 WIRE 816 560 816 400 WIRE -128 592 -128 -32 WIRE -128 592 -256 592 WIRE -48 592 -128 592 WIRE 176 592 32 592 WIRE -592 720 -592 -16 WIRE -320 720 -320 640 WIRE -320 720 -592 720 WIRE 240 720 240 640 WIRE 240 720 -320 720 WIRE 320 720 320 32 WIRE 816 720 816 624 WIRE 816 720 320 720 WIRE 1008 720 1008 512 WIRE 1008 720 816 720 WIRE 1056 720 1056 512 WIRE 1056 720 1008 720 WIRE 1104 720 1104 288 WIRE 1104 720 1056 720 WIRE 1344 720 1344 480 WIRE 1344 720 1104 720 WIRE -592 752 -592 720 WIRE 1344 768 1344 720 FLAG -592 752 0 FLAG -32 64 Vct FLAG -272 336 tank- FLAG 240 336 tank+ FLAG 1344 768 0 FLAG 1344 -80 VOUT_P FLAG 1040 400 VOUT_N SYMBOL ind2 -304 176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L1 SYMATTR Value 0.176m SYMATTR Type ind SYMATTR SpiceLine Rser=0.5 Cpar=8p SYMBOL ind2 80 176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L2 SYMATTR Value 0.176m SYMATTR Type ind SYMATTR SpiceLine Rser=0.5 Cpar=8p SYMBOL cap 48 320 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 46 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 1n SYMBOL ind -48 -176 R0 SYMATTR InstName L7 SYMATTR Value 3.3m SYMATTR SpiceLine Rser=8 Cpar=18p SYMATTR Type ind2 SYMBOL diode 704 -64 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMATTR Value RFU02VS8S SYMBOL diode 704 48 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D2 SYMATTR Value RFU02VS8S SYMBOL diode 656 224 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D3 SYMATTR Value RFU02VS8S SYMBOL diode 608 320 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D4 SYMATTR Value RFU02VS8S SYMBOL cap 1088 16 R0 SYMATTR InstName C5 SYMATTR Value 47n SYMBOL cap 832 624 R180 WINDOW 3 24 8 Left 2 WINDOW 0 24 56 Left 2 SYMATTR Value 47n SYMATTR InstName C4 SYMBOL res 1328 384 R0 SYMATTR InstName R6 SYMATTR Value 47k SYMBOL res 1024 528 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R5 SYMATTR Value 47k SYMBOL ind2 368 -64 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L4 SYMATTR Value 12.2m SYMATTR Type ind SYMATTR SpiceLine Rser=10 Cpar=14p SYMBOL ind2 480 16 R90 WINDOW 0 4 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L3 SYMATTR Value 12.2m SYMATTR Type ind SYMATTR SpiceLine Rser=10 Cpar=14p SYMBOL ind 672 416 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 -6 69 VBottom 2 SYMATTR InstName L9 SYMATTR Value 100m SYMATTR SpiceLine Rser=190 Cpar=38p SYMATTR Type ind2 SYMBOL voltage -592 -112 R0 WINDOW 123 0 0 Left 0 WINDOW 39 24 44 Left 2 SYMATTR InstName V1 SYMATTR Value 24 SYMBOL ind 960 -96 R90 WINDOW 0 4 56 VBottom 2 WINDOW 3 48 56 VTop 2 SYMATTR InstName L8 SYMATTR Value 100m SYMATTR SpiceLine Rser=190 Cpar=38p SYMATTR Type ind2 SYMBOL ind2 48 576 R90 WINDOW 0 4 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L5 SYMATTR Value 3µ SYMATTR SpiceLine Cpar=1.5p SYMBOL res -144 -128 R0 WINDOW 3 21 18 Left 2 SYMATTR Value 22k SYMATTR InstName R1 SYMBOL res 96 320 M90 WINDOW 0 -18 21 VBottom 2 WINDOW 3 19 15 VTop 2 SYMATTR InstName R2 SYMATTR Value 56 SYMBOL npn 176 544 R0 SYMATTR InstName Q1 SYMATTR Value 2N5550 SYMBOL npn -256 544 M0 SYMATTR InstName Q2 SYMATTR Value 2N5550 SYMBOL cap 512 -48 R0 SYMATTR InstName C3 SYMATTR Value 220p SYMBOL cap -208 432 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 15p SYMBOL res 1136 -64 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL res 832 416 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL cap 1040 448 R0 SYMATTR InstName C6 SYMATTR Value 10n SYMBOL cap 1264 144 R0 SYMATTR InstName C7 SYMATTR Value 10n TEXT -648 832 Left 2 !.tran 0 10m 0m 10n TEXT -648 896 Left 2 !K1 L1 L2 L3 L4 L5 0.99 TEXT 920 -304 Left 2 ;EPW-BS-SED Jun 2021 P-P HV Converter TEXT -272 504 Left 2 ;Cprim stray piglet
Reply by ●June 20, 20212021-06-20
On Sunday, June 20, 2021 at 8:54:44 PM UTC+10, piglet wrote:> On 19/06/2021 12:30, Bill Sloman wrote: > > > > Ferrite beads don't have much parallel capacitance. Wound components do. Ferrite beads tend to be cheap and compact, which helps. They do block fast current spikes, which cuts down radiated high frequency noise, which won't worry you until you put the board next to something sensitive, which always happens at the worst possible moment. > > > Well, L10 is probably not doing much seeing as it is in series with 820 > ohms R7? > >> It works well. Looks to me like you have re-invented the Weinberg converter! > > > > Wrong, if the Texas Instrument text about the Weinberg converter is anything to go by. > > > > https://www.ti.com/seclit/ug/slyu036/slyu036.pdf > > > > What I've described is a resonant converter, and it's unique selling point is that its rectified DC output doesn't look like a series of half-sine pulses, but has had that AC component cancelled out > > > > You may need to pay closer attention. As I said, "I've been swapping e-mails with a couple of expert friends and the idea doesn't seem to be easy to get across." > > > I don't see why it should be hard to explain, the ripple cancellation scheme seems sound enough. I still contend it is conceptually broadly similar to Weinberg's low noise converter of ca 50 years ago.Which wasn't a resonant converter, and hasn't shown up on my radar at all.> However I am worried that the parasitics of your simulated coils may be too low to be realizable easily in real life. For instance the 153mH L8 L9 were only given 10pF shunt capacitance.I was figuring that they'd have to be bank wound to get them that low. There was a time when you could buy four-section coil formers for some RM cores that made that reasonably practical. I posted a bit on calculating these capacitances here, back in 2013.> The secondary windings L3 L4 would probably be bifilar or at least share the same bobbin section but you gave them no end-to-end interwinding capacitance.You certainly wouldn't wind the output windings as twisted pair - as you say, it would introduce a lot of inter-winding capacitance. It's perfectly calculable, once you've worked out the wire diameter, got the thickness of the insulation and worked out the length of twisted pair in the winding. If at all possible I'd put them on separate bobbin sections.> The moment larger strays are included the rectifier current waveform changes radically.They form part of the tank circuit - that's what make the Baxandall approach attractive, since all the strays are all coupled into one closely coupled tank circuit. If you do it exactly right , you don't need a tank capacitor at all, because the strays will do the whole job. The dielectric isn't ideal.> While the ripple cancellation scheme could be great at higher powers I think at this low power good enough results could be got using single coil off the peg discrete inductors for primary center-tap feed and choke input rectifiers.Obviously - that's what everybody has been doing since 1959. There are a lot of products on the market that demonstrate exactly this point.> That also reduces primary side-secondary side capacitance as only one transformer is needed.You definitely need the primary side inductor, if you want Baxandall level efficiencies. My point was that if you added two over-windings to that inductor you could use them to cancel the AC voltage on the rectified output.> BJTs can be easier to bias at these low powers.But - as Baxandall pointed out in 1959 - if you make the primary side inductor too big, the circuit can "squeg". He didn't know what was going on, and I don't either (though I do have my suspoicions), but if you use LT Spice to look at a version of a BJTdriven circuit with a big primary side inductor it won't squeg - during startup the inductor pulls the centre-tap below the rail, but this eventually goes away in the simulation, which doesn't happen in real life My guess is that reflects a defect in the Gummel-Poon model of the BJT in inverted operation. The VBIC model might do better, but the semi-conductor business treats VBIC models as commercial in confidence. MOSFet drivers don't seem to have the same problem. Your circuit reverse biases your transistor base-emitter junction by about 4V. Anything more than 6V blows them up. Your 3u (actually 3.12u) is two turns on the EFD15-5-8 core. Don't get greedy and use three.> Here is my bastardization of your circuit, using off-the-shelf L7 L8 L9 inductors and a brute force second stage RC output filter to get 9mV p-p ripple.It's perfectly sensible, and that's what people have been doing since 1959. It consequently isn't actually all that interesting. -- Bill Sloman, Sydney
Reply by ●June 23, 20212021-06-23
On Saturday, June 19, 2021 at 1:55:27 PM UTC+10, Bill Sloman wrote:> On Tuesday, June 15, 2021 at 6:54:02 PM UTC+10, Bill Sloman wrote: > > On Tuesday, June 15, 2021 at 6:36:19 PM UTC+10, timo.k...@ibtk.de wrote: > > > Bill Sloman schrieb am Dienstag, 15. Juni 2021 um 08:40:23 UTC+2: > <snip> > > > Thank you for your effort! It's still very interesting! :) > I hope this is a bit more interesting. I've just up-dated my copy of LT Spice 17, so I hope that components will now stay where I put them. > > This is about as simple as the circuit can get. The MOSFets are driven by a centre-tapped 6-turn winding (L5 and L6) and the EFD55-8 former has only got eight pins, which means that on a real circuit you'd have to improvise a bit. > > For the circuit to start the bias voltage on the centre tap has to be just high enough for both MOSFets to be turned on, which is a bit too high to let the circuit work properly once it running as intended. The network around D6, D7 and D8 lets bias voltage get pulled down to the point where the circuit will work correctly, once it is operating as intended. > > With values chosen, each of D7 and D8 is pulling current out of the bias node for about a quartrer the time, and I imagine that that will probably work over the tolerance range for the MOSFets M1 and M2 - Siliconix Si3.440DV parts which happened to be in the LT Spice component range. > > R8 damps the 2.5MHz parastic oscillation driven by the switching transients. A more complex design could have smaller switching transients, but it wouldn't be worth posting here. > > L14 is a totally dummy part - it exists to create the waveform V(cancelingV) which is there to make it easier to explain what L8 an L9 were put in to do. If you plot V(n009) + V(cancellingv) or V(n018) - V(cancellingv) you get pretty close to flat +200V and -200V traces, which are a lot easier to filter than the voltage coming out of the rectifiers. > > The circuit seems to deliver 4mA at +200V and -200V - 1.6 Watt - and draw 81mA at 24V - 1.95 Watt, which 82% efficiency. Two mA of the current drawn is setting up bias voltages. The inductor resistances aren't properly worked out, so this isn't all that reliable. > > I've been swapping e-mails with a couple of expert friends and the idea doesn't seem to be easy to get across.I've been thinking about a more complicated solution, and the one that comes to mind would use a 4046 to generate a roughly 5MHz clock and a cheap programmable logic device - the XC2C64A-7VQG44C comes to mind, though it isn't all that cheap - to divide this down to generate two roughly 100kHz non-over-lapping drive waveforms for the MOSFets, plus a square wave to drive one of the phase comparators on the 4046, to lock it to the nominally 100kHz sine wave coming out of a one turn winding on the transformer (L5 in the "simple' circuit). Divide by fifty is a six-stage binary counter, so the XC2C64A with it's 64 cells is bigger than necessary. The ICT PA7024 which I used back in 1992 would probably be quite big enough. The tank circuit doesn't do anything silly if you drive it off-resonance - the peak voltages move away from 90 degrees and 270 degrees, which the phase comparator can detect and use to lock the actual operating frequency to the resonant frequency, even if moves as the inductor warms up -- Bill Sloman, Sydney
Reply by ●June 26, 20212021-06-26
On Thursday, June 24, 2021 at 12:09:31 AM UTC+10, Bill Sloman wrote:> On Saturday, June 19, 2021 at 1:55:27 PM UTC+10, Bill Sloman wrote: > > On Tuesday, June 15, 2021 at 6:54:02 PM UTC+10, Bill Sloman wrote: > > > On Tuesday, June 15, 2021 at 6:36:19 PM UTC+10, timo.k...@ibtk.de wrote: > > > > Bill Sloman schrieb am Dienstag, 15. Juni 2021 um 08:40:23 UTC+2:<snip> I finally got around to reading the "zero ripple" paper < https://sci-hub.do/10.1109/tpel.2007.909192 > more carefully and it looks as if they want to run a Baxandall-like inverter a bit below resonance, which sort of works, but the centre tap voltage sits at 0V for an appreciable period each cycle, and peaks higher ( 46.14V in the example circuit below - versus 37.7V for an ideal Baxandall converter) while the current through the feed inductor peaks a bit higher. My ripple cancelling scheme doesn't work as well either but there's not a lot in it. It strikes that you could start the converter at a frequency that is guaranteed to be below the resonant frequency - 17% below the on-tolerance value should be enough for the circuit we've been looking at - and monitor the length of time that the centre tap stays close to the negative rail with something relatively slow (like a cheap single chip microprocessor) and inch it up until it gets close to value you'd see at the resonant frequency, and stick with that. Version 4 SHEET 1 1944 1396 WIRE -1888 -848 -2000 -848 WIRE -1776 -848 -1824 -848 WIRE -1632 -848 -1776 -848 WIRE 1712 -848 -1632 -848 WIRE -1632 -784 -1632 -848 WIRE -1632 -672 -1632 -704 WIRE -656 -464 -704 -464 WIRE -272 -464 -656 -464 WIRE 16 -464 -208 -464 WIRE 464 -464 96 -464 WIRE 624 -464 464 -464 WIRE -1632 -368 -1632 -608 WIRE -544 -368 -1632 -368 WIRE -384 -368 -544 -368 WIRE -704 -304 -704 -464 WIRE -672 -304 -704 -304 WIRE -384 -304 -384 -368 WIRE -384 -304 -592 -304 WIRE -240 -304 -384 -304 WIRE 624 -304 624 -464 WIRE 624 -304 -160 -304 WIRE 1872 -224 1872 -288 WIRE -2000 -112 -2000 -848 WIRE -1776 144 -1776 -848 WIRE -400 176 -624 176 WIRE 960 176 -320 176 WIRE 1072 176 960 176 WIRE 1200 176 1136 176 WIRE 1280 176 1200 176 WIRE 1424 176 1360 176 WIRE 1584 176 1488 176 WIRE 1792 176 1584 176 WIRE -624 288 -624 176 WIRE -400 288 -624 288 WIRE -288 288 -400 288 WIRE 912 288 -208 288 WIRE 1072 288 912 288 WIRE 1200 288 1200 176 WIRE 1200 288 1136 288 WIRE -1632 384 -1632 -368 WIRE 320 384 -1456 384 WIRE 1792 384 1792 176 WIRE 624 400 624 -304 WIRE -1456 480 -1456 384 WIRE 320 480 320 384 WIRE 432 480 320 480 WIRE 576 480 512 480 WIRE 1584 480 1584 176 WIRE -1632 512 -1632 448 WIRE -704 560 -704 -304 WIRE -912 640 -1008 640 WIRE -752 640 -832 640 WIRE -1008 816 -1008 640 WIRE -2000 1088 -2000 -32 WIRE -1776 1088 -1776 208 WIRE -1776 1088 -2000 1088 WIRE -1632 1088 -1632 576 WIRE -1632 1088 -1776 1088 WIRE -1456 1088 -1456 560 WIRE -1456 1088 -1632 1088 WIRE -1008 1088 -1008 896 WIRE -1008 1088 -1456 1088 WIRE -704 1088 -704 656 WIRE -704 1088 -1008 1088 WIRE -400 1088 -400 288 WIRE -400 1088 -704 1088 WIRE 624 1088 624 496 WIRE 624 1088 -400 1088 WIRE 1264 1088 1264 592 WIRE 1264 1088 624 1088 WIRE 1584 1088 1584 544 WIRE 1584 1088 1264 1088 WIRE 1664 1088 1584 1088 WIRE 1792 1088 1792 464 WIRE 1792 1088 1664 1088 WIRE 1824 1088 1792 1088 WIRE 1920 1088 1824 1088 WIRE -2000 1120 -2000 1088 WIRE 1664 1136 1664 1088 WIRE 1824 1184 1824 1088 WIRE 960 1216 960 176 WIRE 1104 1216 960 1216 WIRE 1296 1216 1168 1216 WIRE 912 1344 912 288 WIRE 1104 1344 912 1344 WIRE 1296 1344 1296 1216 WIRE 1296 1344 1168 1344 WIRE 1376 1344 1296 1344 WIRE 1504 1344 1456 1344 WIRE 1664 1344 1664 1200 WIRE 1664 1344 1568 1344 WIRE 1824 1344 1824 1264 WIRE 1824 1344 1664 1344 FLAG -2000 1120 0 FLAG -544 -368 Vct FLAG -656 -464 tank- FLAG 1264 512 CancellingV FLAG 464 -464 tank+ SYMBOL ind2 -688 -288 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L1 SYMATTR Value 0.176m SYMATTR Type ind SYMATTR SpiceLine Rser=0.088 Cpar=10p SYMBOL ind2 -256 -288 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L2 SYMATTR Value 0.176m SYMATTR Type ind SYMATTR SpiceLine Rser=0.022 SYMBOL cap -208 -480 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 46 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 2.2n SYMBOL res 464 480 M90 WINDOW 0 -26 11 VBottom 2 WINDOW 3 22 8 VTop 2 SYMATTR InstName R1 SYMATTR Value 22 SYMBOL nmos 576 400 R0 SYMATTR InstName M1 SYMATTR Value Si3440DV SYMBOL nmos -752 560 R0 SYMATTR InstName M2 SYMATTR Value Si3440DV SYMBOL res -880 640 M90 WINDOW 0 -18 21 VBottom 2 WINDOW 3 19 15 VTop 2 SYMATTR InstName R2 SYMATTR Value 22 SYMBOL ind2 -1648 -800 R0 SYMATTR InstName L7 SYMATTR Value 2.2m SYMATTR SpiceLine Ipk=5A Rser=0.8 Rpar=100k Cpar=10p SYMBOL diode 1072 192 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMATTR Value RFU02VS8S SYMBOL diode 1072 304 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D2 SYMATTR Value RFU02VS8S SYMBOL diode 1168 1200 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D3 SYMATTR Value RFU02VS8S SYMBOL diode 1168 1328 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D4 SYMATTR Value RFU02VS8S SYMBOL cap 1568 480 R0 SYMATTR InstName C2 SYMATTR Value 10n SYMBOL cap 1648 1136 R0 WINDOW 3 17 75 Left 2 SYMATTR Value 10n SYMATTR InstName C3 SYMBOL res 1792 416 R0 SYMATTR InstName R4 SYMATTR Value 47k SYMBOL res 1824 1216 R0 SYMATTR InstName R5 SYMATTR Value 47k SYMBOL cap -1792 144 R0 SYMATTR InstName C4 SYMATTR Value 1µ SYMBOL ind2 -416 192 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L4 SYMATTR Value 12.2m SYMATTR Type ind SYMATTR SpiceLine Rser=10 Cpar=10p SYMBOL ind2 -192 272 R90 WINDOW 0 4 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L3 SYMATTR Value 12.2m SYMATTR Type ind SYMATTR SpiceLine Rser=10 Cpar=10p SYMBOL zener -1616 448 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D5 SYMATTR Value 1N5375B SYMBOL FerriteBead -1632 544 R180 SYMATTR InstName L15 SYMATTR Value 12µ SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p SYMBOL ind2 1360 1360 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 -6 69 VBottom 2 SYMATTR InstName L9 SYMATTR Value 153m SYMATTR SpiceLine Rser=1 Cpar=10p SYMBOL voltage -2000 -128 R0 WINDOW 123 0 0 Left 0 WINDOW 39 24 44 Left 2 SYMATTR SpiceLine Rser=1 SYMATTR InstName V1 SYMATTR Value 24 SYMBOL ind2 1376 160 R90 WINDOW 0 4 56 VBottom 2 WINDOW 3 48 56 VTop 2 SYMATTR InstName L8 SYMATTR Value 153m SYMATTR SpiceLine Rser=1 Cpar=10p SYMBOL FerriteBead 1456 176 R90 WINDOW 0 -16 0 VBottom 2 SYMATTR InstName L11 SYMATTR Value 12µ SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f SYMBOL FerriteBead 1536 1344 R90 WINDOW 0 -16 0 VBottom 2 SYMATTR InstName L12 SYMATTR Value 12µ SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f mfg="Würth Elektronik" pn="74275010 WE-UKW 6050" SYMBOL FerriteBead -1632 -640 R180 SYMATTR InstName L16 SYMATTR Value 12µ SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p SYMBOL FerriteBead -1856 -848 R90 WINDOW 0 -16 0 VBottom 2 SYMATTR InstName L13 SYMATTR Value 12µ SYMATTR SpiceLine Ipk=3 Rser=0.0083 Rpar=880 Cpar=715f SYMBOL ind2 1248 496 R0 SYMATTR InstName L14 SYMATTR Value 153m SYMBOL voltage -1008 800 R0 WINDOW 123 0 0 Left 0 WINDOW 39 24 44 Left 2 SYMATTR SpiceLine Rser=1 SYMATTR InstName V2 SYMATTR Value PULSE(0 8 0u 25n 25n 5.95u 12u 11000) SYMBOL voltage -1456 464 R0 WINDOW 123 0 0 Left 0 WINDOW 39 24 44 Left 2 SYMATTR SpiceLine Rser=1 SYMATTR InstName V3 SYMATTR Value PULSE(0 8 6u 25n 25n 5.95u 12u 11000) SYMBOL res 48 -464 M90 WINDOW 0 -26 11 VBottom 2 WINDOW 3 22 8 VTop 2 SYMATTR InstName R3 SYMATTR Value 33 TEXT -1920 1144 Left 2 !.tran 0 10m 0m 10n TEXT -1792 1208 Left 2 !K1 L1 L2 L3 L4 0.99 TEXT -856 1144 Left 2 !.ic I(L7=1u) I(L1=1u) V(Bias)=5) TEXT -848 1208 Left 2 !K2 L7 L8 L9 L14 0.99 -- Bill Sloman, Sydney
Reply by ●July 2, 20212021-07-02
On Saturday, June 26, 2021 at 6:50:39 PM UTC+10, Anthony William Sloman wrote:> On Thursday, June 24, 2021 at 12:09:31 AM UTC+10, Bill Sloman wrote: > > On Saturday, June 19, 2021 at 1:55:27 PM UTC+10, Bill Sloman wrote: > > > On Tuesday, June 15, 2021 at 6:54:02 PM UTC+10, Bill Sloman wrote: > > > > On Tuesday, June 15, 2021 at 6:36:19 PM UTC+10, timo.k...@ibtk.de wrote: > > > > > Bill Sloman schrieb am Dienstag, 15. Juni 2021 um 08:40:23 UTC+2: > > <snip> > I finally got around to reading the "zero ripple" paper > > < https://sci-hub.do/10.1109/tpel.2007.909192 > > > more carefully and it looks as if they want to run a Baxandall-like inverter a bit below resonance, which sort of works, but the centre tap voltage sits at 0V for an appreciable period each cycle, and peaks higher ( 46.14V in the example circuit below - versus 37.7V for an ideal Baxandall converter) while the current through the feed inductor peaks a bit higher. > > My ripple cancelling scheme doesn't work as well either but there's not a lot in it. It strikes that you could start the converter at a frequency that is guaranteed to be below the resonant frequency - 17% below the on-tolerance value should be enough for the circuit we've been looking at - and monitor the length of time that the centre tap stays close to the negative rail with something relatively slow (like a cheap single chip microprocessor) and inch it up until it gets close to value you'd see at the resonant frequency, and stick with that.Cheap single chip microcontrollers seem to be quite quick these days. I've just had a look at the dsPIC33EPXXXGP50X data sheet http://ww1.microchip.com/downloads/en/devicedoc/ds-70657b.pdf It's 470 pages, and I only looked at the bit about the clock - pages 143-152 - which seems to suggest that you could clock at at 140Mz if you keep the chip cooler than 85C. Element 14 has 33 DSPIC33CK64MC105-I/PT in stock in Australia for couple of dollars each $A3.23 ($A3.55 including GST which I would have to pay). The programming kit would be more expensive. That's fast enough to do a proper non-overlapping drive for the Siliconix Si3440DV which has a worst case turn-on delay time of 15nsec, and a worst case turn-off delay time of 30nsec, which does imply half an amp of gate drive (or 1.6mA averaged over the whole duty cycle). The microcontroller draws up 35mA from 3.3Vwhen running at 70MIPs (which you probably wouldn't want to draw directly from a 24V rail) so you might be able to get a bit of current gain out of the 3.3V rail to make this happen relatively cheaply. -- Bill Sloman, Sydney
