On Sun, 30 May 2021 13:16:15 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>Joe Gwinn wrote: >> On Sat, 29 May 2021 18:24:16 -0400, Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >>> Joe Gwinn wrote: >>>> On Sat, 29 May 2021 16:29:27 -0400, Phil Hobbs >>>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>>> >>>>> Joe Gwinn wrote: >>>>>> On Fri, 28 May 2021 10:32:27 -0400, Phil Hobbs >>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>>>>> >>>>>>> Joe Gwinn wrote: >>>>>>>> On Thu, 27 May 2021 16:50:51 -0400, Phil Hobbs >>>>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>>>>>>> >>>>>>>>> timo.k...@ibtk.de wrote: >>>>>>>>>> Hi Phil, >>>>>>>>>> >>>>>>>>>> excuse the delay please, I got my second vaccination 2 hours >>>>>>>>>> ago. direct link: https://de1lib.org/dl/5420567/4762b2 It >>>>>>>>>> seems to change the hash daily (the part following last >>>>>>>>>> slash). alternatively: >>>>>>>>>> https://de1lib.org/book/5420567/adfe6c?id=5420567&secret=adfe6c >>>>>>>>>> >>>>>>>>>> >>>>> Thank you for sharing your valuable experiences! >>>>>>>>>> >>>>>>>>>> Cheeers, Timo >>>>>>>>>> >>>>>>>>> Thanks. I made an OCRed version using >>>>>>>>> https://djvu.org/any2djvu, which seems to work fine. >>>>>>>> >>>>>>>> It wants a password, and my security software was wailing about >>>>>>>> it. >>>>>>>> >>>>>>>> Joe >>>>>>>> >>>>>>> >>>>>>> No password required when I use it. >>>>>> >>>>>> I just checked again, got the djvu password request. >>>>>> >>>>>> You may have your credentials cached, so it doesn't keep asking you. >>>>>> >>>>>> If you come in using a private browser window, what happens? >>>>>> >>>>>> Joe Gwinn >>>>>> >>>>> >>>>> Weird. If I just type djvu.org into the address bar, it comes up in >>>>> http:// and works normally. The https:// thing works as you say. >>>>> >>>>> Use the http:// one. ;0 >>>> >>>> Using plain http did get rid of the password dialog, and did get me to >>>> the any2djvu page, which is not an OCRed copy of anything. >>>> >>>> Joe Gwinn >>>> >>> >>> Try it out on an actual PDF. There are several options for getting >>> embedded text, two of which involve OCR. I've done hundreds of >>> documents that way, from one-pagers up to full-length books. It's Good >>> Medicine. >> >> Ahh. I thought that an already OCRed pdf was there. I don't have the >> original pdf yet. Where do I find that? >> >> Thanks, >> >> Joe Gwinn >> >Timo's link above.Got it. Thanks. I have already read a library copy, but wanted a copy for reference. The key idea that is useful outside of metrology is using toroid cores around the coaxial cables to force center and shield currents to be exactly equal but opposite, like a transmission-line balun. Joe Gwinn
Low noise, high bias voltage on picoAmp TIA's input, howto?
Started by ●May 21, 2021
Reply by ●May 31, 20212021-05-31
Reply by ●June 1, 20212021-06-01
On Friday, May 28, 2021 at 11:26:41 PM UTC+10, Bill Sloman wrote:> On Friday, May 28, 2021 at 6:03:40 PM UTC+10, timo.k...@ibtk.de wrote: > > Bill Sloman schrieb am Freitag, 28. Mai 2021 um 07:24:52 UTC+2: > > > > > LTSpice 17 did better, but the circuit is horribly messed up with resistors not hooked up and in the wrong place. I've made a start at making the schematic look more like something that would work, but it isn't going quickly, and the saturatable transformer model doesn't seem to have made it. > > > Using the John Chan model for saturation is nice, but does it seem to make the schematic very messy. > > > Using a bipolar transistor to drive the transformer may not help the efficiency - they do need base drive (though the FTZ694B is a high gain part) and they don't pull the collector as low as a good MOSFET pulls it drain, particularly when you have Schottky diodes in series with the emitters .... > > > > > Good morning Bill, > > > > excuse me please, I did not tell about usage. > > You should expand the zip with another program than LTSpice and put all files in _one_ (working) directory. You may prefer a new one but not necessarily. LTSpice grabs all needed symbols from there, also the modified res.asy. > > This is explained here: > > https://www.mikrocontroller.net/topic/373488#4226728 > > > > I sent you an email containing the single files. > > > > The chan model or the schematics become much more clear by using the Symbols: > > Trafo_1pri_1sek.asy > > or > > Trafo_3pri_2sek.asy > > which has to carry the identical name as ist's nets: > > trafo_1pri_1sek.asc > > or > > Trafo_3pri_2sek.asc > Thanks. I had to put in three ferrite beads - I picked the 1uH Wurth parts from the LTSpice list - and add a Spice model for the FTZ694B - but after that the circuit did simulate and produced sensible waveforms. I had to stretch the simulation periods out to 10msec - there was something odd happening around 2.2msec. > > The model description is put into the *.asc files, the upper-/lowercase does not seem to be a problem. > > > > The original resistors use a bad placed origin, it should be in the middle of the symbol. Additionaly I like to know, which is pin 1 in the schematic (e.g. to determine the direction of the current flow). > > > > One may prove the power wasted by e.g. the bipolars using [Alt]+[left mouse button] on it. It is low in comparison to the whole efficiency loss. > > If I prefer FETs, I have to watch Vgs or complicate the gate-controls due to the 24V power which translates into (Pi)*24V=75V at the drains. > > I agree that MOSFETs are bit trickier to drive than bipolar transistors - I tend to use a one turn base drive coil between the bases of a PNP long-tail pair, and switch the tail current between two gate to source resistors. but you typically have a 20V rating between gate and source, which allows plenty of head-room. > > 75V isn't a problem. The Rohm RSQ030N08HZG - at 3A peak current - is a bit bigger than you'd need, but element-14 have 102 in stock for about a dollar each. > > http://www.farnell.com/datasheets/2918432.pdf > > I am still not sure which version would be the more suitable for that application. At least I saw the bipolar version working. ;) > > Bipolar transistors can give you squegging - which LT Spice doesn't simulate because it seems to depend on something odd that inverted bipolar transistors that the Gummell-Poon model doesn't capture.Here's a more conventional LT Spice model of a MOSFet driven inverter. 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1312 736 WIRE 1472 736 1440 736 WIRE 1552 736 1472 736 WIRE -1312 768 -1312 736 WIRE 1312 784 1312 736 WIRE 1472 832 1472 736 WIRE 608 864 608 208 WIRE 752 864 608 864 WIRE 944 864 816 864 WIRE 560 992 560 288 WIRE 752 992 560 992 WIRE 944 992 944 864 WIRE 944 992 816 992 WIRE 992 992 944 992 WIRE 1088 992 1056 992 WIRE 1312 992 1312 848 WIRE 1312 992 1168 992 WIRE 1472 992 1472 912 WIRE 1472 992 1312 992 FLAG -1312 768 0 FLAG -544 -16 Vct FLAG -640 -112 tank- FLAG -128 -112 tank+ DATAFLAG 1328 208 "" SYMBOL ind2 -688 64 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L1 SYMATTR Value 0.176m SYMATTR Type ind SYMATTR SpiceLine Rser=0.088 Cpar=10p SYMBOL ind2 -256 64 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L2 SYMATTR Value 0.176m SYMATTR Type ind SYMATTR SpiceLine Rser=0.022 SYMBOL cap -384 -128 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 46 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 2.2n SYMBOL voltage -1312 -128 R0 WINDOW 123 0 0 Left 0 WINDOW 39 24 132 Left 0 SYMATTR SpiceLine Rser=0.001 SYMATTR InstName V1 SYMATTR Value 24 SYMBOL ind2 -192 -320 M90 WINDOW 0 4 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L5 SYMATTR Value 780n SYMATTR Type ind SYMATTR SpiceLine Rser=0.004 Cpar=1pF SYMBOL res -304 -592 R0 SYMATTR InstName R14 SYMATTR Value 2k2 SYMBOL res 192 448 M90 WINDOW 0 -26 11 VBottom 2 WINDOW 3 22 8 VTop 2 SYMATTR InstName R1 SYMATTR Value 22 SYMBOL nmos 272 368 R0 SYMATTR InstName M1 SYMATTR Value Si3440DV SYMBOL nmos -656 352 M0 SYMATTR InstName M2 SYMATTR Value Si3440DV SYMBOL res -560 432 M90 WINDOW 0 -18 21 VBottom 2 WINDOW 3 19 15 VTop 2 SYMATTR InstName R2 SYMATTR Value 22 SYMBOL ind2 -960 -336 R0 SYMATTR InstName L6 SYMATTR Value 2.2m SYMATTR SpiceLine Ipk=5A Rser=0.8 Rpar=100k Cpar=10p SYMBOL diode 720 224 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D1 SYMATTR Value RFU02VS8S SYMBOL diode 720 304 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D2 SYMATTR Value RFU02VS8S SYMBOL diode 816 848 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D3 SYMATTR Value RFU02VS8S SYMBOL diode 816 976 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D4 SYMATTR Value RFU02VS8S SYMBOL cap 1216 480 R0 SYMATTR InstName C2 SYMATTR Value 10n SYMBOL cap 1296 784 R0 WINDOW 3 17 75 Left 2 SYMATTR Value 10n SYMATTR InstName C3 SYMBOL FerriteBead 928 208 R90 WINDOW 0 -16 0 VBottom 2 SYMATTR InstName L7 SYMATTR Value 12µ SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p SYMBOL FerriteBead 1024 992 R90 WINDOW 0 -16 0 VBottom 2 SYMATTR InstName L8 SYMATTR Value 12µ SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p mfg="Würth Elektronik" pn="7427501 WE-UKW 40060" SYMBOL res 1440 416 R0 SYMATTR InstName R4 SYMATTR Value 820k SYMBOL res 1472 864 R0 SYMATTR InstName R5 SYMATTR Value 820k SYMBOL res 1136 992 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 1k SYMBOL res 1088 208 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 1k SYMBOL cap -1104 144 R0 SYMATTR InstName C4 SYMATTR Value 100nF SYMBOL pnp -240 -256 R180 SYMATTR InstName Q1 SYMBOL pnp 48 -256 M180 SYMATTR InstName Q2 SYMBOL res -304 592 R0 SYMATTR InstName R3 SYMATTR Value 1k5 SYMBOL res 112 608 R0 WINDOW 3 13 26 Left 2 SYMATTR Value 1k5 SYMATTR InstName R9 SYMBOL res -32 -560 R0 SYMATTR InstName R10 SYMATTR Value 11k SYMBOL res 0 480 R0 SYMATTR InstName R11 SYMATTR Value 13k SYMBOL cap 144 -576 R0 SYMATTR InstName C5 SYMATTR Value 10n SYMBOL FerriteBead -944 -144 R180 SYMATTR InstName L3 SYMATTR Value 12µ SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p SYMBOL ind2 -544 224 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L4 SYMATTR Value 5m SYMATTR Type ind SYMATTR SpiceLine Rser=10 Cpar=10p SYMBOL ind2 -224 304 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 -2 57 VBottom 2 SYMATTR InstName L9 SYMATTR Value 5m SYMATTR Type ind SYMATTR SpiceLine Rser=10 Cpar=10p TEXT -1232 792 Left 2 !.tran 0 10m 0m 100n TEXT -1232 856 Left 2 !K1 L1 L2 L3 L4 L5 0.99 Seems to work. Startup is messy. The MOSFet was picked from what LT Spice offered - it isn't all that cheap. The transformer is what Timo seems to have used, but I haven't worked out wire sizes and layering. The single turn winding - L5 - would presumably be at the bottom pf the stack, tucked in a corner under the centre-tapped primary, which I'd probably wind as as 15 turns of twisted pair. The secondaries are 80 turns each, which might be one layer each of 0.1mm wire - maybe 0.6mm with there layers of 0.06mm tape - but you still have 1.6 mm of height for the primaries, which should be plenty. Two layer secondaries might work too. -- Bill Sloman, Sydney
Reply by ●June 1, 20212021-06-01
Bill Sloman 28.05.2021, 15:26:41 (vor 4 Tagen) Hi Bill, Excuse for the delay, please!> I had to put in three ferrite beads - I picked the 1uH Wurth parts from the LTSpice list...The simulation run always better without ferrites at the end, the inductance produced ringing.> I had to stretch the simulation periods out to 10msec - there was something odd happening around 2.2msec.Yes, it should! Because the load changes at this time.> I agree that MOSFETs are bit trickier to drive than bipolar transistors - I tend to use a one turn base drive coil between the bases of a PNP long-tail pair, and switch the tail current between two gate to source resistors. but you typically have a 20V rating between gate and source, which allows plenty of head-room.I fiddled around with some vriations of the FET's gate control. All ended up in a more complicated but not necessarily "smoother" working circuits. The startup of the FET-based oscillator is much faster at the cost of a huge overshoot and much higher startup currents.> but element-14 have 102 in stock for about a dollar each.Wer are "lucky" to have the "time" problem only. I am the only one working on the analog part of this (and a few other) projects. Mostly we have to deliver only a few modules/systems to our scientific customers. So the part costs are not the main issue in most cases.> Bipolar transistors can give you squegging - which LT Spice doesn't simulate because it seems to depend on something odd that inverted bipolar transistors that the Gummell-Poon model doesn't capture. > In fact, that seems to have been what was gong on from 2.0 msec to about 2.7msec. > The current through L7 started going negative - to about -5mA, and there were a negative current spikes through Q1 and Q2. > The problem is that this goes away in Spice simulations, but have been known to persist in real life. In real life you'd probably reduce the inductance of L7 until it went away.Hmm, for sure? I don't know exactly. See https://ibtk.de/project/hzdr/Fameio-presentation/20210521_Fameio.html 20210531_FAMEIO_SuperSIMS-MV40-Ersatz_S40.pdf Abb. 7.25: The oscillator was not optimised for no-load conditions, see Ic(Q1/2) spikes and it’s negative part. Raising the value of R11 compensates it. Even the choke current goes partly negative. Raising the choke’s value lowers amplitude of the current and prevents it from going negative. Abb. 7.26: Effects of raising the values of R11 and the choke. In my opinion the BJT based variant seems to be more robust, more simple and has a smoother startup. The latest simulations showed >80% overall efficiency at 250kHz except core losses, which haven't been simulated. The no load power consumption is safely below 500mW (partly below 250mW). After all I trust the simulation in principle (because the circuit behaved very similar on the bench) and will build up (wind the transformer) the latest version for tests. Your last circuit runs the simulation promptly but does not start nor oscillate normally. One cycle in 2ms. At least on my PC (LTSpice17). Maybe, the LTSpice versions behave different? Thank you! Cheers, Timo
Reply by ●June 1, 20212021-06-01
On Tuesday, June 1, 2021 at 7:48:11 PM UTC+10, timo.k...@ibtk.de wrote:> Bill Sloman > 28.05.2021, 15:26:41 (vor 4 Tagen) > > Hi Bill, > > Excuse for the delay, please! > > > I had to put in three ferrite beads - I picked the 1uH Wurth parts from the LTSpice list... > > The simulation run always better without ferrites at the end, the inductance produced ringing.Real circuits use ferrite beads to contain ringing.> > I had to stretch the simulation periods out to 10msec - there was something odd happening around 2.2msec. > > Yes, it should! Because the load changes at this time.That doesn't tie up with what was going on.> > I agree that MOSFETs are bit trickier to drive than bipolar transistors - I tend to use a one turn base drive coil between the bases of a PNP long-tail pair, and switch the tail current between two gate to source resistors. but you typically have a 20V rating between gate and source, which allows plenty of head-room. > > I fiddled around with some variations of the FET's gate control. All ended up in a more complicated but not necessarily "smoother" working circuits. > The startup of the FET-based oscillator is much faster at the cost of a huge overshoot and much higher startup currents.If you use a large inductor (as you did) start up does involve the centre-tap voltage going well above what you see when the circuit has settled down, and the inductor pulling the centre-tap below ground during start-up. With bipolar transistors this gets you into squegging, which persists. If you put a high voltage zener between the centre-tap and ground - something like 40V - it will cap the centre tap-voltage, when it goes over 38V, and divert the negative current to ground, and the start-up would be briefer and cleaner. The messy start-up isn't a consequence of the FET drive.> > but element-14 have 102 in stock for about a dollar each. > > We are "lucky" to have the "time" problem only. I am the only one working on the analog part of this (and a few other) projects. Mostly we have to deliver only a few modules/systems to our scientific customers. So the part costs are not the main issue in most cases. > > > Bipolar transistors can give you squegging - which LT Spice doesn't simulate because it seems to depend on something odd that inverted bipolar transistors that the Gummell-Poon model doesn't capture. > > In fact, that seems to have been what was gong on from 2.0 msec to about 2.7msec. > > The current through L7 started going negative - to about -5mA, and there were a negative current spikes through Q1 and Q2. > > The problem is that this goes away in Spice simulations, but have been known to persist in real life. In real life you'd probably reduce the inductance of L7 until it went away. > > Hmm, for sure? I don't know exactly. > See https://ibtk.de/project/hzdr/Fameio-presentation/20210521_Fameio.html > 20210531_FAMEIO_SuperSIMS-MV40-Ersatz_S40.pdfSimulations aren't real life.> Abb. 7.25: The oscillator was not optimised for no-load conditions, see Ic(Q1/2) spikes and it’s negative part. Raising the value of R11 compensates it. > Even the choke current goes partly negative. Raising the choke’s value lowers amplitude of the current and prevents it from going negative. > Abb. 7.26: Effects of raising the values of R11 and the choke. > > In my opinion the BJT based variant seems to be more robust, more simple and has a smoother startup.You may need to revise that opinion. The start-up isn't a problem with actual circuits I've worked with, unless it persists - when it is called squegging. Baxandall's paper only refers to it in a footnote on page 752. I've run into it in real life, and the late Tony Williams had seen more of it than he liked. It's not problem that persists with MOSFet drive.> The latest simulations showed >80% overall efficiency at 250kHz except core losses, which haven't been simulated. The no load power consumption is safely below 500mW (partly below 250mW). > After all I trust the simulation in principle (because the circuit behaved very similar on the bench) and will build up (wind the transformer) the latest version for tests. > > Your last circuit runs the simulation promptly but does not start nor oscillate normally. One cycle in 2ms. At least on my PC (LTSpice17). Maybe, the LTSpice versions behave different?Starting oscillators in LTSpice is pest. Real circuits have enough asymmetry so they start up fast. Simulated circuits are much more symmetrical. My circuit did take a few msec start, which is why I let the simulation run for 10msec to let it settle down. You can fiddle the initial conditions to get them to start faster, but that takes work and it's rarely worth the effort. -- Bill Sloman, Sydney
Reply by ●June 2, 20212021-06-02
On Wednesday, June 2, 2021 at 12:27:56 AM UTC+10, Bill Sloman wrote:> On Tuesday, June 1, 2021 at 7:48:11 PM UTC+10, timo.k...@ibtk.de wrote: > > Bill Sloman > > 28.05.2021, 15:26:41 (vor 4 Tagen) > > > > Hi Bill, > > > > Excuse for the delay, please! > > > > > I had to put in three ferrite beads - I picked the 1uH Wurth parts from the LTSpice list... > > > > The simulation run always better without ferrites at the end, the inductance produced ringing. > > Real circuits use ferrite beads to contain ringing. > > > > I had to stretch the simulation periods out to 10msec - there was something odd happening around 2.2msec. > > > > Yes, it should! Because the load changes at this time. > > That doesn't tie up with what was going on. > > > > I agree that MOSFETs are bit trickier to drive than bipolar transistors - I tend to use a one turn base drive coil between the bases of a PNP long-tail pair, and switch the tail current between two gate to source resistors. but you typically have a 20V rating between gate and source, which allows plenty of head-room. > > > > I fiddled around with some variations of the FET's gate control. All ended up in a more complicated but not necessarily "smoother" working circuits. > > The startup of the FET-based oscillator is much faster at the cost of a huge overshoot and much higher startup currents. > > If you use a large inductor (as you did) start up does involve the centre-tap voltage going well above what you see when the circuit has settled down, and the inductor pulling the centre-tap below ground during start-up. With bipolar transistors this gets you into squegging, which persists. If you put a high voltage zener between the centre-tap and ground - something like 40V - it will cap the centre tap-voltage, when it goes over 38V, and divert the negative current to ground, and the start-up would be briefer and cleaner. > > The messy start-up isn't a consequence of the FET drive.In fact what was going on was that the current though feed inductor L6 - went up to 12.6A before the oscillator started oscillating at all, and it started off at 7kHz, moving up to 100kHz with about a millisecond. You power supply isn't going to deliver 12A and real components are different enough that the oscillation would have got going earlier. -- Bill Sloman, Sydney
Reply by ●June 2, 20212021-06-02
Reply by ●June 2, 20212021-06-02
On 27/05/2021 18:52, timo.k...@ibtk.de wrote:> Hi Phil, > > excuse the delay please, I got my second vaccination 2 hours ago. > direct link: > https://de1lib.org/dl/5420567/4762b2 > It seems to change the hash daily (the part following last slash). > alternatively: > https://de1lib.org/book/5420567/adfe6c?id=5420567&secret=adfe6c > Thank you for sharing your valuable experiences! > > Cheeers, Timo >Note that the IET published a book co-authored by Kibble called "Coaxial Electrical Circuits for Interference-free Measurements" which is still in print. It covers the information in Kibble's earlier book.
Reply by ●June 2, 20212021-06-02
On Wednesday, June 2, 2021 at 1:10:25 PM UTC+10, Bill Sloman wrote:> On Wednesday, June 2, 2021 at 12:27:56 AM UTC+10, Bill Sloman wrote: > > On Tuesday, June 1, 2021 at 7:48:11 PM UTC+10, timo.k...@ibtk.de wrote: > > > Bill Sloman > > > 28.05.2021, 15:26:41 (vor 4 Tagen)<snip>> In fact what was going on was that the current though feed inductor L6 - went up to 12.6A before the oscillator started oscillating at all, and it started off at 7kHz, moving up to 100kHz with about a millisecond. > > You power supply isn't going to deliver 12A and real components are different enough that the oscillation would have got going earlier.I've tweaked my simulation by adding 22R to the 24V source, which pulls the initial peak current through L6 down to less than an amp. I threw in a zener to limit the peak centre tap voltage, but added a ferrite bead to kill some very high frequency ringing which showed up on the capacitative current through the zener in regular operatoin. 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R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 1k SYMBOL res 1088 208 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 1k SYMBOL cap -1104 144 R0 SYMATTR InstName C4 SYMATTR Value 100nF SYMBOL pnp -240 -256 R180 SYMATTR InstName Q1 SYMBOL pnp 48 -256 M180 SYMATTR InstName Q2 SYMBOL res -304 592 R0 SYMATTR InstName R3 SYMATTR Value 1k5 SYMBOL res 112 608 R0 WINDOW 3 13 26 Left 2 SYMATTR Value 1k5 SYMATTR InstName R9 SYMBOL res -32 -560 R0 SYMATTR InstName R10 SYMATTR Value 11k SYMBOL res 0 480 R0 SYMATTR InstName R11 SYMATTR Value 13k SYMBOL cap 144 -576 R0 SYMATTR InstName C5 SYMATTR Value 10n SYMBOL FerriteBead -944 -144 R180 SYMATTR InstName L3 SYMATTR Value 12µ SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p SYMBOL ind2 -544 224 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L4 SYMATTR Value 5m SYMATTR Type ind SYMATTR SpiceLine Rser=10 Cpar=10p SYMBOL ind2 -224 304 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 -2 57 VBottom 2 SYMATTR InstName L9 SYMATTR Value 5m SYMATTR Type ind SYMATTR SpiceLine Rser=10 Cpar=10p SYMBOL zener -928 448 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D5 SYMATTR Value 1N5371B SYMBOL FerriteBead -944 544 R180 SYMATTR InstName L10 SYMATTR Value 12µ SYMATTR SpiceLine Ipk=3 Rser=0.0118 Rpar=870 Cpar=1.1p SYMBOL res -1136 -704 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 22 TEXT -1232 792 Left 2 !.tran 0 10m 0m 100n TEXT -1232 856 Left 2 !K1 L1 L2 L3 L4 L5 0.99 -- Bill Sloman, Sydney
Reply by ●June 12, 20212021-06-12
A Resonant DC-DC transformer with Zero Current Ripple https://www.semanticscholar.org/paper/A-Resonant-DC-DC-transformer-with-Zero-Current-Abramovitz-Smedley/25b64c261fbe69200035b905ad8010814d8a0535
Reply by ●June 12, 20212021-06-12
On Saturday, June 12, 2021 at 7:19:41 PM UTC+10, Dmitriy Pshonkin wrote:> A Resonant DC-DC transformer with Zero Current Ripple > https://www.semanticscholar.org/paper/A-Resonant-DC-DC-transformer-with-Zero-Current-Abramovitz-Smedley/25b64c261fbe69200035b905ad8010814d8a0535It costs money to see it. The Cuk converter from 1983 https://ieeexplore.ieee.org/document/1062238 offered ripple-free output (if I remember rightly - and I had to dig a bit to come up with the name). I looked at it at the time, and it looked a bit expensive for what it offered. -- Bill Sloman, Sydney
