digital capacitor

A few people make digital caps. This one is nice:

https://www.mouser.com/ProductDetail/IXYS-Integrated-Circuits/NCD2100TTR?qs=npTsUczJOtNXvd3UFPIV7g%3D%3D

I'm upgrading an oldish product that used a Maxim part that is, of
course, discontinued. Maxim won't even acknowledge the old part
number. Nobody in the world seems to have any.

The Ixys part has three cap groups, coarse/medium/fine, with 10 bits
total. The transfer function code to capacitance is sawtooth shaped,
not monotonic, which guarantees that any cap value in the full range
has some code that will hit it within one LSB.

I'm coarse tuning an LC oscillator at powerup, to be close to 50 MHz,
so that a varicap can take over and swing it to exactly 50.

John Larkin <jlarkin@highland_atwork_technology.com> wrote:

> A few people make digital caps. This one is nice:
> 
> https://www.mouser.com/ProductDetail/IXYS-Integrated-Circuits/NCD2100TTR?
> qs=npTsUczJOtNXvd3UFPIV7g%3D%3D 
> 
> I'm upgrading an oldish product that used a Maxim part that is, of
> course, discontinued. Maxim won't even acknowledge the old part
> number. Nobody in the world seems to have any.
> 
> The Ixys part has three cap groups, coarse/medium/fine, with 10 bits
> total. The transfer function code to capacitance is sawtooth shaped,
> not monotonic, which guarantees that any cap value in the full range
> has some code that will hit it within one LSB.
> 
> I'm coarse tuning an LC oscillator at powerup, to be close to 50 MHz,
> so that a varicap can take over and swing it to exactly 50.

Unquestionably the worst capacitors on the market: -705pm/VCC, +41.4ppm/C, 
+/- 25% tolerance, no data on quality factor, limited frequency range. 

Might as well put a strand of spaghetti in a linear actuator and measure 
the aroma as a function of stretch.

Trimming LC oscillators is a well-established topic with many options to 
choose from. A digital cap is probably the worst one.

Why not design the oscillator so the varicap has enough range to 
accommodate all the component tolerances? Then you won't need a digicap 
and complex power up circutry.




-- 
The best designs occur in the theta state. - sw

On Fri, 16 Apr 2021 08:09:11 -0000 (UTC), Steve Wilson <spam@me.com>
wrote:

>John Larkin <jlarkin@highland_atwork_technology.com> wrote:
>
>> A few people make digital caps. This one is nice:
>> 
>> https://www.mouser.com/ProductDetail/IXYS-Integrated-Circuits/NCD2100TTR?
>> qs=npTsUczJOtNXvd3UFPIV7g%3D%3D 
>> 
>> I'm upgrading an oldish product that used a Maxim part that is, of
>> course, discontinued. Maxim won't even acknowledge the old part
>> number. Nobody in the world seems to have any.
>> 
>> The Ixys part has three cap groups, coarse/medium/fine, with 10 bits
>> total. The transfer function code to capacitance is sawtooth shaped,
>> not monotonic, which guarantees that any cap value in the full range
>> has some code that will hit it within one LSB.
>> 
>> I'm coarse tuning an LC oscillator at powerup, to be close to 50 MHz,
>> so that a varicap can take over and swing it to exactly 50.
>
>Unquestionably the worst capacitors on the market: -705pm/VCC, +41.4ppm/C, 
>+/- 25% tolerance, no data on quality factor, limited frequency range. 

Hi-k ceramics are far, far worse. Electrolytics too. There is a graph
on the data sheet of q vs frequency: 50 to 100 at my frequency, and
it's just the trimmer. Everything has a limited frequency range.

The oscillator is temperature compensated. The inductor and the FR4
capacitance gang up to give it a negative TC. This digicap hardly
matters.

Tolerance doesn't matter: it's a trimmer!

You seem crabby today. That distorts objectivity.

>
>Might as well put a strand of spaghetti in a linear actuator and measure 
>the aroma as a function of stretch.
>
>Trimming LC oscillators is a well-established topic with many options to 
>choose from. A digital cap is probably the worst one.

Do I have to give the money back?

>
>Why not design the oscillator so the varicap has enough range to 
>accommodate all the component tolerances? Then you won't need a digicap 
>and complex power up circutry.

Varicaps are terrible. They have huge TCs that are a function of the
applied voltage. I want to minimize the pull range of the varicap.
That keeps phase noise down too.

I first did this sort of PLL with a piston cap for the coarse tune,
but the digital cap is way cheaper and smaller and autotunes every
powerup.

Here's the gadget:

http://www.highlandtechnology.com/DSS/T564DS.shtml

We're going to do a very minor redesign now, with the new digicap, to
hold us over for a year maybe. Then it needs a full redesign; too many
parts are going eol, including the 68K uP and an old FPGA. And the
Maxim digital cap of course.

The old design has parts on both sides. With modern power supplies and
a Zynq, I think it might fit on one side.

https://www.dropbox.com/s/1hj4ckpmsdu8d55/T560_Board.JPG?raw=1



-- 

John Larkin      Highland Technology, Inc

The best designs are necessarily accidental.


  

On Thu, 15 Apr 2021 17:45:54 -0700, John Larkin
<jlarkin@highland_atwork_technology.com> wrote:

>A few people make digital caps. This one is nice:
>
>https://www.mouser.com/ProductDetail/IXYS-Integrated-Circuits/NCD2100TTR?qs=npTsUczJOtNXvd3UFPIV7g%3D%3D
>
>I'm upgrading an oldish product that used a Maxim part that is, of
>course, discontinued. Maxim won't even acknowledge the old part
>number. Nobody in the world seems to have any.
>
>The Ixys part has three cap groups, coarse/medium/fine, with 10 bits
>total. The transfer function code to capacitance is sawtooth shaped,
>not monotonic, which guarantees that any cap value in the full range
>has some code that will hit it within one LSB.
>
>I'm coarse tuning an LC oscillator at powerup, to be close to 50 MHz,
>so that a varicap can take over and swing it to exactly 50.

Pretty sure ONS discontinued a bunch of these before 2010, but could 
only find one or two other parts in files. Peregrine, Intersil and 
Xycor(?). Ranges typically below 15pF.

RL

RL

jlarkin@highlandsniptechnology.com wrote:

> On Fri, 16 Apr 2021 08:09:11 -0000 (UTC), Steve Wilson <spam@me.com>
> wrote:

>>John Larkin <jlarkin@highland_atwork_technology.com> wrote:

>>> A few people make digital caps. This one is nice:

>>> https://www.mouser.com/ProductDetail/IXYS-Integrated-Circuits/NCD2100TT
>>> R? qs=npTsUczJOtNXvd3UFPIV7g%3D%3D

>>> I'm upgrading an oldish product that used a Maxim part that is, of
>>> course, discontinued. Maxim won't even acknowledge the old part
>>> number. Nobody in the world seems to have any.

>>> The Ixys part has three cap groups, coarse/medium/fine, with 10 bits
>>> total. The transfer function code to capacitance is sawtooth shaped,
>>> not monotonic, which guarantees that any cap value in the full range
>>> has some code that will hit it within one LSB.

>>> I'm coarse tuning an LC oscillator at powerup, to be close to 50 MHz,
>>> so that a varicap can take over and swing it to exactly 50.

>>Unquestionably the worst capacitors on the market: -705pm/VCC,
>>+41.4ppm/C, +/- 25% tolerance, no data on quality factor, limited
>>frequency range.

> Hi-k ceramics are far, far worse. Electrolytics too. There is a graph
> on the data sheet of q vs frequency: 50 to 100 at my frequency, and
> it's just the trimmer. Everything has a limited frequency range.

The question is why is there a limit. What is the reason?

> The oscillator is temperature compensated. The inductor and the FR4
> capacitance gang up to give it a negative TC. This digicap hardly
> matters.

> Tolerance doesn't matter: it's a trimmer!

[...]

>>Why not design the oscillator so the varicap has enough range to
>>accommodate all the component tolerances? Then you won't need a digicap
>>and complex power up circutry.

> Varicaps are terrible. They have huge TCs that are a function of the
> applied voltage. I want to minimize the pull range of the varicap.
> That keeps phase noise down too.

The NXP BB201 dual varicap has a temco of 0.6% at 0.5V, 0.15% at 10V.

The ESR is 0.25 ohm at 100 MHz and 3V bias. This gives 60 pF. 

Xc at 50 MHz is 53 ohms so Q = 53 / 0.25 = 212.

So the phase noise would better than the digicap.

> I first did this sort of PLL with a piston cap for the coarse tune,
> but the digital cap is way cheaper and smaller and autotunes every
> powerup.

How do you accomodate drift between powerups?

> Here's the gadget:

> http://www.highlandtechnology.com/DSS/T564DS.shtml

> We're going to do a very minor redesign now, with the new digicap, to
> hold us over for a year maybe. Then it needs a full redesign; too many
> parts are going eol, including the 68K uP and an old FPGA. And the
> Maxim digital cap of course.

> The old design has parts on both sides. With modern power supplies and
> a Zynq, I think it might fit on one side.

> https://www.dropbox.com/s/1hj4ckpmsdu8d55/T560_Board.JPG?raw=1

Presumably, you use a ramp to interpolate between the 50 MHz clock
pulses. This allows you to trigger the output pulse when the ramp
crosses the voltage set by a DAC, and the desired number of 50 MHz
clocks have passed.

You could use the 50 MHz clock to set the timing instead of an LC
oscillator.

You could use another identical ramp to find the time of the input
trigger by clocking an ADC.

Combine the two values to determine the settings for the output
pulse.

This would give much lower drift and jitter, and eliminate the setup
at power on. The changes would probably fit in the same board area.

You could upgrade the 50 MHz clock to a low noise OCXO for even lower drift 
and jitter. You could also use stable external clocks, such as rubidium or 
GPSDO for the ultimate in long term stability.





-- The best designs occur in the theta state. - sw

On Tue, 20 Apr 2021 20:04:24 -0000 (UTC), Steve Wilson <spam@me.com>
wrote:

>jlarkin@highlandsniptechnology.com wrote:
>
>> On Fri, 16 Apr 2021 08:09:11 -0000 (UTC), Steve Wilson <spam@me.com>
>> wrote:
>
>>>John Larkin <jlarkin@highland_atwork_technology.com> wrote:
>
>>>> A few people make digital caps. This one is nice:
>
>>>> https://www.mouser.com/ProductDetail/IXYS-Integrated-Circuits/NCD2100TT
>>>> R? qs=npTsUczJOtNXvd3UFPIV7g%3D%3D
>
>>>> I'm upgrading an oldish product that used a Maxim part that is, of
>>>> course, discontinued. Maxim won't even acknowledge the old part
>>>> number. Nobody in the world seems to have any.
>
>>>> The Ixys part has three cap groups, coarse/medium/fine, with 10 bits
>>>> total. The transfer function code to capacitance is sawtooth shaped,
>>>> not monotonic, which guarantees that any cap value in the full range
>>>> has some code that will hit it within one LSB.
>
>>>> I'm coarse tuning an LC oscillator at powerup, to be close to 50 MHz,
>>>> so that a varicap can take over and swing it to exactly 50.
>
>>>Unquestionably the worst capacitors on the market: -705pm/VCC,
>>>+41.4ppm/C, +/- 25% tolerance, no data on quality factor, limited
>>>frequency range.
>
>> Hi-k ceramics are far, far worse. Electrolytics too. There is a graph
>> on the data sheet of q vs frequency: 50 to 100 at my frequency, and
>> it's just the trimmer. Everything has a limited frequency range.
>
>The question is why is there a limit. What is the reason?
>
>> The oscillator is temperature compensated. The inductor and the FR4
>> capacitance gang up to give it a negative TC. This digicap hardly
>> matters.
>
>> Tolerance doesn't matter: it's a trimmer!
>
>[...]
>
>>>Why not design the oscillator so the varicap has enough range to
>>>accommodate all the component tolerances? Then you won't need a digicap
>>>and complex power up circutry.
>
>> Varicaps are terrible. They have huge TCs that are a function of the
>> applied voltage. I want to minimize the pull range of the varicap.
>> That keeps phase noise down too.
>
>The NXP BB201 dual varicap has a temco of 0.6% at 0.5V, 0.15% at 10V.

That has way more capacitance than I need for trimming my oscillator.

>
>The ESR is 0.25 ohm at 100 MHz and 3V bias. This gives 60 pF. 
>
>Xc at 50 MHz is 53 ohms so Q = 53 / 0.25 = 212.
>
>So the phase noise would better than the digicap.

A varicap needs an analog voltage input, which I guess could come from
a DAC, which I don't have. That would have some noise. The digital cap
is fixed once it's set at powerup.

>
>> I first did this sort of PLL with a piston cap for the coarse tune,
>> but the digital cap is way cheaper and smaller and autotunes every
>> powerup.
>
>How do you accomodate drift between powerups?

It just worked, with a bit of active temperature compensation.

>
>> Here's the gadget:
>
>> http://www.highlandtechnology.com/DSS/T564DS.shtml
>
>> We're going to do a very minor redesign now, with the new digicap, to
>> hold us over for a year maybe. Then it needs a full redesign; too many
>> parts are going eol, including the 68K uP and an old FPGA. And the
>> Maxim digital cap of course.
>
>> The old design has parts on both sides. With modern power supplies and
>> a Zynq, I think it might fit on one side.
>
>> https://www.dropbox.com/s/1hj4ckpmsdu8d55/T560_Board.JPG?raw=1
>
>Presumably, you use a ramp to interpolate between the 50 MHz clock
>pulses. This allows you to trigger the output pulse when the ramp
>crosses the voltage set by a DAC, and the desired number of 50 MHz
>clocks have passed.
>
>You could use the 50 MHz clock to set the timing instead of an LC
>oscillator.

The 50 MHz LC oscillator is started at trigger time, and then
phase-locked to the crystal oscillator, which is a different
frequency. Time delays are programmable to 10 ps resolution, with
under 30 ps RMS jitter from an external trigger.

>
>You could use another identical ramp to find the time of the input
>trigger by clocking an ADC.

SRS does something like that, but it adds a lot of insertion delay.

One problem is that fast ADCs have a lot of pipeline delay.


>
>Combine the two values to determine the settings for the output
>pulse.
>
>This would give much lower drift and jitter, and eliminate the setup
>at power on. The changes would probably fit in the same board area.
>
>You could upgrade the 50 MHz clock to a low noise OCXO for even lower drift 
>and jitter. You could also use stable external clocks, such as rubidium or 
>GPSDO for the ultimate in long term stability.

As noted, the 50 MHz oscillator is started at trigger time.

On Wednesday, April 21, 2021 at 6:52:51 AM UTC+10, John Larkin wrote:
> On Tue, 20 Apr 2021 20:04:24 -0000 (UTC), Steve Wilson <sp...@me.com>
> wrote: 
> >jla...@highlandsniptechnology.com wrote:  
> >> On Fri, 16 Apr 2021 08:09:11 -0000 (UTC), Steve Wilson <sp...@me.com> 
> >> wrote: 
> >>>John Larkin <jlarkin@highland_atwork_technology.com> wrote: 

<snip>

> >You could use the 50 MHz clock to set the timing instead of an LC oscillator.
>
> The 50 MHz LC oscillator is started at trigger time, and then  phase-locked to the crystal oscillator, which is a different  frequency. Time delays are programmable to 10 ps resolution, with  under 30 ps RMS jitter from an external trigger.
> > 
> >You could use another identical ramp to find the time of the input trigger by clocking an ADC.
>
> SRS does something like that, but it adds a lot of insertion delay. 

That's what we did at Cambridge Instruments back in 1988-91. The whole story is written up on my website.

http://sophia-elektronica.com/The_first_stage.html

You'd have to dig through a lot of stuff to find anything relevant. We used an 800MHz local oscillator (phase-locked to a good 50MHz crystal oscillator) so digitising a 125nsec ramp to 5psec only took an 8-bit ADC. The ramp ran for longer than 125nsec but we used frequent auto calibration to make sure that the ramp stopped somewhere exactly within the voltage range the ADC could digitise.
 
> One problem is that fast ADCs have a lot of pipeline delay.

True, but two isn't any more of a problem that one, and fewer bits helps a lot.

> >Combine the two values to determine the settings for the output pulse. 

Exactly what we did.

> >This would give much lower drift and jitter, and eliminate the setup at power on. The changes would probably fit in the same board area. 

There's quite a lot of fast arithmetic involved, which we did in 100k ECL. Programmable logic has come a long way since then.
 
> >You could upgrade the 50 MHz clock to a low noise OCXO for even lower drift and jitter. You could also use stable external clocks, such as rubidium or 
GPSDO for the ultimate in long term stability. As noted, the 50 MHz oscillator is started at trigger time.

It's a remarkably expensive way of avoiding having two ramps and two ramp digitisers. When I reworked parts of the scheme a few years later for a very different application, I went for a crystal-controlled 500MHz oscillator - it would used a crystal that had been etched down until it was remarkably thin, if we'd ever been able to build the hardware.

John Larkin doesn't like the approach - he won't even dignify it by claiming that it wouldn't work - but it worked for me.

-- 
Bill Sloman, Sydney

On Tuesday, April 20, 2021 at 10:59:40 PM UTC-7, Bill Sloman wrote:
> That's what we did at Cambridge Instruments back in 1988-91. The whole story is written up on my website. 
> 
> http://sophia-elektronica.com/The_first_stage.html 

Those weekly reports are more interesting than they have any right to be. :)  Thanks for 
the read, detailed post-mortems of complicated projects are almost always worthwhile.

Having confessed your sins, you can stop beating yourself up for overlooking the 
column transit time now...

-- john, KE5FX

On Thursday, April 22, 2021 at 4:53:57 AM UTC+10, John Miles, KE5FX wrote:
> On Tuesday, April 20, 2021 at 10:59:40 PM UTC-7, Bill Sloman wrote: 
> > That's what we did at Cambridge Instruments back in 1988-91. The whole story is written up on my website. 
> > 
> > http://sophia-elektronica.com/The_first_stage.html
>
> Those weekly reports are more interesting than they have any right to be. :) Thanks for 
> the read, detailed post-mortems of complicated projects are almost always worthwhile. 
> 
> Having confessed your sins, you can stop beating yourself up for overlooking the 
> column transit time now... 

I didn't see it as beating myself up. I just got it wrong in a situation where I couldn't easily measure what I was estimating. Being rude about the fact that I didn't have easy access to a working system when it would have been useful, wouldn't have gone down well with my superiors (which wouldn't have worried me in the least) but also wouldn't have won me anything that I happened to need at the time. I did have an interest in getting people to tell me about things that weren't working out as expected, so confessing to my own error did make sense as setting an example.

-- 
Bill Sloman, Sydney

John Larkin <jlarkin@highland_atwork_technology.com> wrote:

> On Tue, 20 Apr 2021 20:04:24 -0000 (UTC), Steve Wilson <spam@me.com>
> wrote:

[...]

>>> Here's the gadget:

>>> http://www.highlandtechnology.com/DSS/T564DS.shtml

>>> https://www.dropbox.com/s/1hj4ckpmsdu8d55/T560_Board.JPG?raw=1

>>Presumably, you use a ramp to interpolate between the 50 MHz clock
>>pulses. This allows you to trigger the output pulse when the ramp
>>crosses the voltage set by a DAC, and the desired number of 50 MHz
>>clocks have passed.

>>You could use the 50 MHz clock to set the timing instead of an LC
>>oscillator.

> The 50 MHz LC oscillator is started at trigger time, and then
> phase-locked to the crystal oscillator, which is a different
> frequency. Time delays are programmable to 10 ps resolution, with
> under 30 ps RMS jitter from an external trigger.

Why spec resolution at 10 ps when the jitter is 30 ps? 

RMS is only 1 sigma. Practical jitter should be spec'd at 3 sigma,
which means the pulse can be +/- 90 ps from center. If you want to
get nasty, you should spec the jitter at 6 sigma to give a more
realistic idea of where the pulse could be.

>>You could use another identical ramp to find the time of the input
>>trigger by clocking an ADC.

> SRS does something like that, but it adds a lot of insertion delay.

I love their spec: "approximately 80 ns"

I have been studying SRS for some time. They have two models which
are different architectures. One model integrates the time between
the input trigger and the 100 MHz clock, which is not the same as
using a ramp. They have extremely complicated architectures, which
is due to the design philosophy in the '60s and '70s. You can tell
when they were designed by looking at the parts list.

> One problem is that fast ADCs have a lot of pipeline delay.

The Renesas KAD5510P-25Q48 has a latency of 7.5 cycles at 250 MHz.
This takes 30 ns, and would increase your insertion delay a bit.

However it would allow you to significantly reduce the 30 ns rms
jitter figure, and provide continuous calibration of the
interpolation ramp. $47.240 at Newark:

https://octopart.com/kad5510p-25q48-renesas-88256306?r=sp

https://datasheet.octopart.com/KAD5510P-25Q48-Renesas-datasheet-
138173667.pdf

>>Combine the two values to determine the settings for the output pulse.

>>This would give much lower drift and jitter, and eliminate the setup
>>at power on. The changes would probably fit in the same board area.

>>You could upgrade the 50 MHz clock to a low noise OCXO for even lower
>>drift and jitter. You could also use stable external clocks, such as
>>rubidium or GPSDO for the ultimate in long term stability.

> As noted, the 50 MHz oscillator is started at trigger time.

You can never achieve the low jitter of a crystal, and using DSP to
lock to a separate clock will add phase error and jitter.

Most important, you have no way to correct for drift in the
interpolation ramp.

With two identical ramps, you could continuously corect for any
drift in the ramps by comparing one ramp with 50 MHz clock, leaving
the other ramp free for the output pulse. Then swap roles on the
next 50 MHz clock.

So by adding an ADC and referring everything to a low noise crystal,
you can reduce the clock drift and jitter, and provide continuous
calibration of the interpolation ramps.



--
The best designs occur in the theta state. - sw