On 3.8.19 19:08, bitrex wrote:> On 8/3/19 12:06 PM, bitrex wrote: >> IRL I don't think there's anything this configuration of the 'HC74 >> could do but oscillate; with an RC network from not-Q to not-CLR and >> D, CLK, and not-PRE grounded. >> >> But with these models from the Yahoo LTSpice users group the LTSPice >> time domain looks like it manages to find some other metastable state >> and sits there spinning its wheels. >> >> Can anyone suggest some ICs that could bust it out and get it to >> square-wave in the sim? Thanks >> >> <https://imgur.com/a/Idv4LSs> > > plz use this link instead > > <https://imgur.com/a/ochGSav>Your circuit is simply wrong: there is a stable state with both Q- and CLR- high. The classic oscillator (though bad) is to use a Schmitt with integrating feedback. -- -TV
74HC74 oscillator simulation
Started by ●August 3, 2019
Reply by ●August 3, 20192019-08-03
Reply by ●August 3, 20192019-08-03
On 3.8.19 19:58, bitrex wrote:> On 8/3/19 12:24 PM, John Larkin wrote: >> On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote: >> >>> IRL I don't think there's anything this configuration of the 'HC74 could >>> do but oscillate; with an RC network from not-Q to not-CLR and D, CLK, >>> and not-PRE grounded. >>> >>> But with these models from the Yahoo LTSpice users group the LTSPice >>> time domain looks like it manages to find some other metastable state >>> and sits there spinning its wheels. >>> >>> Can anyone suggest some ICs that could bust it out and get it to >>> square-wave in the sim? Thanks >>> >>> <https://imgur.com/a/Idv4LSs> >> >> The voltage gain from \Q to \CLR is low, and there's no schmitt >> action, so you can get a stable negative feedback loop. It would >> likely oscillate at a higher frequency, where the logic prop delay >> becomes important. >> >> Why not use a schmitt inverter? This circuit could be rescued, but it >> would take more parts. >> >> Maybe "ground" C1 to Q? >> >> But I wouldn't trust the Spice models for what is basically analog >> behavior. >> >> > > Check this out someone actually got a patent for this back in 1990 (the > crystal probably helps a lot): > > <https://imgur.com/a/YryI2p6>An idea can be patented even if it does not work. -- -TV
Reply by ●August 3, 20192019-08-03
On Saturday, August 3, 2019 at 2:28:58 PM UTC-4, Tauno Voipio wrote:> On 3.8.19 19:08, bitrex wrote: > > On 8/3/19 12:06 PM, bitrex wrote: > >> IRL I don't think there's anything this configuration of the 'HC74 > >> could do but oscillate; with an RC network from not-Q to not-CLR and > >> D, CLK, and not-PRE grounded. > >> > >> But with these models from the Yahoo LTSpice users group the LTSPice > >> time domain looks like it manages to find some other metastable state > >> and sits there spinning its wheels. > >> > >> Can anyone suggest some ICs that could bust it out and get it to > >> square-wave in the sim? Thanks > >> > >> <https://imgur.com/a/Idv4LSs> > > > > plz use this link instead > > > > <https://imgur.com/a/ochGSav> > > Your circuit is simply wrong: there is a stable state > with both Q- and CLR- high.I think not. The PRE- pin is grounded. If CLR- is high the Q is 1 and Q- is 0. The circuit should work in simulation. If the waveform shown in the picture is anything relative to the Q- output, there is something logically wrong with the simulation... which is very possible if the FF doesn't initialize properly. -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
Reply by ●August 3, 20192019-08-03
On 8/3/19 2:40 PM, Rick C wrote:> On Saturday, August 3, 2019 at 2:28:58 PM UTC-4, Tauno Voipio wrote: >> On 3.8.19 19:08, bitrex wrote: >>> On 8/3/19 12:06 PM, bitrex wrote: >>>> IRL I don't think there's anything this configuration of the 'HC74 >>>> could do but oscillate; with an RC network from not-Q to not-CLR and >>>> D, CLK, and not-PRE grounded. >>>> >>>> But with these models from the Yahoo LTSpice users group the LTSPice >>>> time domain looks like it manages to find some other metastable state >>>> and sits there spinning its wheels. >>>> >>>> Can anyone suggest some ICs that could bust it out and get it to >>>> square-wave in the sim? Thanks >>>> >>>> <https://imgur.com/a/Idv4LSs> >>> >>> plz use this link instead >>> >>> <https://imgur.com/a/ochGSav> >> >> Your circuit is simply wrong: there is a stable state >> with both Q- and CLR- high. > > I think not. The PRE- pin is grounded. If CLR- is high the Q is 1 and Q- is 0. The circuit should work in simulation. If the waveform shown in the picture is anything relative to the Q- output, there is something logically wrong with the simulation... which is very possible if the FF doesn't initialize properly. >With the error that I made wrt setting parameters corrected and the sim tested such that the flip flop divides down and otherwise operates correctly here is the output in the former configuration, with more clear labeling of voltages. also no oscillation. <https://imgur.com/a/tHr6Qij>
Reply by ●August 3, 20192019-08-03
On Sat, 3 Aug 2019 21:31:15 +0300, Tauno Voipio <tauno.voipio@notused.fi.invalid> wrote:>On 3.8.19 19:58, bitrex wrote: >> On 8/3/19 12:24 PM, John Larkin wrote: >>> On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote: >>> >>>> IRL I don't think there's anything this configuration of the 'HC74 could >>>> do but oscillate; with an RC network from not-Q to not-CLR and D, CLK, >>>> and not-PRE grounded. >>>> >>>> But with these models from the Yahoo LTSpice users group the LTSPice >>>> time domain looks like it manages to find some other metastable state >>>> and sits there spinning its wheels. >>>> >>>> Can anyone suggest some ICs that could bust it out and get it to >>>> square-wave in the sim? Thanks >>>> >>>> <https://imgur.com/a/Idv4LSs> >>> >>> The voltage gain from \Q to \CLR is low, and there's no schmitt >>> action, so you can get a stable negative feedback loop. It would >>> likely oscillate at a higher frequency, where the logic prop delay >>> becomes important. >>> >>> Why not use a schmitt inverter? This circuit could be rescued, but it >>> would take more parts. >>> >>> Maybe "ground" C1 to Q? >>> >>> But I wouldn't trust the Spice models for what is basically analog >>> behavior. >>> >>> >> >> Check this out someone actually got a patent for this back in 1990 (the >> crystal probably helps a lot): >> >> <https://imgur.com/a/YryI2p6> > >An idea can be patented even if it does not work.For some people, getting patents is a kind of addiction. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●August 3, 20192019-08-03
On 8/3/19 2:40 PM, Rick C wrote:> On Saturday, August 3, 2019 at 2:28:58 PM UTC-4, Tauno Voipio wrote: >> On 3.8.19 19:08, bitrex wrote: >>> On 8/3/19 12:06 PM, bitrex wrote: >>>> IRL I don't think there's anything this configuration of the 'HC74 >>>> could do but oscillate; with an RC network from not-Q to not-CLR and >>>> D, CLK, and not-PRE grounded. >>>> >>>> But with these models from the Yahoo LTSpice users group the LTSPice >>>> time domain looks like it manages to find some other metastable state >>>> and sits there spinning its wheels. >>>> >>>> Can anyone suggest some ICs that could bust it out and get it to >>>> square-wave in the sim? Thanks >>>> >>>> <https://imgur.com/a/Idv4LSs> >>> >>> plz use this link instead >>> >>> <https://imgur.com/a/ochGSav> >> >> Your circuit is simply wrong: there is a stable state >> with both Q- and CLR- high. > > I think not. The PRE- pin is grounded. If CLR- is high the Q is 1 and Q- is 0. The circuit should work in simulation. If the waveform shown in the picture is anything relative to the Q- output, there is something logically wrong with the simulation... which is very possible if the FF doesn't initialize properly. >I think the oscillator relies on the 0/0 state at the not-PRE/not-CLR inputs being metastable to start up, but the model's state is not actually metastable.
Reply by ●August 3, 20192019-08-03
On Saturday, August 3, 2019 at 3:17:11 PM UTC-4, bitrex wrote:> On 8/3/19 2:40 PM, Rick C wrote: > > On Saturday, August 3, 2019 at 2:28:58 PM UTC-4, Tauno Voipio wrote: > >> On 3.8.19 19:08, bitrex wrote: > >>> On 8/3/19 12:06 PM, bitrex wrote: > >>>> IRL I don't think there's anything this configuration of the 'HC74 > >>>> could do but oscillate; with an RC network from not-Q to not-CLR and > >>>> D, CLK, and not-PRE grounded. > >>>> > >>>> But with these models from the Yahoo LTSpice users group the LTSPice > >>>> time domain looks like it manages to find some other metastable state > >>>> and sits there spinning its wheels. > >>>> > >>>> Can anyone suggest some ICs that could bust it out and get it to > >>>> square-wave in the sim? Thanks > >>>> > >>>> <https://imgur.com/a/Idv4LSs> > >>> > >>> plz use this link instead > >>> > >>> <https://imgur.com/a/ochGSav> > >> > >> Your circuit is simply wrong: there is a stable state > >> with both Q- and CLR- high. > > > > I think not. The PRE- pin is grounded. If CLR- is high the Q is 1 and Q- is 0. The circuit should work in simulation. If the waveform shown in the picture is anything relative to the Q- output, there is something logically wrong with the simulation... which is very possible if the FF doesn't initialize properly. > > > > I think the oscillator relies on the 0/0 state at the not-PRE/not-CLR > inputs being metastable to start up, but the model's state is not > actually metastable.Metastability is not needed. Gates in the FF drive the corresponding output high when each input is low. So both Q and Q- will be high when the CLR- input is low. There may be something going on internally if you were clocking it, but clock is grounded. This circuit is just an inverter between the CLR- and Q- signals. When RC went low, the Q- output should have gone high. Not sure what is still wrong, but again, I suggest you connect a square wave to the CLR- pin to test the operation of the FF. Q should stay high while Q- is the square wave inverted. What is going on with the initialization statement? I don't see a "res" signal. -- Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209
Reply by ●August 3, 20192019-08-03
On Sat, 3 Aug 2019 21:28:55 +0300, Tauno Voipio <tauno.voipio@notused.fi.invalid> wrote:>On 3.8.19 19:08, bitrex wrote: >> On 8/3/19 12:06 PM, bitrex wrote: >>> IRL I don't think there's anything this configuration of the 'HC74 >>> could do but oscillate; with an RC network from not-Q to not-CLR and >>> D, CLK, and not-PRE grounded. >>> >>> But with these models from the Yahoo LTSpice users group the LTSPice >>> time domain looks like it manages to find some other metastable state >>> and sits there spinning its wheels. >>> >>> Can anyone suggest some ICs that could bust it out and get it to >>> square-wave in the sim? Thanks >>> >>> <https://imgur.com/a/Idv4LSs> >> >> plz use this link instead >> >> <https://imgur.com/a/ochGSav> > >Your circuit is simply wrong: there is a stable state >with both Q- and CLR- high.But \preset is grounded.> >The classic oscillator (though bad) is to use a Schmitt >with integrating feedback.It's an off-label use, but most flops will act as a net inverter in that circuit. Spice may well not model that mode correctly. But the voltage gain is typically low so the whole thing might stabilize near Vcc/2. More phase shift around the loop can make it oscillate. A gated, edge-triggered one-shot is sometimes handy, so I've used a similar circuit to make a flop clear itself, but with a higher-order delay than the single RC. An RLC works, or a PCB trace delay line. A dual delay, RCRC, might work too. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●August 3, 20192019-08-03
On Sat, 3 Aug 2019 15:12:01 -0400, bitrex <user@example.net> wrote:>On 8/3/19 2:40 PM, Rick C wrote: >> On Saturday, August 3, 2019 at 2:28:58 PM UTC-4, Tauno Voipio wrote: >>> On 3.8.19 19:08, bitrex wrote: >>>> On 8/3/19 12:06 PM, bitrex wrote: >>>>> IRL I don't think there's anything this configuration of the 'HC74 >>>>> could do but oscillate; with an RC network from not-Q to not-CLR and >>>>> D, CLK, and not-PRE grounded. >>>>> >>>>> But with these models from the Yahoo LTSpice users group the LTSPice >>>>> time domain looks like it manages to find some other metastable state >>>>> and sits there spinning its wheels. >>>>> >>>>> Can anyone suggest some ICs that could bust it out and get it to >>>>> square-wave in the sim? Thanks >>>>> >>>>> <https://imgur.com/a/Idv4LSs> >>>> >>>> plz use this link instead >>>> >>>> <https://imgur.com/a/ochGSav> >>> >>> Your circuit is simply wrong: there is a stable state >>> with both Q- and CLR- high. >> >> I think not. The PRE- pin is grounded. If CLR- is high the Q is 1 and Q- is 0. The circuit should work in simulation. If the waveform shown in the picture is anything relative to the Q- output, there is something logically wrong with the simulation... which is very possible if the FF doesn't initialize properly. >> > >With the error that I made wrt setting parameters corrected and the sim >tested such that the flip flop divides down and otherwise operates >correctly here is the output in the former configuration, with more >clear labeling of voltages. also no oscillation. > ><https://imgur.com/a/tHr6Qij>You might try a real flop. The model may not properly handle this case. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●August 3, 20192019-08-03
On 8/3/19 3:47 PM, Rick C wrote:> On Saturday, August 3, 2019 at 3:17:11 PM UTC-4, bitrex wrote: >> On 8/3/19 2:40 PM, Rick C wrote: >>> On Saturday, August 3, 2019 at 2:28:58 PM UTC-4, Tauno Voipio wrote: >>>> On 3.8.19 19:08, bitrex wrote: >>>>> On 8/3/19 12:06 PM, bitrex wrote: >>>>>> IRL I don't think there's anything this configuration of the 'HC74 >>>>>> could do but oscillate; with an RC network from not-Q to not-CLR and >>>>>> D, CLK, and not-PRE grounded. >>>>>> >>>>>> But with these models from the Yahoo LTSpice users group the LTSPice >>>>>> time domain looks like it manages to find some other metastable state >>>>>> and sits there spinning its wheels. >>>>>> >>>>>> Can anyone suggest some ICs that could bust it out and get it to >>>>>> square-wave in the sim? Thanks >>>>>> >>>>>> <https://imgur.com/a/Idv4LSs> >>>>> >>>>> plz use this link instead >>>>> >>>>> <https://imgur.com/a/ochGSav> >>>> >>>> Your circuit is simply wrong: there is a stable state >>>> with both Q- and CLR- high. >>> >>> I think not. The PRE- pin is grounded. If CLR- is high the Q is 1 and Q- is 0. The circuit should work in simulation. If the waveform shown in the picture is anything relative to the Q- output, there is something logically wrong with the simulation... which is very possible if the FF doesn't initialize properly. >>> >> >> I think the oscillator relies on the 0/0 state at the not-PRE/not-CLR >> inputs being metastable to start up, but the model's state is not >> actually metastable. > > Metastability is not needed. Gates in the FF drive the corresponding output high when each input is low. So both Q and Q- will be high when the CLR- input is low. There may be something going on internally if you were clocking it, but clock is grounded. > > This circuit is just an inverter between the CLR- and Q- signals. > > When RC went low, the Q- output should have gone high. Not sure what is still wrong, but again, I suggest you connect a square wave to the CLR- pin to test the operation of the FF. Q should stay high while Q- is the square wave inverted.Doesn't pass any signal at all when I do that.> What is going on with the initialization statement? I don't see a "res" signal. >I removed some other stuff before posting but forgot that, sorry I found a thread on the Yahoo LTSpice users group that might be relevant, <https://groups.yahoo.com/neo/groups/LTspice/conversations/topics/101425> "Hello! I think I found an error in the model 74HC74 in 74HC_v.lib. When I ground D, CLK, PRE und CLR then Q is 0V and /Q is VCC but both Q and /Q should be VCC see function table page 4 http://assets.nexperia.com/documents/data-sheet/74HC_HCT74.pdf Please can someone verify this error and maybe someone can correct the LIB. I'm not qualified to correct it. Thanks for your help!!!!! Best Regards Harald" Looks like a corrected model may have been posted in the thread but it doesn't look like the model file I downloaded has been updated, nothing in there about the 'HC74 being revised after the date of the above thread (2017) "* 74hc.lib * * 74HCxxx Model libraray for LTSPICE from www.linear.com/software * * * Revision 0.55 08/20/2003 * Revision 0.56 08/21/2003 * Revision 0.57 02/04/2005 * Revision 0.58 03/28/2005 * Revision 0.59 03/29/2005 * Revision 0.60 07/09/2006 74HC191 added * Revision 0.61 10/16/2006 74HC4538 added * Revision 0.62 10/23/2009 74HC373 typo corrected * Revision 0.63 11/13/2009 74HC533 added * Revision 0.64 05/02/2010 74HC40103 added * Revision 0.65 30/05/2010 74HC244 added * Revision 0.66 01/30/2012 enabled B(VCC) in input/output driver models * Revision 0.67 10/04/2013 74HC_IN_0: V=LIMIT(0,V(in) -> V=LIMIT(0,V(in,VGND) * Revision 0.68 09/30/2014 corrected a typo HCT to HC in 74HC244 * Revision 0.69 02/01/2019 74HC05 added *
