On 2019-08-03, John Larkin <jjlarkin@highlandtechnology.com> wrote:
> On Sat, 3 Aug 2019 21:28:55 +0300, Tauno Voipio
><tauno.voipio@notused.fi.invalid> wrote:
>
>>On 3.8.19 19:08, bitrex wrote:
>>> On 8/3/19 12:06 PM, bitrex wrote:
>>>> IRL I don't think there's anything this configuration of the 'HC74
>>>> could do but oscillate; with an RC network from not-Q to not-CLR and
>>>> D, CLK, and not-PRE grounded.
>>>>
>>>> But with these models from the Yahoo LTSpice users group the LTSPice
>>>> time domain looks like it manages to find some other metastable state
>>>> and sits there spinning its wheels.
>>>>
>>>> Can anyone suggest some ICs that could bust it out and get it to
>>>> square-wave in the sim? Thanks
>>>>
>>>> <https://imgur.com/a/Idv4LSs>
>>>
>>> plz use this link instead
>>>
>>> <https://imgur.com/a/ochGSav>
>>
>>Your circuit is simply wrong: there is a stable state
>>with both Q- and CLR- high.
>
>
> But \preset is grounded.
>
>
>>
>>The classic oscillator (though bad) is to use a Schmitt
>>with integrating feedback.
>
> It's an off-label use, but most flops will act as a net inverter in
> that circuit. Spice may well not model that mode correctly. But the
> voltage gain is typically low so the whole thing might stabilize near
> Vcc/2.
On Sunday, August 4, 2019 at 8:20:09 PM UTC-4, legg wrote:
> On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote:
>
> >IRL I don't think there's anything this configuration of the 'HC74 could
> >do but oscillate; with an RC network from not-Q to not-CLR and D, CLK,
> >and not-PRE grounded.
> >
> >But with these models from the Yahoo LTSpice users group the LTSPice
> >time domain looks like it manages to find some other metastable state
> >and sits there spinning its wheels.
> >
> >Can anyone suggest some ICs that could bust it out and get it to
> >square-wave in the sim? Thanks
> >
> ><https://imgur.com/a/Idv4LSs>
>
> This recently posted to the Previously-mentioned group:
>
> "In the course of writing my 74LVC1G library I discovered that my
> first attempt at the '74 D flip-flop wasn't quite right: the truth
> table was correct except for when Set and Reset were both low. The
> datasheet states that Q and Qbar should both be high, but Q was in
> fact low.
>
> I checked just the A device Dflop and found that the behaviour of
> Preset and Clear is complex and incompatible with *74 devices.
> Therefore, any 74xx series D flip-flop model that just relies
> internally on the A device Dflop will likely be incorrect. I checked
> Helmut's 74HC and 74HCT libraries and the '74 devices were incorrect.
>
> I'm surprised that after all these years, nobody has spotted this
> subtle error with these libraries!
>
> I haven't checked whether there are other device models in various
> libraries with asynchronous Set and Reset that also have this problem
> feature.
>
> The truth table of the A device Dflop depends on the order that Preset
> and Clear are set. If Preset is set first and remains high and Clear
> is set later, Preset overrides Clear and Q remains high and Qbar
> remains low. If Clear is set first, then Q remains low and Qbar
> remains high. If both are set simultaneously, then Q and Qbar are
> latched in the states they were before before Preset and Clear were
> set.
>
> If both Preset and Clear are set from t=0 (initialised), Q always
> remains low and Qbar remains high.
>
> I have since found that
> http://ltwiki.org/index.php?title=Undocumented_LTspice#A-Devices
> states that with the Dflop and SRflop, Clear has precedence over
> Preset, but that's not the whole story, as that only seems to apply at
> initialisation. It is not known whether the observed behaviour is
> wholly intended. I would guess that these A devices are extensively
> used within the distributed LTspice libraries...
>
> To correct the 74HC74 and 74HCT74 library model static truth tables
> requires that the A device Dflop Preset and Q are OR'd and Clear and
> Qbar are OR'd for the respective outputs, and the timing adjusted.
Clearly this is not an easy issue to fully grasp. The last bit of this explanation is not correct I think. Rather than ORing the signals listed, they should be NORed or low true ANDed (same thing, different ways of saying it). From the earlier description of how the models currently work, I'm not sure this would properly account for the internal state of the FF however.
--
Rick C.
--- Get 1,000 miles of free Supercharging
--- Tesla referral code - https://ts.la/richard11209
Reply by legg●August 4, 20192019-08-04
On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote:
>IRL I don't think there's anything this configuration of the 'HC74 could
>do but oscillate; with an RC network from not-Q to not-CLR and D, CLK,
>and not-PRE grounded.
>
>But with these models from the Yahoo LTSpice users group the LTSPice
>time domain looks like it manages to find some other metastable state
>and sits there spinning its wheels.
>
>Can anyone suggest some ICs that could bust it out and get it to
>square-wave in the sim? Thanks
>
><https://imgur.com/a/Idv4LSs>
This recently posted to the Previously-mentioned group:
"In the course of writing my 74LVC1G library I discovered that my
first attempt at the '74 D flip-flop wasn't quite right: the truth
table was correct except for when Set and Reset were both low. The
datasheet states that Q and Qbar should both be high, but Q was in
fact low.
I checked just the A device Dflop and found that the behaviour of
Preset and Clear is complex and incompatible with *74 devices.
Therefore, any 74xx series D flip-flop model that just relies
internally on the A device Dflop will likely be incorrect. I checked
Helmut's 74HC and 74HCT libraries and the '74 devices were incorrect.
I'm surprised that after all these years, nobody has spotted this
subtle error with these libraries!
I haven't checked whether there are other device models in various
libraries with asynchronous Set and Reset that also have this problem
feature.
The truth table of the A device Dflop depends on the order that Preset
and Clear are set. If Preset is set first and remains high and Clear
is set later, Preset overrides Clear and Q remains high and Qbar
remains low. If Clear is set first, then Q remains low and Qbar
remains high. If both are set simultaneously, then Q and Qbar are
latched in the states they were before before Preset and Clear were
set.
If both Preset and Clear are set from t=0 (initialised), Q always
remains low and Qbar remains high.
I have since found that
http://ltwiki.org/index.php?title=Undocumented_LTspice#A-Devices
states that with the Dflop and SRflop, Clear has precedence over
Preset, but that's not the whole story, as that only seems to apply at
initialisation. It is not known whether the observed behaviour is
wholly intended. I would guess that these A devices are extensively
used within the distributed LTspice libraries...
To correct the 74HC74 and 74HCT74 library model static truth tables
requires that the A device Dflop Preset and Q are OR'd and Clear and
Qbar are OR'd for the respective outputs, and the timing adjusted.
Regards,
Tony Casey"
RL
Reply by Robert Baer●August 4, 20192019-08-04
bitrex wrote:
> IRL I don't think there's anything this configuration of the 'HC74 could
> do but oscillate; with an RC network from not-Q to not-CLR and D, CLK,
> and not-PRE grounded.
>
> But with these models from the Yahoo LTSpice users group the LTSPice
> time domain looks like it manages to find some other metastable state
> and sits there spinning its wheels.
>
> Can anyone suggest some ICs that could bust it out and get it to
> square-wave in the sim? Thanks
>
> <https://imgur.com/a/Idv4LSs>
Zoinks! You've taken a wrong turn.
Let's split up, gang. If you're looking for an image, it's probably been
deleted or may not have existed at all.
If you are looking for groovy images, visit our gallery!
Reply by bitrex●August 4, 20192019-08-04
On 8/4/19 2:25 AM, Tom Gardner wrote:
> On 04/08/19 04:05, Bill Sloman wrote:
>> On Sunday, August 4, 2019 at 5:12:06 AM UTC+10, John Larkin wrote:
>>> On Sat, 3 Aug 2019 21:31:15 +0300, Tauno Voipio
>>> <tauno.voipio@notused.fi.invalid> wrote:
>>>
>>>> On 3.8.19 19:58, bitrex wrote:
>>>>> On 8/3/19 12:24 PM, John Larkin wrote:
>>>>>> On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote:
>>>>>>
>>>>>>> IRL I don't think there's anything this configuration of the 'HC74
>>>>>>> could do but oscillate; with an RC network from not-Q to not-CLR
>>>>>>> and D, CLK, and not-PRE grounded.
>>>>>>>
>>>>>>> But with these models from the Yahoo LTSpice users group the
>>>>>>> LTSPice time domain looks like it manages to find some other
>>>>>>> metastable state and sits there spinning its wheels.
>>>>>>>
>>>>>>> Can anyone suggest some ICs that could bust it out and get it to
>>>>>>> square-wave in the sim? Thanks
>>>>>>>
>>>>>>> <https://imgur.com/a/Idv4LSs>
>>>>>>
>>>>>> The voltage gain from \Q to \CLR is low, and there's no schmitt
>>>>>> action, so you can get a stable negative feedback loop. It would
>>>>>> likely oscillate at a higher frequency, where the logic prop delay
>>>>>> becomes important.
>>>>>>
>>>>>> Why not use a schmitt inverter? This circuit could be rescued, but
>>>>>> it would take more parts.
>>>>>>
>>>>>> Maybe "ground" C1 to Q?
>>>>>>
>>>>>> But I wouldn't trust the Spice models for what is basically analog
>>>>>> behavior.
>>>>>>
>>>>>>
>>>>>
>>>>> Check this out someone actually got a patent for this back in 1990
>>>>> (the crystal probably helps a lot):
>>>>>
>>>>> <https://imgur.com/a/YryI2p6>
>>>>
>>>> An idea can be patented even if it does not work.
>>>
>>> For some people, getting patents is a kind of addiction.
>>
>> Places like IBM, Bell Labs and EMI Central Research had teams of patent
>> lawyers, and a culture where the staff were encourage to put in patent
>> queries.
>
> Rule of thumb: if a company decides to put a /new/
> emphasis on getting patents, then someone has
> /started/ thinking of selling the company.
>
>
>> One of my colleagues at EMI held the record for patent queries filed
>> in any
>> one year. None of them went through. One of the two I got resulted
>> from what
>> had struck me as a perfectly obvious point, but after I'd had to
>> explain it
>> to some half-dozen people I decided that it probably wasn't obvious to
>> those
>> skilled in the art. The patent examiners agreed.
>
> Yup; that was my experience too.
>
>
> On Sunday, August 4, 2019 at 5:12:06 AM UTC+10, John Larkin wrote:
>> On Sat, 3 Aug 2019 21:31:15 +0300, Tauno Voipio
>> <tauno.voipio@notused.fi.invalid> wrote:
>>
>>> On 3.8.19 19:58, bitrex wrote:
>>>> On 8/3/19 12:24 PM, John Larkin wrote:
>>>>> On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote:
>>>>>
>>>>>> IRL I don't think there's anything this configuration of the 'HC74
>>>>>> could do but oscillate; with an RC network from not-Q to not-CLR
>>>>>> and D, CLK, and not-PRE grounded.
>>>>>>
>>>>>> But with these models from the Yahoo LTSpice users group the
>>>>>> LTSPice time domain looks like it manages to find some other
>>>>>> metastable state and sits there spinning its wheels.
>>>>>>
>>>>>> Can anyone suggest some ICs that could bust it out and get it to
>>>>>> square-wave in the sim? Thanks
>>>>>>
>>>>>> <https://imgur.com/a/Idv4LSs>
>>>>>
>>>>> The voltage gain from \Q to \CLR is low, and there's no schmitt
>>>>> action, so you can get a stable negative feedback loop. It would
>>>>> likely oscillate at a higher frequency, where the logic prop delay
>>>>> becomes important.
>>>>>
>>>>> Why not use a schmitt inverter? This circuit could be rescued, but
>>>>> it would take more parts.
>>>>>
>>>>> Maybe "ground" C1 to Q?
>>>>>
>>>>> But I wouldn't trust the Spice models for what is basically analog
>>>>> behavior.
>>>>>
>>>>>
>>>>
>>>> Check this out someone actually got a patent for this back in 1990
>>>> (the crystal probably helps a lot):
>>>>
>>>> <https://imgur.com/a/YryI2p6>
>>>
>>> An idea can be patented even if it does not work.
>>
>> For some people, getting patents is a kind of addiction.
>
> Places like IBM, Bell Labs and EMI Central Research had teams of patent
> lawyers, and a culture where the staff were encourage to put in patent
> queries.
Rule of thumb: if a company decides to put a /new/
emphasis on getting patents, then someone has
/started/ thinking of selling the company.
> One of my colleagues at EMI held the record for patent queries filed in any
> one year. None of them went through. One of the two I got resulted from what
> had struck me as a perfectly obvious point, but after I'd had to explain it
> to some half-dozen people I decided that it probably wasn't obvious to those
> skilled in the art. The patent examiners agreed.
Yup; that was my experience too.
Reply by Rick C●August 4, 20192019-08-04
On Saturday, August 3, 2019 at 11:12:45 PM UTC-4, whit3rd wrote:
> On Saturday, August 3, 2019 at 9:06:10 AM UTC-7, bitrex wrote:
> > IRL I don't think there's anything this configuration of the 'HC74 could
> > do but oscillate
>
> The innards of a master/slave D flipflop are huge;
By grounding the clock, data input and PRE- input, the "huge" innards are all disabled other than a NAND gate and an output buffer. CLR- to Q- looks like a single inverter.
> a simpler
> oscillator (ring oscillator) just takes an odd number of inverters,
> so in CMOS it starts at six transistors, maybe even two, no external
> capacitors/resistors required.
>
> One generally uses other things, to minimize side-effects
> (power supply current spikes) , and timing components accurate
> over temperature, aging, device variation.
Crystals are good, oscillators are better.
--
Rick C.
++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209
Reply by whit3rd●August 4, 20192019-08-04
On Saturday, August 3, 2019 at 9:06:10 AM UTC-7, bitrex wrote:
> IRL I don't think there's anything this configuration of the 'HC74 could
> do but oscillate
The innards of a master/slave D flipflop are huge; a simpler
oscillator (ring oscillator) just takes an odd number of inverters,
so in CMOS it starts at six transistors, maybe even two, no external
capacitors/resistors required.
One generally uses other things, to minimize side-effects
(power supply current spikes) , and timing components accurate
over temperature, aging, device variation.
Reply by Bill Sloman●August 4, 20192019-08-04
On Sunday, August 4, 2019 at 5:12:06 AM UTC+10, John Larkin wrote:
> On Sat, 3 Aug 2019 21:31:15 +0300, Tauno Voipio
> <tauno.voipio@notused.fi.invalid> wrote:
>
> >On 3.8.19 19:58, bitrex wrote:
> >> On 8/3/19 12:24 PM, John Larkin wrote:
> >>> On Sat, 3 Aug 2019 12:06:05 -0400, bitrex <user@example.net> wrote:
> >>>
> >>>> IRL I don't think there's anything this configuration of the 'HC74 could
> >>>> do but oscillate; with an RC network from not-Q to not-CLR and D, CLK,
> >>>> and not-PRE grounded.
> >>>>
> >>>> But with these models from the Yahoo LTSpice users group the LTSPice
> >>>> time domain looks like it manages to find some other metastable state
> >>>> and sits there spinning its wheels.
> >>>>
> >>>> Can anyone suggest some ICs that could bust it out and get it to
> >>>> square-wave in the sim? Thanks
> >>>>
> >>>> <https://imgur.com/a/Idv4LSs>
> >>>
> >>> The voltage gain from \Q to \CLR is low, and there's no schmitt
> >>> action, so you can get a stable negative feedback loop. It would
> >>> likely oscillate at a higher frequency, where the logic prop delay
> >>> becomes important.
> >>>
> >>> Why not use a schmitt inverter? This circuit could be rescued, but it
> >>> would take more parts.
> >>>
> >>> Maybe "ground" C1 to Q?
> >>>
> >>> But I wouldn't trust the Spice models for what is basically analog
> >>> behavior.
> >>>
> >>>
> >>
> >> Check this out someone actually got a patent for this back in 1990 (the
> >> crystal probably helps a lot):
> >>
> >> <https://imgur.com/a/YryI2p6>
> >
> >An idea can be patented even if it does not work.
>
> For some people, getting patents is a kind of addiction.
Places like IBM, Bell Labs and EMI Central Research had teams of patent lawyers, and a culture where the staff were encourage to put in patent queries.
One of my colleagues at EMI held the record for patent queries filed in any one year. None of them went through. One of the two I got resulted from what had struck me as a perfectly obvious point, but after I'd had to explain it to some half-dozen people I decided that it probably wasn't obvious to those skilled in the art. The patent examiners agreed.
--
Bill Sloman, Sydney
Reply by bitrex●August 3, 20192019-08-03
On 8/3/19 5:10 PM, bitrex wrote:
>> Small uPs usually have a pretty good internal oscillator.
>>
>>
>
> uP's are so cheap and easy that there's little reason for me to not
> recommend one for most simple projects right off the bat
>
> This is a great tool, it lets you drag and drop little functional blocks
> like "voltage controlled" oscillators, logic gates, functional blocks of
> various types and bang it up to an 8 pin AVR in about 5 minutes:
>
> <https://xod.io/>
There's a niche for low-speed hairball logic-like circuitry, that being
able to "program" a microprocessor visually and end up with a "circuit"
but expressed in auto-generated code, but that is provably glitch-free
and that runs on a general-purpose uP that this tool fills very nicely