On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:>On Mon, 17 Jul 2017 21:10:20 +0100, piglet <erichpwagner@hotmail.com> >wrote: > >[snip] >>> >> >>If the TTL world provides complementary true and true-bar inputs to the >>level shifter then 2/3 of CD4007 can shift to high level very easily: >> >><https://www.dropbox.com/s/gur02pqy5nv1ugo/IMG_20170717_TBLEVSHIFT.jpg?dl=0> >> >>If there are inverters or other CD4007s living in the low rail >>environment they could provide the low-level inversion. > >That is the classic way that level-shifting is done on-chip (with >embellishments that minimize the peak current required at each >transition). > >First thing I tried. The problem is that the N-channel devices are >too 'weak' to overcome the P-channels, thus I went the route of the >added resistors. > >> >>Real shame all the CD4007 p-channels are tied to Vdd - then this >>challenge would be simpler :> >> >>piglet >> > >Only the body ties are to VDD, two of the P-channel devices have free >sources. > >I'd would have loved to have a few 'free' N-channel gates, then my >embellishment tricks could be implemented. > >On custom chip designs I have all those freedoms plus I can size >devices at will ;-) > >(I think it was you, piglet, who commented, "...power from output" for >the first inverter. That's also in my bag of tricks, but also >wouldn't play because the N-channels at three volt gate drive are >'weenies' ;-) > > ...Jim ThompsonWhy not a single grounded-source n-fet, and a pullup resistor on the drain? -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Good Find, CD4007 Spice Model Library....
Started by ●July 15, 2017
Reply by ●July 17, 20172017-07-17
Reply by ●July 17, 20172017-07-17
On Mon, 17 Jul 2017 13:31:18 -0700, John Larkin <jjlarkin@highland_snip_technology.com> wrote:>On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: > >>On Mon, 17 Jul 2017 21:10:20 +0100, piglet <erichpwagner@hotmail.com> >>wrote: >> >>[snip] >>>> >>> >>>If the TTL world provides complementary true and true-bar inputs to the >>>level shifter then 2/3 of CD4007 can shift to high level very easily: >>> >>><https://www.dropbox.com/s/gur02pqy5nv1ugo/IMG_20170717_TBLEVSHIFT.jpg?dl=0> >>> >>>If there are inverters or other CD4007s living in the low rail >>>environment they could provide the low-level inversion. >> >>That is the classic way that level-shifting is done on-chip (with >>embellishments that minimize the peak current required at each >>transition). >> >>First thing I tried. The problem is that the N-channel devices are >>too 'weak' to overcome the P-channels, thus I went the route of the >>added resistors. >> >>> >>>Real shame all the CD4007 p-channels are tied to Vdd - then this >>>challenge would be simpler :> >>> >>>piglet >>> >> >>Only the body ties are to VDD, two of the P-channel devices have free >>sources. >> >>I'd would have loved to have a few 'free' N-channel gates, then my >>embellishment tricks could be implemented. >> >>On custom chip designs I have all those freedoms plus I can size >>devices at will ;-) >> >>(I think it was you, piglet, who commented, "...power from output" for >>the first inverter. That's also in my bag of tricks, but also >>wouldn't play because the N-channels at three volt gate drive are >>'weenies' ;-) >> >> ...Jim Thompson > >Why not a single grounded-source n-fet, and a pullup resistor on the >drain?If your application can tolerate the exponential rising edge, sure, why not. The 'classic' approach in CMOS has quite 'stiff' edges at the output (there _is_ positive feedback, two inverters tied back on themselves). ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I'm looking for work... see my website. Thinking outside the box...producing elegant & economic solutions.
Reply by ●July 17, 20172017-07-17
On Mon, 17 Jul 2017 13:43:52 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:>On Mon, 17 Jul 2017 13:31:18 -0700, John Larkin ><jjlarkin@highland_snip_technology.com> wrote: > >>On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson >><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >> >>>On Mon, 17 Jul 2017 21:10:20 +0100, piglet <erichpwagner@hotmail.com> >>>wrote: >>> >>>[snip] >>>>> >>>> >>>>If the TTL world provides complementary true and true-bar inputs to the >>>>level shifter then 2/3 of CD4007 can shift to high level very easily: >>>> >>>><https://www.dropbox.com/s/gur02pqy5nv1ugo/IMG_20170717_TBLEVSHIFT.jpg?dl=0> >>>> >>>>If there are inverters or other CD4007s living in the low rail >>>>environment they could provide the low-level inversion. >>> >>>That is the classic way that level-shifting is done on-chip (with >>>embellishments that minimize the peak current required at each >>>transition). >>> >>>First thing I tried. The problem is that the N-channel devices are >>>too 'weak' to overcome the P-channels, thus I went the route of the >>>added resistors. >>> >>>> >>>>Real shame all the CD4007 p-channels are tied to Vdd - then this >>>>challenge would be simpler :> >>>> >>>>piglet >>>> >>> >>>Only the body ties are to VDD, two of the P-channel devices have free >>>sources. >>> >>>I'd would have loved to have a few 'free' N-channel gates, then my >>>embellishment tricks could be implemented. >>> >>>On custom chip designs I have all those freedoms plus I can size >>>devices at will ;-) >>> >>>(I think it was you, piglet, who commented, "...power from output" for >>>the first inverter. That's also in my bag of tricks, but also >>>wouldn't play because the N-channels at three volt gate drive are >>>'weenies' ;-) >>> >>> ...Jim Thompson >> >>Why not a single grounded-source n-fet, and a pullup resistor on the >>drain? > >If your application can tolerate the exponential rising edge, sure, >why not.After the nfet input stage, there are two leftover buffers in the 4007. It's easy to make a Schmitt, too. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●July 17, 20172017-07-17
On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:>On Mon, 17 Jul 2017 21:10:20 +0100, piglet <erichpwagner@hotmail.com> >wrote: > >[snip] >>> >> >>If the TTL world provides complementary true and true-bar inputs to the >>level shifter then 2/3 of CD4007 can shift to high level very easily: >> >><https://www.dropbox.com/s/gur02pqy5nv1ugo/IMG_20170717_TBLEVSHIFT.jpg?dl=0> >> >>If there are inverters or other CD4007s living in the low rail >>environment they could provide the low-level inversion. > >That is the classic way that level-shifting is done on-chip (with >embellishments that minimize the peak current required at each >transition). >[snip] One embellishment method... <http://www.analog-innovations.com/SED/LogicTranslator_Classic_2017-07-17.png> Done by ignoring the pin-out restrictions of the CD4007 but no optimizing size scaling. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I'm looking for work... see my website. Thinking outside the box...producing elegant & economic solutions.
Reply by ●July 18, 20172017-07-18
On Monday, July 17, 2017 at 1:10:30 PM UTC-7, piglet wrote:> On 17/07/2017 09:18, Piglet wrote:> Real shame all the CD4007 p-channels are tied to Vdd - then this > challenge would be simpler :>That's an example of Leaver's Law. Putting many transistors into an integrated circuit is a big win. But, everything it does FOR you, it also does TO you. SOS (silicon-on-sapphire) and other oxide isolation gets around this, but adds cost and complication.
Reply by ●July 18, 20172017-07-18
>SOS (silicon-on-sapphire) and other oxide isolation gets >around this, butadds cost and complication. SOS was an '80s enthusiasm, mostly of HP's, iirc. More modern S0I is a whole lot cheaper--a bonded or SIMOX wafer isn't that much more expensive than a bulk wafer. There are still a few folks using SoS, but it's far from mainstream. Cheers Phil Hobbs
Reply by ●July 18, 20172017-07-18
On 17/07/2017 22:59, Jim Thompson wrote:> On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson > > One embellishment method... > > <http://www.analog-innovations.com/SED/LogicTranslator_Classic_2017-07-17.png> > > Done by ignoring the pin-out restrictions of the CD4007 but no > optimizing size scaling. > > ...Jim Thompson >Thanks Jim. That embellishment is too subtle for me: MN1 and MN2 have their gates at +15V and their substrates at 0V so both will be fully enhanced and basically just two pieces of wire. Is that a monolithic way of making a low resistance? piglet
Reply by ●July 18, 20172017-07-18
On 17/07/2017 21:31, John Larkin wrote:> > Why not a single grounded-source n-fet, and a pullup resistor on the > drain? > >Yeah, but that is a real-world way of doing things :> The more interesting problem was to make it true to the ethos of CMOS and have no current draw for either logical state. piglet
Reply by ●July 18, 20172017-07-18
On Tue, 18 Jul 2017 09:51:05 +0100, piglet <erichpwagner@hotmail.com> wrote:>On 17/07/2017 21:31, John Larkin wrote: >> >> Why not a single grounded-source n-fet, and a pullup resistor on the >> drain? >> >> > >Yeah, but that is a real-world way of doing things :> > >The more interesting problem was to make it true to the ethos of CMOS >and have no current draw for either logical state. > >piglet > > >Don't cheat by requiring complementary TTL inputs! -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●July 18, 20172017-07-18
On Tue, 18 Jul 2017 09:48:18 +0100, piglet <erichpwagner@hotmail.com> wrote:>On 17/07/2017 22:59, Jim Thompson wrote: >> On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson >> >> One embellishment method... >> >> <http://www.analog-innovations.com/SED/LogicTranslator_Classic_2017-07-17.png> >> >> Done by ignoring the pin-out restrictions of the CD4007 but no >> optimizing size scaling. >> >> ...Jim Thompson >> > >Thanks Jim. That embellishment is too subtle for me: MN1 and MN2 have >their gates at +15V and their substrates at 0V so both will be fully >enhanced and basically just two pieces of wire. Is that a monolithic way >of making a low resistance? > >pigletAt the low end of the output swing they're low resistances, at the high end of the output swing they're high resistances. Thus the low current required to 'upset' the latch. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I'm looking for work... see my website. Thinking outside the box...producing elegant & economic solutions.
