Reply by Jim Thompson August 7, 20172017-08-07
On Sat, 15 Jul 2017 11:54:10 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

>On Sat, 15 Jul 2017 18:36:23 -0000 (UTC), Cursitor Doom ><curd@notformail.com> wrote: > >>On Sat, 15 Jul 2017 11:31:33 -0700, Jim Thompson wrote: >> >>> Good Find, CD4007 Spice Model Library, at Rochester Institute of >>> Technology, actual measurements by Professor Lynn Fuller... >>> >>> <https://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf> >>> >>> >>> ...Jim Thompson >> >>You must have an *exceedingly* copious library of spice models by now, >>Jim? > >119 Manufacturers/Foundries, some, like X-Fab, with 12 different >processes. > >Plus all the behavioral models I've rolled myself, probably also in >the hundreds ;-) > > ...Jim Thompson
Just added foundry #120... Vanguard International Semiconductor Corporation ;-) ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I'm looking for work... see my website. Thinking outside the box...producing elegant & economic solutions.
Reply by Jim Thompson July 19, 20172017-07-19
On Wed, 19 Jul 2017 19:46:58 +0100, "Kevin Aylward"
<kevinRemovAT@kevinaylward.co.uk> wrote:

>"Jim Thompson" wrote in message >news:jdinmc5tvkl0kbcv9em0q2c2ta3lv6v0tf@4ax.com... > >On Sun, 16 Jul 2017 20:09:11 -0000 (UTC), Cursitor Doom ><curd@notformail.com> wrote: > >>On Sun, 16 Jul 2017 09:26:30 -0700, Jim Thompson wrote: >> >>> Then it dawned. His "compiling" is going in and replacing every >>> recognizable "standard" part in the netlist with idealized equivalents. >>> Thus the speed "improvement". >>s >>>Oh boy. Well, I guess Mike in his own defence would simply say he'd >>>refund you every single cent you paid for it. ;-) >>>I hope Mike's not reading this, btw, as from the exchanges I've had with >>>him from time to time in the past, he doesn't like this kind of thing >>>being openly discussed in a public forum (not surprisingly). > >>Having met him face-to-face over lunch at one of his seminars a few >>years back, I'd rank Mike Engelhardt as a first class narcissistic >>pompous ass... and I'm being kind >:-} > >I have to agree. If you recall around 2,000 he posted to this PUBLIC NG that >I had applied to LT, and trashed my resume in PUBLIC, and hence told the >world that I had applied for a job whilst employed at TI. I made an >official complaint to LT HR that Mike had breached a clear confidentiality. >17 years on, I have yet to receive any apology from LT. This also says >something about LT. > >Anyway, at least I now have a superior to Mikes LTSpice VDMOS. To wit, >non-linear cgs, cgd, quasi-sat and subthreshold... > >http://www.anasoft.co.uk/MOS1Model.htm :-) > >-- Kevin Aylward >http://www.anasoft.co.uk - SuperSpice >http://www.kevinaylward.co.uk/ee/index.html
Nice! ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I'm looking for work... see my website. Thinking outside the box...producing elegant & economic solutions.
Reply by Kevin Aylward July 19, 20172017-07-19
"Jim Thompson"  wrote in message 
news:jdinmc5tvkl0kbcv9em0q2c2ta3lv6v0tf@4ax.com...

On Sun, 16 Jul 2017 20:09:11 -0000 (UTC), Cursitor Doom
<curd@notformail.com> wrote:

>On Sun, 16 Jul 2017 09:26:30 -0700, Jim Thompson wrote: > >> Then it dawned. His "compiling" is going in and replacing every >> recognizable "standard" part in the netlist with idealized equivalents. >> Thus the speed "improvement". >s >>Oh boy. Well, I guess Mike in his own defence would simply say he'd >>refund you every single cent you paid for it. ;-) >>I hope Mike's not reading this, btw, as from the exchanges I've had with >>him from time to time in the past, he doesn't like this kind of thing >>being openly discussed in a public forum (not surprisingly).
>Having met him face-to-face over lunch at one of his seminars a few >years back, I'd rank Mike Engelhardt as a first class narcissistic >pompous ass... and I'm being kind >:-}
I have to agree. If you recall around 2,000 he posted to this PUBLIC NG that I had applied to LT, and trashed my resume in PUBLIC, and hence told the world that I had applied for a job whilst employed at TI. I made an official complaint to LT HR that Mike had breached a clear confidentiality. 17 years on, I have yet to receive any apology from LT. This also says something about LT. Anyway, at least I now have a superior to Mikes LTSpice VDMOS. To wit, non-linear cgs, cgd, quasi-sat and subthreshold... http://www.anasoft.co.uk/MOS1Model.htm :-) -- Kevin Aylward http://www.anasoft.co.uk - SuperSpice http://www.kevinaylward.co.uk/ee/index.html
Reply by Jim Thompson July 18, 20172017-07-18
On Tue, 18 Jul 2017 22:20:37 +0100, piglet <erichpwagner@hotmail.com>
wrote:

>On 18/07/2017 16:24, Jim Thompson wrote: >> On Tue, 18 Jul 2017 09:48:18 +0100, piglet <erichpwagner@hotmail.com> >> wrote: >> >>> On 17/07/2017 22:59, Jim Thompson wrote: >>>> On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson >>>> >>>> One embellishment method... >>>> >>>> <http://www.analog-innovations.com/SED/LogicTranslator_Classic_2017-07-17.png> >>>> >>>> Done by ignoring the pin-out restrictions of the CD4007 but no >>>> optimizing size scaling. >>>> >>>> ...Jim Thompson >>>> >>> >>> Thanks Jim. That embellishment is too subtle for me: MN1 and MN2 have >>> their gates at +15V and their substrates at 0V so both will be fully >>> enhanced and basically just two pieces of wire. Is that a monolithic way >>> of making a low resistance? >>> >>> piglet >> >> At the low end of the output swing they're low resistances, at the >> high end of the output swing they're high resistances. Thus the low >> current required to 'upset' the latch. >> >> ...Jim Thompson >> > >Thanks. I see now. > >piglet
There are far snazzier ways, but can't be done with CD4007 devices... plus the device count would offend Larkin's sensibilities ;-) (Did you note that low power even at a 10MHz rate?) ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I'm looking for work... see my website. Thinking outside the box...producing elegant & economic solutions.
Reply by piglet July 18, 20172017-07-18
On 18/07/2017 16:24, Jim Thompson wrote:
> On Tue, 18 Jul 2017 09:48:18 +0100, piglet <erichpwagner@hotmail.com> > wrote: > >> On 17/07/2017 22:59, Jim Thompson wrote: >>> On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson >>> >>> One embellishment method... >>> >>> <http://www.analog-innovations.com/SED/LogicTranslator_Classic_2017-07-17.png> >>> >>> Done by ignoring the pin-out restrictions of the CD4007 but no >>> optimizing size scaling. >>> >>> ...Jim Thompson >>> >> >> Thanks Jim. That embellishment is too subtle for me: MN1 and MN2 have >> their gates at +15V and their substrates at 0V so both will be fully >> enhanced and basically just two pieces of wire. Is that a monolithic way >> of making a low resistance? >> >> piglet > > At the low end of the output swing they're low resistances, at the > high end of the output swing they're high resistances. Thus the low > current required to 'upset' the latch. > > ...Jim Thompson >
Thanks. I see now. piglet
Reply by Jim Thompson July 18, 20172017-07-18
On Tue, 18 Jul 2017 09:48:18 +0100, piglet <erichpwagner@hotmail.com>
wrote:

>On 17/07/2017 22:59, Jim Thompson wrote: >> On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson >> >> One embellishment method... >> >> <http://www.analog-innovations.com/SED/LogicTranslator_Classic_2017-07-17.png> >> >> Done by ignoring the pin-out restrictions of the CD4007 but no >> optimizing size scaling. >> >> ...Jim Thompson >> > >Thanks Jim. That embellishment is too subtle for me: MN1 and MN2 have >their gates at +15V and their substrates at 0V so both will be fully >enhanced and basically just two pieces of wire. Is that a monolithic way >of making a low resistance? > >piglet
At the low end of the output swing they're low resistances, at the high end of the output swing they're high resistances. Thus the low current required to 'upset' the latch. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I'm looking for work... see my website. Thinking outside the box...producing elegant & economic solutions.
Reply by John Larkin July 18, 20172017-07-18
On Tue, 18 Jul 2017 09:51:05 +0100, piglet <erichpwagner@hotmail.com>
wrote:

>On 17/07/2017 21:31, John Larkin wrote: >> >> Why not a single grounded-source n-fet, and a pullup resistor on the >> drain? >> >> > >Yeah, but that is a real-world way of doing things :> > >The more interesting problem was to make it true to the ethos of CMOS >and have no current draw for either logical state. > >piglet > > >
Don't cheat by requiring complementary TTL inputs! -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by piglet July 18, 20172017-07-18
On 17/07/2017 21:31, John Larkin wrote:
> > Why not a single grounded-source n-fet, and a pullup resistor on the > drain? > >
Yeah, but that is a real-world way of doing things :> The more interesting problem was to make it true to the ethos of CMOS and have no current draw for either logical state. piglet
Reply by piglet July 18, 20172017-07-18
On 17/07/2017 22:59, Jim Thompson wrote:
> On Mon, 17 Jul 2017 13:22:48 -0700, Jim Thompson > > One embellishment method... > > <http://www.analog-innovations.com/SED/LogicTranslator_Classic_2017-07-17.png> > > Done by ignoring the pin-out restrictions of the CD4007 but no > optimizing size scaling. > > ...Jim Thompson >
Thanks Jim. That embellishment is too subtle for me: MN1 and MN2 have their gates at +15V and their substrates at 0V so both will be fully enhanced and basically just two pieces of wire. Is that a monolithic way of making a low resistance? piglet
Reply by July 18, 20172017-07-18
>SOS (silicon-on-sapphire) and other oxide isolation gets >around this, but
adds cost and complication. SOS was an '80s enthusiasm, mostly of HP's, iirc. More modern S0I is a whole lot cheaper--a bonded or SIMOX wafer isn't that much more expensive than a bulk wafer. There are still a few folks using SoS, but it's far from mainstream. Cheers Phil Hobbs