On Saturday, June 3, 2017 at 12:58:42 AM UTC+2, k...@notreal.com wrote:> On Fri, 2 Jun 2017 15:43:27 -0700 (PDT), klaus.kragelund@gmail.com > wrote: > > >On Friday, 2 June 2017 23:35:33 UTC+2, k...@notreal.com wrote: > >> On Fri, 2 Jun 2017 09:56:02 -0700 (PDT), klaus.kragelund@gmail.com > >> wrote: > >> > >> >On Friday, 2 June 2017 18:47:09 UTC+2, k...@notreal.com wrote: > >> >> On Fri, 2 Jun 2017 01:19:05 -0700 (PDT), klaus.kragelund@gmail.com > >> >> wrote: > >> >> > >> >> >On Friday, 2 June 2017 02:24:30 UTC+2, k...@notreal.com wrote: > >> >> >> On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: > >> >> >> > >> >> >> >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund > >> >> >> ><klauskvik@hotmail.com> wrote: > >> >> >> > > >> >> >> >>Datasheet: > >> >> >> >> > >> >> >> >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > >> >> >> >> > >> >> >> >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > >> >> >> > > >> >> >> >Where? > >> >> >> >> > >> >> >> >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > >> >> >> > > >> >> >> >That's certainly not true. If it were, there wouldn't be mixed > >> >> >> >technology chips. > >> >> >> > > >> >> >> >>Operation from SRAM draws less current > >> >> >> > > >> >> >> >Not buying it, at least reads (operation). Note that both are zero > >> >> >> >wait-states so no advantage there. > >> >> >> > >> >> >> BTW, the datasheet claims 3MB "on-chip" flash? That's not what we > >> >> >> were discussing (and *really* hard to believe). I shoulda checked the > >> >> >> date on the datasheet (4/1? ;). > >> >> > > >> >> >Check the reverse engineering document. They have serial flash, so it is up to 3MB > >> >> > >> >> You've said so many things contrary to the datasheet and yourself, and > >> >> it's equally opaque, that I have no idea what you're talking about > >> >> anymore. > >> > > >> >Name them, I do not think I have stated anything misleading? > >> > >> Is the flash on-chip or not? > > > >That was shown in the original post, this link: > > > >https://www.google.com/url?q=https%3A%2F%2Fzeptobars.com%2Fen%2Fread%2FGD32F103CBT6-mcm-serial-flash-Giga-Devices&sa=D&sntz=1&usg=AFQjCNGxP01l8TwSoAUL0fUySa4gGXhUYw > > > >2 dies. AFAICT the flash is loaded to SRAM during startup (50ms startup), and then excutions runs in SRAM, hence the 0 wait state > > The datasheet (and you) claimed that it was a single chip.[snip] NO. Did you read the first post at all? - the thread is about reliability of a TWO die solution...
Reliability of microcontroller silicon die glue on top of another die
Started by ●May 31, 2017
Reply by ●June 2, 20172017-06-02
Reply by ●June 2, 20172017-06-02
On Fri, 2 Jun 2017 16:27:01 -0700 (PDT), Klaus Kragelund <klauskvik@hotmail.com> wrote:>On Saturday, June 3, 2017 at 12:58:42 AM UTC+2, k...@notreal.com wrote: >> On Fri, 2 Jun 2017 15:43:27 -0700 (PDT), klaus.kragelund@gmail.com >> wrote: >> >> >On Friday, 2 June 2017 23:35:33 UTC+2, k...@notreal.com wrote: >> >> On Fri, 2 Jun 2017 09:56:02 -0700 (PDT), klaus.kragelund@gmail.com >> >> wrote: >> >> >> >> >On Friday, 2 June 2017 18:47:09 UTC+2, k...@notreal.com wrote: >> >> >> On Fri, 2 Jun 2017 01:19:05 -0700 (PDT), klaus.kragelund@gmail.com >> >> >> wrote: >> >> >> >> >> >> >On Friday, 2 June 2017 02:24:30 UTC+2, k...@notreal.com wrote: >> >> >> >> On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: >> >> >> >> >> >> >> >> >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund >> >> >> >> ><klauskvik@hotmail.com> wrote: >> >> >> >> > >> >> >> >> >>Datasheet: >> >> >> >> >> >> >> >> >> >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf >> >> >> >> >> >> >> >> >> >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 >> >> >> >> > >> >> >> >> >Where? >> >> >> >> >> >> >> >> >> >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies >> >> >> >> > >> >> >> >> >That's certainly not true. If it were, there wouldn't be mixed >> >> >> >> >technology chips. >> >> >> >> > >> >> >> >> >>Operation from SRAM draws less current >> >> >> >> > >> >> >> >> >Not buying it, at least reads (operation). Note that both are zero >> >> >> >> >wait-states so no advantage there. >> >> >> >> >> >> >> >> BTW, the datasheet claims 3MB "on-chip" flash? That's not what we >> >> >> >> were discussing (and *really* hard to believe). I shoulda checked the >> >> >> >> date on the datasheet (4/1? ;). >> >> >> > >> >> >> >Check the reverse engineering document. They have serial flash, so it is up to 3MB >> >> >> >> >> >> You've said so many things contrary to the datasheet and yourself, and >> >> >> it's equally opaque, that I have no idea what you're talking about >> >> >> anymore. >> >> > >> >> >Name them, I do not think I have stated anything misleading? >> >> >> >> Is the flash on-chip or not? >> > >> >That was shown in the original post, this link: >> > >> >https://www.google.com/url?q=https%3A%2F%2Fzeptobars.com%2Fen%2Fread%2FGD32F103CBT6-mcm-serial-flash-Giga-Devices&sa=D&sntz=1&usg=AFQjCNGxP01l8TwSoAUL0fUySa4gGXhUYw >> > >> >2 dies. AFAICT the flash is loaded to SRAM during startup (50ms startup), and then excutions runs in SRAM, hence the 0 wait state >> >> The datasheet (and you) claimed that it was a single chip. > >[snip] > >NO. Did you read the first post at all? - the thread is about reliability of a TWO die solution...But then you kept saying "on chip", as does the datasheet. It's not. It's a kludge.
Reply by ●June 3, 20172017-06-03
On Friday, June 2, 2017 at 4:31:59 PM UTC-7, k...@notreal.com wrote:> On Fri, 2 Jun 2017 16:27:01 -0700 (PDT), Klaus Kragelund > <klauskvik@hotmail.com> wrote: > > >On Saturday, June 3, 2017 at 12:58:42 AM UTC+2, k...@notreal.com wrote:> >> The datasheet (and you) claimed that it was a single chip.> >NO. Did you read the first post at all? - the thread is about reliability of a TWO die solution... > > But then you kept saying "on chip", as does the datasheet. It's not. > It's a kludge.One chip, with two dice. The flash is useful as a read-mainly store, so the odd mounting makes some sense. It doesn't NEED heatsinking, or lots of wire connection. I'm uncertain what "it's a kludge" signifies. Does this relate to your filing system "put this in the folder marked KLUDGE"? Folders marked "miscellaneous' don't make sense either.
Reply by ●June 3, 20172017-06-03
On Sat, 3 Jun 2017 15:09:41 -0700 (PDT), whit3rd <whit3rd@gmail.com> wrote:>On Friday, June 2, 2017 at 4:31:59 PM UTC-7, k...@notreal.com wrote: >> On Fri, 2 Jun 2017 16:27:01 -0700 (PDT), Klaus Kragelund >> <klauskvik@hotmail.com> wrote: >> >> >On Saturday, June 3, 2017 at 12:58:42 AM UTC+2, k...@notreal.com wrote: > >> >> The datasheet (and you) claimed that it was a single chip. > >> >NO. Did you read the first post at all? - the thread is about reliability of a TWO die solution... >> >> But then you kept saying "on chip", as does the datasheet. It's not. >> It's a kludge. > >One chip, with two dice. The flash is useful as a read-mainly store, so the odd >mounting makes some sense. It doesn't NEED heatsinking, or lots of >wire connection.No, one module with two chips. AKA (a poorly done) MCM (multi-chip module).>I'm uncertain what "it's a kludge" signifies. Does this relate to your filing system >"put this in the folder marked KLUDGE"? >Folders marked "miscellaneous' don't make sense either.No, this part goes into my recycle bin.
