On Friday, 2 June 2017 02:04:06 UTC+2, rickman wrote:> Klaus Kragelund wrote on 6/1/2017 7:47 PM: > > Datasheet: > > > > http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > > WTF? You had to find the data sheet on a third party web site??? > > Ok, I dug a bit at gsense.com and it seems they are the parent company. How > did you find the data sheet? >Google is your friend> > > Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > > Where did you get a price? >Page 11: http://site.eettaiwan.com/events/iot/201607/pdf/GigaDevice-GD32-Cortex-M3-MCU-ECCN.pdf> > > The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > > Huh? Having two die is not so cheap. If two separate die are "always" > better, why do they combine the Flash with CPU in most cases for chips in > this range? >In this case it's cheaper, as far as I know because they only pay ARM licencing for a chip without flash, and they have good grip on the flash technology> > > Operation from SRAM draws less current > > I don't see that in the numbers in the data sheet. ~300 uA/MHz. >It's not specifically stated. For reference look up the STM32 datasheet Cheers Klaus
Reliability of microcontroller silicon die glue on top of another die
Started by ●May 31, 2017
Reply by ●June 2, 20172017-06-02
Reply by ●June 2, 20172017-06-02
On Friday, 2 June 2017 02:24:30 UTC+2, k...@notreal.com wrote:> On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: > > >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund > ><klauskvik@hotmail.com> wrote: > > > >>Datasheet: > >> > >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > >> > >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > > > >Where? > >> > >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > > > >That's certainly not true. If it were, there wouldn't be mixed > >technology chips. > > > >>Operation from SRAM draws less current > > > >Not buying it, at least reads (operation). Note that both are zero > >wait-states so no advantage there. > > BTW, the datasheet claims 3MB "on-chip" flash? That's not what we > were discussing (and *really* hard to believe). I shoulda checked the > date on the datasheet (4/1? ;).Check the reverse engineering document. They have serial flash, so it is up to 3MB Cheers Klaus
Reply by ●June 2, 20172017-06-02
On Friday, 2 June 2017 05:11:10 UTC+2, whit3rd wrote:> On Thursday, June 1, 2017 at 3:40:54 PM UTC-7, k...@notreal.com wrote: > > On Thu, 1 Jun 2017 15:37:46 -0700 (PDT), Lasse Langwadt Christensen > > <langwadt@fonz.dk> wrote: > > > > >Den fredag den 2. juni 2017 kl. 00.21.49 UTC+2 skrev k...@notreal.com: > > [about flash piggybacked on CPU die] > > > >> ... The whole idea is goofy. > > > > > >why? > > > > 1. It's a kludge > > A 'kludge' like adding another level of cache? When the manufacturer does it > for you, you TAKE it and enjoy. Intel's Pentiums got more useful when they > went to the Pentium Pro and various other multichip modules. > > > 2. SRAM is expensive/Flash is cheap > > Only in mass production. The flash requires more masks, and odd thin oxides > with steps (for the floating gates) that can be omitted from a CPU. > SRAM is identical to other CPU logic and registers, no extra masks or process steps. > If you already have a FLASH production line, it makes sense to multipurpose its > chip output for other products. > > > 3. Faster uCs are available, if necessary > ?so? > > > 4. Off-chip flash is trivial and incredibly cheap. > > But, if there's enough ON-chip flash, some customers will pay to avoid the 'extra part'. > Low power dissipation in the flash chip makes it a reasonable packaging decision. > > > Bottom line: it's a solution looking for a problem. > > It's an affordable upgrade from a bare-bones CPU, and when a design > gets to the find-more-resources stage, this can be an easy sale. It makes business > sense. It makes extra-special sense when the unexpected problem arises. > > That's happened to me, once or twice.Yes, exactly. And when before in history did you have the opportunity to have a almost real second source for a microcontroller, like here for the STM32/GD32 You have to go back to the 8051 I guess Cheers Klaus
Reply by ●June 2, 20172017-06-02
On Friday, 2 June 2017 00:40:54 UTC+2, k...@notreal.com wrote:> On Thu, 1 Jun 2017 15:37:46 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > > >Den fredag den 2. juni 2017 kl. 00.21.49 UTC+2 skrev k...@notreal.com: > >> On Thu, 1 Jun 2017 14:56:18 -0400, rickman <gnuarm@gmail.com> wrote: > >> > >> >Lasse Langwadt Christensen wrote on 6/1/2017 1:14 PM: > >> >> Den torsdag den 1. juni 2017 kl. 18.58.11 UTC+2 skrev k...@notreal.com: > >> >>> On Wed, 31 May 2017 23:27:10 -0700 (PDT), Klaus Kragelund > >> >>> <klauskvik@hotmail.com> wrote: > >> >>> > >> >>>> Advantages: Flash is loaded to SRAM, so zero wait stage performance, almost double as a standard M3.... > >> >>> > >> >>> Huh? ARMs are flash rich and SRAM poor. If you want double the > >> >>> performance, go to an M7. SRAM is expensive. > >> >> > >> >> yeh, afair from when I was involved with something similar, SRAM is something > >> >> like 4x the die area and higher standby current than flash > >> >> > >> >> the though I guess some of the die area penalty might be reduced by being able to use smaller process that doesn't have flash > >> > > >> >Is there any reason to argue the concept when the details can be viewed? > >> > >> You found details? > >> > >> >Er, ah, I can't seem to find any data sheets on their MCUs. The web site is > >> >rather goofy. It has a selection guide, but once you locate a part number > >> >there are no links to more info. I found a page with data sheets, but none > >> >for the MCUs. Very strange. > >> > >> I didn't think so. The whole idea is goofy. > > > >why? > > 1. It's a kludge > 2. SRAM is expensive/Flash is cheapWhen I quote microcontrollers, there a strong correlation between flash and price, so that is not true. In some cases it's actually the testing of the flash that makes the difference, and the yields
Reply by ●June 2, 20172017-06-02
On 02/06/17 00:40, krw@notreal.com wrote:> On Thu, 1 Jun 2017 15:37:46 -0700 (PDT), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: > >> Den fredag den 2. juni 2017 kl. 00.21.49 UTC+2 skrev k...@notreal.com: >>> On Thu, 1 Jun 2017 14:56:18 -0400, rickman <gnuarm@gmail.com> wrote: >>> >>>> Lasse Langwadt Christensen wrote on 6/1/2017 1:14 PM: >>>>> Den torsdag den 1. juni 2017 kl. 18.58.11 UTC+2 skrev k...@notreal.com: >>>>>> On Wed, 31 May 2017 23:27:10 -0700 (PDT), Klaus Kragelund >>>>>> <klauskvik@hotmail.com> wrote: >>>>>> >>>>>>> Advantages: Flash is loaded to SRAM, so zero wait stage performance, almost double as a standard M3.... >>>>>> >>>>>> Huh? ARMs are flash rich and SRAM poor. If you want double the >>>>>> performance, go to an M7. SRAM is expensive. >>>>> >>>>> yeh, afair from when I was involved with something similar, SRAM is something >>>>> like 4x the die area and higher standby current than flash >>>>> >>>>> the though I guess some of the die area penalty might be reduced by being able to use smaller process that doesn't have flash >>>> >>>> Is there any reason to argue the concept when the details can be viewed? >>> >>> You found details? >>> >>>> Er, ah, I can't seem to find any data sheets on their MCUs. The web site is >>>> rather goofy. It has a selection guide, but once you locate a part number >>>> there are no links to more info. I found a page with data sheets, but none >>>> for the MCUs. Very strange. >>> >>> I didn't think so. The whole idea is goofy. >> >> why? > > 1. It's a kludge > 2. SRAM is expensive/Flash is cheap > 3. Faster uCs are available, if necessary > 4. Off-chip flash is trivial and incredibly cheap. > Bottom line: it's a solution looking for a problem. >Separate processor and memory dies inside one device is not new - though usually it is a little neater than this example. While flash is cheap in itself, the die stackup (number and type of layers, sizes, etc.) that is ideal for flash is not the same as the stackup that is ideal for a microcontroller or SRAM. With modern flash designs, and modern microcontroller designs, it is not too much of a compromise to combine them - and it results in a much cheaper chip. But for older designs, there was a bigger difference - it would not surprise me if a two-die solution had lower power, for example.
Reply by ●June 2, 20172017-06-02
klaus.kragelund@gmail.com wrote on 6/2/2017 4:13 AM:> On Friday, 2 June 2017 02:04:06 UTC+2, rickman wrote: >> Klaus Kragelund wrote on 6/1/2017 7:47 PM: >>> Datasheet: >>> >>> http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf >> >> WTF? You had to find the data sheet on a third party web site??? >> >> Ok, I dug a bit at gsense.com and it seems they are the parent company. How >> did you find the data sheet? >> > > Google is your friendIf I have to use Google to find a data sheet, I figure the company must not make the parts anymore or at least aren't looking for sales.>>> Price = 0.3 USD in volume, at least 25% cheaper than the STM32 >> >> Where did you get a price? >> > > Page 11: > > http://site.eettaiwan.com/events/iot/201607/pdf/GigaDevice-GD32-Cortex-M3-MCU-ECCN.pdfOk, a BS marketing price. Which part, what quantity...>>> The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies >> >> Huh? Having two die is not so cheap. If two separate die are "always" >> better, why do they combine the Flash with CPU in most cases for chips in >> this range? >> > > In this case it's cheaper, as far as I know because they only pay ARM licencing for a chip without flash, and they have good grip on the flash technologyWho says it is cheaper? If you can't buy them it doesn't matter. I can't find anyone who sells them.>>> Operation from SRAM draws less current >> >> I don't see that in the numbers in the data sheet. ~300 uA/MHz. >> > > It's not specifically stated. For reference look up the STM32 datasheetThe point is 300 uA/MHz is not even in the running for low power these days. The fact that running from SRAM *should* use less current doesn't mean their chips are competitive. I believe the forefront of low power ARMs is in the 100 uA/MHz these days. Am I mistaken? -- Rick C
Reply by ●June 2, 20172017-06-02
On Fri, 2 Jun 2017 01:19:05 -0700 (PDT), klaus.kragelund@gmail.com wrote:>On Friday, 2 June 2017 02:24:30 UTC+2, k...@notreal.com wrote: >> On Thu, 01 Jun 2017 20:20:32 -0400, krw@notreal.com wrote: >> >> >On Thu, 1 Jun 2017 16:47:07 -0700 (PDT), Klaus Kragelund >> ><klauskvik@hotmail.com> wrote: >> > >> >>Datasheet: >> >> >> >>http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf >> >> >> >>Price = 0.3 USD in volume, at least 25% cheaper than the STM32 >> > >> >Where? >> >> >> >>The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies >> > >> >That's certainly not true. If it were, there wouldn't be mixed >> >technology chips. >> > >> >>Operation from SRAM draws less current >> > >> >Not buying it, at least reads (operation). Note that both are zero >> >wait-states so no advantage there. >> >> BTW, the datasheet claims 3MB "on-chip" flash? That's not what we >> were discussing (and *really* hard to believe). I shoulda checked the >> date on the datasheet (4/1? ;). > >Check the reverse engineering document. They have serial flash, so it is up to 3MBYou've said so many things contrary to the datasheet and yourself, and it's equally opaque, that I have no idea what you're talking about anymore.
Reply by ●June 2, 20172017-06-02
On Thu, 1 Jun 2017 20:10:59 -0700 (PDT), whit3rd <whit3rd@gmail.com> wrote:>On Thursday, June 1, 2017 at 3:40:54 PM UTC-7, k...@notreal.com wrote: >> On Thu, 1 Jun 2017 15:37:46 -0700 (PDT), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >> >Den fredag den 2. juni 2017 kl. 00.21.49 UTC+2 skrev k...@notreal.com: > >[about flash piggybacked on CPU die] > >> >> ... The whole idea is goofy. >> > >> >why? >> >> 1. It's a kludge > >A 'kludge' like adding another level of cache? When the manufacturer does it >for you, you TAKE it and enjoy. Intel's Pentiums got more useful when they >went to the Pentium Pro and various other multichip modules.Well, perhaps as klugy as adding another level of cache to an M3.>> 2. SRAM is expensive/Flash is cheap > >Only in mass production.Duh! WTF are we talking about one-off ARMs? <moron>>The flash requires more masks, and odd thin oxides >with steps (for the floating gates) that can be omitted from a CPU. >SRAM is identical to other CPU logic and registers, no extra masks or process steps. >If you already have a FLASH production line, it makes sense to multipurpose its >chip output for other products.SRAM takes 10x the silicon. End of discussion.> >> 3. Faster uCs are available, if necessary >?so? > >> 4. Off-chip flash is trivial and incredibly cheap. > >But, if there's enough ON-chip flash, some customers will pay to avoid the 'extra part'. >Low power dissipation in the flash chip makes it a reasonable packaging decision.IT'S NOT ON-CHIP MORON!>> Bottom line: it's a solution looking for a problem. > >It's an affordable upgrade from a bare-bones CPU, and when a design >gets to the find-more-resources stage, this can be an easy sale. It makes business >sense. It makes extra-special sense when the unexpected problem arises.Bullshit.>That's happened to me, once or twice.I can imagine.
Reply by ●June 2, 20172017-06-02
On Friday, 2 June 2017 17:21:13 UTC+2, rickman wrote:> klaus.kragelund@gmail.com wrote on 6/2/2017 4:13 AM: > > On Friday, 2 June 2017 02:04:06 UTC+2, rickman wrote: > >> Klaus Kragelund wrote on 6/1/2017 7:47 PM: > >>> Datasheet: > >>> > >>> http://www.gsense.com.cn/Uploadfiles/20144241734995881.pdf > >> > >> WTF? You had to find the data sheet on a third party web site??? > >> > >> Ok, I dug a bit at gsense.com and it seems they are the parent company. How > >> did you find the data sheet? > >> > > > > Google is your friend > > If I have to use Google to find a data sheet, I figure the company must not > make the parts anymore or at least aren't looking for sales. > > > >>> Price = 0.3 USD in volume, at least 25% cheaper than the STM32 > >> > >> Where did you get a price? > >> > > > > Page 11: > > > > http://site.eettaiwan.com/events/iot/201607/pdf/GigaDevice-GD32-Cortex-M3-MCU-ECCN.pdf > > Ok, a BS marketing price. Which part, what quantity... >I talked to the sales guy at electronica 2016 and he stated even lower prices in volume. So the price is ok> > >>> The process is split, so one is logic and SRAM. The other is flash. Always cheaper to separate technologies > >> > >> Huh? Having two die is not so cheap. If two separate die are "always" > >> better, why do they combine the Flash with CPU in most cases for chips in > >> this range? > >> > > > > In this case it's cheaper, as far as I know because they only pay ARM licencing for a chip without flash, and they have good grip on the flash technology > > Who says it is cheaper? If you can't buy them it doesn't matter. I can't > find anyone who sells them. >They are just moving to the european marked, have sold 100 million devices in china, so I think you will be hearing about them a lot in the future> > >>> Operation from SRAM draws less current > >> > >> I don't see that in the numbers in the data sheet. ~300 uA/MHz. > >> > > > > It's not specifically stated. For reference look up the STM32 datasheet > > The point is 300 uA/MHz is not even in the running for low power these days. > The fact that running from SRAM *should* use less current doesn't mean > their chips are competitive. I believe the forefront of low power ARMs is > in the 100 uA/MHz these days. Am I mistaken?Sort of. THe low current is normally the M0+. The older devices, value line, is about 1mA/MHz Cheers Klaus
Reply by ●June 2, 20172017-06-02
On Fri, 02 Jun 2017 15:38:47 +0200, David Brown <david.brown@hesbynett.no> wrote:>On 02/06/17 00:40, krw@notreal.com wrote: >> On Thu, 1 Jun 2017 15:37:46 -0700 (PDT), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >>> Den fredag den 2. juni 2017 kl. 00.21.49 UTC+2 skrev k...@notreal.com: >>>> On Thu, 1 Jun 2017 14:56:18 -0400, rickman <gnuarm@gmail.com> wrote: >>>> >>>>> Lasse Langwadt Christensen wrote on 6/1/2017 1:14 PM: >>>>>> Den torsdag den 1. juni 2017 kl. 18.58.11 UTC+2 skrev k...@notreal.com: >>>>>>> On Wed, 31 May 2017 23:27:10 -0700 (PDT), Klaus Kragelund >>>>>>> <klauskvik@hotmail.com> wrote: >>>>>>> >>>>>>>> Advantages: Flash is loaded to SRAM, so zero wait stage performance, almost double as a standard M3.... >>>>>>> >>>>>>> Huh? ARMs are flash rich and SRAM poor. If you want double the >>>>>>> performance, go to an M7. SRAM is expensive. >>>>>> >>>>>> yeh, afair from when I was involved with something similar, SRAM is something >>>>>> like 4x the die area and higher standby current than flash >>>>>> >>>>>> the though I guess some of the die area penalty might be reduced by being able to use smaller process that doesn't have flash >>>>> >>>>> Is there any reason to argue the concept when the details can be viewed? >>>> >>>> You found details? >>>> >>>>> Er, ah, I can't seem to find any data sheets on their MCUs. The web site is >>>>> rather goofy. It has a selection guide, but once you locate a part number >>>>> there are no links to more info. I found a page with data sheets, but none >>>>> for the MCUs. Very strange. >>>> >>>> I didn't think so. The whole idea is goofy. >>> >>> why? >> >> 1. It's a kludge >> 2. SRAM is expensive/Flash is cheap >> 3. Faster uCs are available, if necessary >> 4. Off-chip flash is trivial and incredibly cheap. >> Bottom line: it's a solution looking for a problem. >> > >Separate processor and memory dies inside one device is not new - though >usually it is a little neater than this example. While flash is cheap >in itself, the die stackup (number and type of layers, sizes, etc.) that >is ideal for flash is not the same as the stackup that is ideal for a >microcontroller or SRAM. With modern flash designs, and modern >microcontroller designs, it is not too much of a compromise to combine >them - and it results in a much cheaper chip. But for older designs, >there was a bigger difference - it would not surprise me if a two-die >solution had lower power, for example. >Bottom line: It's a frappin' kludge.
