I'm doing a fast thing and thought I might go all CMOS, instead of traditional expensive ECL. We have the Fairchild NC7SV74 tiny logic flipflop in stock, 16 cents each. I thought I'd play with one. Here are the rise and fall times at the Q output, 3.3 volt supply: https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74_2.JPG That fall time is amazing, but the rise time is hard to believe. I can't see that I'm doing anything wrong. The clock rise to Q rise prop delay is 0.8 ns. Its temperature coefficient was hard to measure, but it looks like maybe +0.7 ps per degree C. Vcc delay coefficient is so close to zero that it doesn't matter. -- John Larkin Highland Technology, Inc lunatic fringe electronics
insane flipflop measurements
Started by ●January 31, 2017
Reply by ●January 31, 20172017-01-31
On Monday, January 30, 2017 at 8:08:21 PM UTC-8, John Larkin wrote:> That fall time is amazing, but the rise time is hard to believe. I > can't see that I'm doing anything wrong.Neat, the data sheet says Tr = 2.5 ns. Photo of test setup? -- john, KE5FX
Reply by ●January 31, 20172017-01-31
On Tuesday, January 31, 2017 at 5:08:21 AM UTC+1, John Larkin wrote:> I'm doing a fast thing and thought I might go all CMOS, instead of > traditional expensive ECL. We have the Fairchild NC7SV74 tiny logic > flipflop in stock, 16 cents each. I thought I'd play with one. > > Here are the rise and fall times at the Q output, 3.3 volt supply: > > https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74_2.JPG > > That fall time is amazing, but the rise time is hard to believe. I > can't see that I'm doing anything wrong. > > The clock rise to Q rise prop delay is 0.8 ns. Its temperature > coefficient was hard to measure, but it looks like maybe +0.7 ps per > degree C. Vcc delay coefficient is so close to zero that it doesn't > matter. >Nice measurements :-) We use it also, but never bothered to do any qualification Isn't it the rise time that is beyond amazing? Cheers Klaus
Reply by ●January 31, 20172017-01-31
Am 31.01.2017 um 05:08 schrieb John Larkin:> > > I'm doing a fast thing and thought I might go all CMOS, instead of > traditional expensive ECL. We have the Fairchild NC7SV74 tiny logic > flipflop in stock, 16 cents each. I thought I'd play with one. > > Here are the rise and fall times at the Q output, 3.3 volt supply: > > https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74_2.JPG > > That fall time is amazing, but the rise time is hard to believe. I > can't see that I'm doing anything wrong. > > The clock rise to Q rise prop delay is 0.8 ns. Its temperature > coefficient was hard to measure, but it looks like maybe +0.7 ps per > degree C. Vcc delay coefficient is so close to zero that it doesn't > matter. > >Looks interesting! This is what I got from a pair of SN74LVC1G04DCKR, 50 Ohm source and load terminated, running on 6V, still legal. I wanted acceptable 3V3 CMOS levels @ 50R input. It varies somewhat from batch to batch. < https://www.flickr.com/photos/137684711@N07/32245910100/in/album-72157662535945536/lightbox/ > and left/right Scope rise time is 145 ps. cheers, Gerhard
Reply by ●January 31, 20172017-01-31
On Mon, 30 Jan 2017 20:08:11 -0800, John Larkin <jjlarkin@highlandtechnology.com> wrote:> > >I'm doing a fast thing and thought I might go all CMOS, instead of >traditional expensive ECL. We have the Fairchild NC7SV74 tiny logic >flipflop in stock, 16 cents each. I thought I'd play with one. > >Here are the rise and fall times at the Q output, 3.3 volt supply: > >https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74_2.JPG > >That fall time is amazing, but the rise time is hard to believe. I >can't see that I'm doing anything wrong. > >The clock rise to Q rise prop delay is 0.8 ns. Its temperature >coefficient was hard to measure, but it looks like maybe +0.7 ps per >degree C. Vcc delay coefficient is so close to zero that it doesn't >matter.How much load were you driving? -- Boris --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus
Reply by ●January 31, 20172017-01-31
On Tue, 31 Jan 2017 00:32:04 -0800 (PST), Klaus Kragelund <klauskvik@hotmail.com> wrote:>On Tuesday, January 31, 2017 at 5:08:21 AM UTC+1, John Larkin wrote: >> I'm doing a fast thing and thought I might go all CMOS, instead of >> traditional expensive ECL. We have the Fairchild NC7SV74 tiny logic >> flipflop in stock, 16 cents each. I thought I'd play with one. >> >> Here are the rise and fall times at the Q output, 3.3 volt supply: >> >> https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74_2.JPG >> >> That fall time is amazing, but the rise time is hard to believe. I >> can't see that I'm doing anything wrong. >> >> The clock rise to Q rise prop delay is 0.8 ns. Its temperature >> coefficient was hard to measure, but it looks like maybe +0.7 ps per >> degree C. Vcc delay coefficient is so close to zero that it doesn't >> matter. >> >Nice measurements :-)If believable. The rise time makes no sense. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●January 31, 20172017-01-31
On Tue, 31 Jan 2017 08:36:42 -0500, Boris Mohar <borism_void_@sympatico.ca> wrote:>On Mon, 30 Jan 2017 20:08:11 -0800, John Larkin ><jjlarkin@highlandtechnology.com> wrote: > >> >> >>I'm doing a fast thing and thought I might go all CMOS, instead of >>traditional expensive ECL. We have the Fairchild NC7SV74 tiny logic >>flipflop in stock, 16 cents each. I thought I'd play with one. >> >>Here are the rise and fall times at the Q output, 3.3 volt supply: >> >>https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74_2.JPG >> >>That fall time is amazing, but the rise time is hard to believe. I >>can't see that I'm doing anything wrong. >> >>The clock rise to Q rise prop delay is 0.8 ns. Its temperature >>coefficient was hard to measure, but it looks like maybe +0.7 ps per >>degree C. Vcc delay coefficient is so close to zero that it doesn't >>matter. > > How much load were you driving?Just 500 ohms, a series resistor into a 50 ohm coax. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●January 31, 20172017-01-31
On Mon, 30 Jan 2017 20:08:11 -0800, John Larkin wrote:> I'm doing a fast thing and thought I might go all CMOS, instead of > traditional expensive ECL. We have the Fairchild NC7SV74 tiny logic > flipflop in stock, 16 cents each. I thought I'd play with one. > > Here are the rise and fall times at the Q output, 3.3 volt supply: > > https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74_2.JPG > > That fall time is amazing, but the rise time is hard to believe. I > can't see that I'm doing anything wrong. > > The clock rise to Q rise prop delay is 0.8 ns. Its temperature > coefficient was hard to measure, but it looks like maybe +0.7 ps per > degree C. Vcc delay coefficient is so close to zero that it doesn't > matter.From the sticky-note, the risetime is from the clock; the falltime from Clear. Does the fall-time change if the device is configured to toggle? {WAG not what you want in your application}
Reply by ●January 31, 20172017-01-31
John Larkin wrote:> > > I'm doing a fast thing and thought I might go all CMOS, instead of > traditional expensive ECL. We have the Fairchild NC7SV74 tiny logic > flipflop in stock, 16 cents each. I thought I'd play with one. > > Here are the rise and fall times at the Q output, 3.3 volt supply: > > https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74_2.JPG > > That fall time is amazing, but the rise time is hard to believe. I > can't see that I'm doing anything wrong. > > The clock rise to Q rise prop delay is 0.8 ns. Its temperature > coefficient was hard to measure, but it looks like maybe +0.7 ps per > degree C. Vcc delay coefficient is so close to zero that it doesn't > matter. > >Watch out for the shoot-through current on fast CMOS parts. I did a design some years ago, mixed-signal stuff, and had insideous crosstalk issues. After realizing what it might be, I discovered the single-gate and single-FF parts had a shoot-through of about 0.5 - 1 A that lasted about 3 ns (might have been shorter, that was the best I could resolve with the scope and probes I was using.) I was using the TI SN74LVC1Gxxx family. I then tried the NXP 74AUP1Gxxx family as they specified a really low "equivalent switching charge" and in fact, the shoot-through was not measurable. That required a complete redesign of the boards, though! Jon
Reply by ●January 31, 20172017-01-31
On Tue, 31 Jan 2017 00:22:23 -0800 (PST), "John Miles, KE5FX" <jmiles@gmail.com> wrote:>On Monday, January 30, 2017 at 8:08:21 PM UTC-8, John Larkin wrote: >> That fall time is amazing, but the rise time is hard to believe. I >> can't see that I'm doing anything wrong. > >Neat, the data sheet says Tr = 2.5 ns. > >Photo of test setup? > >-- john, KE5FXHere's the breadboard. https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74/NC7SV74_test.JPG I didn't expect it to be so fast, and the carbon film resistor pickoff from Q to the scope is maybe questionable. But I tried probing Q with an HP54006A resistive probe, rated 6 GHz, and the risetime is still around 200 ps. At that point, my breadboard starts to matter. That US8 adapter is something I threw onto another PCB layout just for fun, not intended for this sort of speed. US8s are horrible little packages. This flop, pulsed at clock and clear, cheerfully makes a reasonably square 700 ps pulse. I would have expected the fall (nfet) to be faster than the rise (pfet) but semiconductors make no sense. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
