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insane flipflop measurements

Started by John Larkin January 31, 2017
Den tirsdag den 31. januar 2017 kl. 05.08.21 UTC+1 skrev John Larkin:
> I'm doing a fast thing and thought I might go all CMOS, instead of > traditional expensive ECL. We have the Fairchild NC7SV74 tiny logic > flipflop in stock, 16 cents each. I thought I'd play with one. > > Here are the rise and fall times at the Q output, 3.3 volt supply: > > https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74_2.JPG > > That fall time is amazing, but the rise time is hard to believe. I > can't see that I'm doing anything wrong. > > The clock rise to Q rise prop delay is 0.8 ns. Its temperature > coefficient was hard to measure, but it looks like maybe +0.7 ps per > degree C. Vcc delay coefficient is so close to zero that it doesn't > matter. >
you should be able to get the all "real" numbers from the ibis file this isn't right part number but it was the first I found http://www.datasheetarchive.com/files/fairchild/simulation-models/nc7sz74l8x.ibs look at around line 16967 for falling waveform at 5V
On Wed, 1 Feb 2017 15:47:17 -0800 (PST), "John Miles, KE5FX"
<jmiles@gmail.com> wrote:

>On Wednesday, February 1, 2017 at 7:09:28 AM UTC-8, John Larkin wrote: >> I don't see a Tr or Tf spec in the data sheet. The 2.5 ns, in one >> figure, seems to be a max for the clock input. > >Hmm, you're right, the waveform on page 7 is labeled CP Input ( >https://www.fairchildsemi.com/datasheets/NC/NC7SV74.pdf ). > >Definitely nothing in that data sheet to suggest transition times >in the hundreds of ps. It would be funny if it turned out that >cheap carbon film resistors act like shock lines. > >-- john, KE5FX
Well, that's unlikely. Somebody would have noticed by now. I repeated the tests with the HP resistive, 6GHz, probe, and it looked about the same. The Q and Qbar outputs look about the same. This is really cool: https://dl.dropboxusercontent.com/u/53724080/Gear/HP/HP54006_probe.zip -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
John Larkin wrote:
> On Tue, 31 Jan 2017 00:32:04 -0800 (PST), Klaus Kragelund > <klauskvik@hotmail.com> wrote: > >> On Tuesday, January 31, 2017 at 5:08:21 AM UTC+1, John Larkin wrote: >>> I'm doing a fast thing and thought I might go all CMOS, instead of >>> traditional expensive ECL. We have the Fairchild NC7SV74 tiny logic >>> flipflop in stock, 16 cents each. I thought I'd play with one. >>> >>> Here are the rise and fall times at the Q output, 3.3 volt supply: >>> >>> https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74_2.JPG >>> >>> That fall time is amazing, but the rise time is hard to believe. I >>> can't see that I'm doing anything wrong. >>> >>> The clock rise to Q rise prop delay is 0.8 ns. Its temperature >>> coefficient was hard to measure, but it looks like maybe +0.7 ps per >>> degree C. Vcc delay coefficient is so close to zero that it doesn't >>> matter. >>> >> Nice measurements :-) > > If believable. The rise time makes no sense.
Then try it with a different scope.
>>Nice measurements :-)
>If believable. The rise time makes no sense.
I'm using a nice LVDS->CMOS receiver chip that has typical rise and fall times in that range, according to a datasheet plot of t_R vs C_load. (I'm not at my computer or I'd post a datasheet link.) Of course that's at very low C_load. Cheers Phil Hobbs
On 02/02/2017 07:16 AM, pcdhobbs@gmail.com wrote:
>>> Nice measurements :-) > >> If believable. The rise time makes no sense. > > I'm using a nice LVDS->CMOS receiver chip that has typical rise and > fall times in that range, according to a datasheet plot of t_R vs > C_load. (I'm not at my computer or I'd post a datasheet link.) > > Of course that's at very low C_load. >
It's a FIN1002. Fairchild are being poopyheads and encrypting their datasheets for some reason, but you can get it from AllDatasheet: <http://pdf1.alldatasheet.com/datasheet-pdf/view/51715/FAIRCHILD/FIN1002.html>. Check out Figure 19. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Am 02.02.2017 um 17:13 schrieb Phil Hobbs:

> It's a FIN1002. Fairchild are being poopyheads and encrypting their > datasheets for some reason, but you can get it from AllDatasheet: > <http://pdf1.alldatasheet.com/datasheet-pdf/view/51715/FAIRCHILD/FIN1002.html>. > Check out Figure 19. >
< http://www.mouser.com/ds/2/149/FIN1002-1008540.pdf >
> Cheers
Gerhard
On 02/02/2017 11:29 AM, Gerhard Hoffmann wrote:
> Am 02.02.2017 um 17:13 schrieb Phil Hobbs: > >> It's a FIN1002. Fairchild are being poopyheads and encrypting their >> datasheets for some reason, but you can get it from AllDatasheet: >> <http://pdf1.alldatasheet.com/datasheet-pdf/view/51715/FAIRCHILD/FIN1002.html>. >> >> Check out Figure 19. >> > > < http://www.mouser.com/ds/2/149/FIN1002-1008540.pdf > > >> Cheers > Gerhard >
In that datasheet it's Figs 20 and 21. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
On Thu, 2 Feb 2017 06:17:34 -0500, "Tom Del Rosso"
<fizzbintuesday@that-google-mail-domain.com> wrote:

>John Larkin wrote: >> On Tue, 31 Jan 2017 00:32:04 -0800 (PST), Klaus Kragelund >> <klauskvik@hotmail.com> wrote: >> >>> On Tuesday, January 31, 2017 at 5:08:21 AM UTC+1, John Larkin wrote: >>>> I'm doing a fast thing and thought I might go all CMOS, instead of >>>> traditional expensive ECL. We have the Fairchild NC7SV74 tiny logic >>>> flipflop in stock, 16 cents each. I thought I'd play with one. >>>> >>>> Here are the rise and fall times at the Q output, 3.3 volt supply: >>>> >>>> https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74_2.JPG >>>> >>>> That fall time is amazing, but the rise time is hard to believe. I >>>> can't see that I'm doing anything wrong. >>>> >>>> The clock rise to Q rise prop delay is 0.8 ns. Its temperature >>>> coefficient was hard to measure, but it looks like maybe +0.7 ps per >>>> degree C. Vcc delay coefficient is so close to zero that it doesn't >>>> matter. >>>> >>> Nice measurements :-) >> >> If believable. The rise time makes no sense. > >Then try it with a different scope. > >
The 11802/SD24 has 20 GHz bendwidth, and it looks perfect using the calibrator pulse and its own TDR step. I see about the same waveform using the resistor pickoff vs the 6 GHz HP probe on the other sampling channel. That 150ish ps rise looks real. Amazing for a 16 cent CMOS part. -- John Larkin Highland Technology, Inc lunatic fringe electronics
On Thu, 2 Feb 2017 11:13:12 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 02/02/2017 07:16 AM, pcdhobbs@gmail.com wrote: >>>> Nice measurements :-) >> >>> If believable. The rise time makes no sense. >> >> I'm using a nice LVDS->CMOS receiver chip that has typical rise and >> fall times in that range, according to a datasheet plot of t_R vs >> C_load. (I'm not at my computer or I'd post a datasheet link.) >> >> Of course that's at very low C_load. >> > >It's a FIN1002. Fairchild are being poopyheads and encrypting their >datasheets for some reason, but you can get it from AllDatasheet: ><http://pdf1.alldatasheet.com/datasheet-pdf/view/51715/FAIRCHILD/FIN1002.html>. > Check out Figure 19. > >Cheers > >Phil Hobbs
Mouser has the PDF data sheet in plain sight. www.mouser.com/ds/2/149/FIN1002-108110.pdf Fig 16 shows the falling-edge transition time as just a bit below 1 picosecond, with a "p". Other figs suggest maybe 300 ps. The numbers are probably 20-80%, which improves the rise time considerably, for free. My flop would be closer to 100 ps, measured 20-80. That data sheet doesn't make a ton of sense. One thing that makes electronic design even more interesting is that data sheets are often wrong. We use the FIN1101 (lvds-lvds buffer) as a 1 ns RRI comparator. 85 cents. LVDS is great stuff. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Den torsdag den 2. februar 2017 kl. 17.45.17 UTC+1 skrev John Larkin:
> On Thu, 2 Feb 2017 06:17:34 -0500, "Tom Del Rosso" > <fizzbintuesday@that-google-mail-domain.com> wrote: > > >John Larkin wrote: > >> On Tue, 31 Jan 2017 00:32:04 -0800 (PST), Klaus Kragelund > >> <klauskvik@hotmail.com> wrote: > >> > >>> On Tuesday, January 31, 2017 at 5:08:21 AM UTC+1, John Larkin wrote: > >>>> I'm doing a fast thing and thought I might go all CMOS, instead of > >>>> traditional expensive ECL. We have the Fairchild NC7SV74 tiny logic > >>>> flipflop in stock, 16 cents each. I thought I'd play with one. > >>>> > >>>> Here are the rise and fall times at the Q output, 3.3 volt supply: > >>>> > >>>> https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/NC7SV74_2.JPG > >>>> > >>>> That fall time is amazing, but the rise time is hard to believe. I > >>>> can't see that I'm doing anything wrong. > >>>> > >>>> The clock rise to Q rise prop delay is 0.8 ns. Its temperature > >>>> coefficient was hard to measure, but it looks like maybe +0.7 ps per > >>>> degree C. Vcc delay coefficient is so close to zero that it doesn't > >>>> matter. > >>>> > >>> Nice measurements :-) > >> > >> If believable. The rise time makes no sense. > > > >Then try it with a different scope. > > > > > > The 11802/SD24 has 20 GHz bendwidth, and it looks perfect using the > calibrator pulse and its own TDR step. I see about the same waveform > using the resistor pickoff vs the 6 GHz HP probe on the other sampling > channel. > > That 150ish ps rise looks real. Amazing for a 16 cent CMOS part. >
here's a plot of the data in the ibis file for NC7SZ74, I can't find an ibis file for NC7SV74 http://imgur.com/a/AmOE2