On Mon, 16 Mar 2015 17:26:44 -0700, Joerg <news@analogconsultants.com>
wrote:
[snip]
Here you go...
.SUBCKT VControlledCap CAP+ CAP- VC+ VC- PARAMS: C1=1nF C2=100pF
C_C1 CAP+ N_1 {C1}
R_NOF1 VC+ 0 1G
R_NOF2 VC- 0 1G
V_IM1 N_1 CAP- 0
G_G2 CAP+ CAP- VALUE {C2/C1*V(VC+,VC-)*I(V_IM1)}
.ENDS VControlledCap
When VC=,VC1 is zero, cap value is C1
When VC=,VC1=+1, cap value is C1+C2
When VC=,VC1=-1, cap value is C1-C2
I'll post this to my website in a few days... honey-do projects abound
;-)
...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Voltage-variable capacitor doesn't work in LTSpice
Started by ●March 16, 2015
Reply by ●March 17, 20152015-03-17
Reply by ●March 17, 20152015-03-17
On Tue, 17 Mar 2015 13:06:35 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:>On Mon, 16 Mar 2015 17:26:44 -0700, Joerg <news@analogconsultants.com> >wrote: > >[snip] > >Here you go... > >.SUBCKT VControlledCap CAP+ CAP- VC+ VC- PARAMS: C1=1nF C2=100pF >C_C1 CAP+ N_1 {C1} >R_NOF1 VC+ 0 1G >R_NOF2 VC- 0 1G >V_IM1 N_1 CAP- 0 >G_G2 CAP+ CAP- VALUE {C2/C1*V(VC+,VC-)*I(V_IM1)} >.ENDS VControlledCap > >When VC=,VC1 is zero, cap value is C1 > >When VC=,VC1=+1, cap value is C1+C2 > >When VC=,VC1=-1, cap value is C1-C2 > >I'll post this to my website in a few days... honey-do projects abound >;-) > > ...Jim ThompsonTypos galore, lagging/leading shift key, text should say... When VC+,VC- is zero, cap value is C1 When VC+,VC- = +1, cap value is C1+C2 When VC+,VC- = -1, cap value is C1-C2 ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●March 17, 20152015-03-17
On 2015-03-17 1:24 PM, Jim Thompson wrote:> On Tue, 17 Mar 2015 13:06:35 -0700, Jim Thompson > <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: > >> On Mon, 16 Mar 2015 17:26:44 -0700, Joerg <news@analogconsultants.com> >> wrote: >> >> [snip] >> >> Here you go... >> >> .SUBCKT VControlledCap CAP+ CAP- VC+ VC- PARAMS: C1=1nF C2=100pF >> C_C1 CAP+ N_1 {C1} >> R_NOF1 VC+ 0 1G >> R_NOF2 VC- 0 1G >> V_IM1 N_1 CAP- 0 >> G_G2 CAP+ CAP- VALUE {C2/C1*V(VC+,VC-)*I(V_IM1)} >> .ENDS VControlledCap >> >> When VC=,VC1 is zero, cap value is C1 >> >> When VC=,VC1=+1, cap value is C1+C2 >> >> When VC=,VC1=-1, cap value is C1-C2 >> >> I'll post this to my website in a few days... honey-do projects abound >> ;-) >> >> ...Jim Thompson > > Typos galore, lagging/leading shift key, text should say... > > When VC+,VC- is zero, cap value is C1 > > When VC+,VC- = +1, cap value is C1+C2 > > When VC+,VC- = -1, cap value is C1-C2 >Thanks, Jim. Couldn't make a go of it yet, it errors with "Port(pin) count mismatch between the definition of subcircuit "vcontrolledcap" and instance: "xc1" ... The instance has fewer connection terminals than the definition" -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●March 17, 20152015-03-17
On Tue, 17 Mar 2015 17:04:42 -0700, Joerg <news@analogconsultants.com> wrote:>On 2015-03-17 1:24 PM, Jim Thompson wrote: >> On Tue, 17 Mar 2015 13:06:35 -0700, Jim Thompson >> <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >> >>> On Mon, 16 Mar 2015 17:26:44 -0700, Joerg <news@analogconsultants.com> >>> wrote: >>> >>> [snip] >>> >>> Here you go... >>> >>> .SUBCKT VControlledCap CAP+ CAP- VC+ VC- PARAMS: C1=1nF C2=100pF >>> C_C1 CAP+ N_1 {C1} >>> R_NOF1 VC+ 0 1G >>> R_NOF2 VC- 0 1G >>> V_IM1 N_1 CAP- 0 >>> G_G2 CAP+ CAP- VALUE {C2/C1*V(VC+,VC-)*I(V_IM1)} >>> .ENDS VControlledCap >>> >>> When VC=,VC1 is zero, cap value is C1 >>> >>> When VC=,VC1=+1, cap value is C1+C2 >>> >>> When VC=,VC1=-1, cap value is C1-C2 >>> >>> I'll post this to my website in a few days... honey-do projects abound >>> ;-) >>> >>> ...Jim Thompson >> >> Typos galore, lagging/leading shift key, text should say... >> >> When VC+,VC- is zero, cap value is C1 >> >> When VC+,VC- = +1, cap value is C1+C2 >> >> When VC+,VC- = -1, cap value is C1-C2 >> > >Thanks, Jim. Couldn't make a go of it yet, it errors with "Port(pin) >count mismatch between the definition of subcircuit "vcontrolledcap" and >instance: "xc1" ... The instance has fewer connection terminals than the >definition"Read the help files about how to make a symbol in LTspice by highlighting the .subckt line. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●March 17, 20152015-03-17
On Tue, 17 Mar 2015 17:04:42 -0700, Joerg <news@analogconsultants.com> wrote:>On 2015-03-17 1:24 PM, Jim Thompson wrote: >> On Tue, 17 Mar 2015 13:06:35 -0700, Jim Thompson >> <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >> >>> On Mon, 16 Mar 2015 17:26:44 -0700, Joerg <news@analogconsultants.com> >>> wrote: >>> >>> [snip] >>> >>> Here you go... >>> >>> .SUBCKT VControlledCap CAP+ CAP- VC+ VC- PARAMS: C1=1nF C2=100pF >>> C_C1 CAP+ N_1 {C1} >>> R_NOF1 VC+ 0 1G >>> R_NOF2 VC- 0 1G >>> V_IM1 N_1 CAP- 0 >>> G_G2 CAP+ CAP- VALUE {C2/C1*V(VC+,VC-)*I(V_IM1)} >>> .ENDS VControlledCap >>> >>> When VC=,VC1 is zero, cap value is C1 >>> >>> When VC=,VC1=+1, cap value is C1+C2 >>> >>> When VC=,VC1=-1, cap value is C1-C2 >>> >>> I'll post this to my website in a few days... honey-do projects abound >>> ;-) >>> >>> ...Jim Thompson >> >> Typos galore, lagging/leading shift key, text should say... >> >> When VC+,VC- is zero, cap value is C1 >> >> When VC+,VC- = +1, cap value is C1+C2 >> >> When VC+,VC- = -1, cap value is C1-C2 >> > >Thanks, Jim. Couldn't make a go of it yet, it errors with "Port(pin) >count mismatch between the definition of subcircuit "vcontrolledcap" and >instance: "xc1" ... The instance has fewer connection terminals than the >definition"I bet you could build a variable c-multiplier with a capacitor and a multiplier, or an e source with the right expression. -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●March 17, 20152015-03-17
John Larkin <jlarkin@highlandtechnology.com> wrote:> On Tue, 17 Mar 2015 17:04:42 -0700, Joerg <news@analogconsultants.com> > wrote: > >> On 2015-03-17 1:24 PM, Jim Thompson wrote: >>> On Tue, 17 Mar 2015 13:06:35 -0700, Jim Thompson >>> <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>> >>>> On Mon, 16 Mar 2015 17:26:44 -0700, Joerg <news@analogconsultants.com> >>>> wrote: >>>> >>>> [snip] >>>> >>>> Here you go... >>>> >>>> .SUBCKT VControlledCap CAP+ CAP- VC+ VC- PARAMS: C1=1nF C2=100pF >>>> C_C1 CAP+ N_1 {C1} >>>> R_NOF1 VC+ 0 1G >>>> R_NOF2 VC- 0 1G >>>> V_IM1 N_1 CAP- 0 >>>> G_G2 CAP+ CAP- VALUE {C2/C1*V(VC+,VC-)*I(V_IM1)} >>>> .ENDS VControlledCap >>>> >>>> When VC=,VC1 is zero, cap value is C1 >>>> >>>> When VC=,VC1=+1, cap value is C1+C2 >>>> >>>> When VC=,VC1=-1, cap value is C1-C2 >>>> >>>> I'll post this to my website in a few days... honey-do projects abound >>>> ;-) >>>> >>>> ...Jim Thompson >>> >>> Typos galore, lagging/leading shift key, text should say... >>> >>> When VC+,VC- is zero, cap value is C1 >>> >>> When VC+,VC- = +1, cap value is C1+C2 >>> >>> When VC+,VC- = -1, cap value is C1-C2 >>> >> >> Thanks, Jim. Couldn't make a go of it yet, it errors with "Port(pin) >> count mismatch between the definition of subcircuit "vcontrolledcap" and >> instance: "xc1" ... The instance has fewer connection terminals than the >> definition" > > I bet you could build a variable c-multiplier with a capacitor and a > multiplier, or an e source with the right expression. >If you dynamically change the value of a capacitor, do you end up with discontinuities in the stores charge on that cap?
Reply by ●March 17, 20152015-03-17
On Wed, 18 Mar 2015 02:22:11 GMT, Ralph Barone <address_is@invalid.invalid> wrote:>John Larkin <jlarkin@highlandtechnology.com> wrote: >> On Tue, 17 Mar 2015 17:04:42 -0700, Joerg <news@analogconsultants.com> >> wrote: >> >>> On 2015-03-17 1:24 PM, Jim Thompson wrote: >>>> On Tue, 17 Mar 2015 13:06:35 -0700, Jim Thompson >>>> <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>>> >>>>> On Mon, 16 Mar 2015 17:26:44 -0700, Joerg <news@analogconsultants.com> >>>>> wrote: >>>>> >>>>> [snip] >>>>> >>>>> Here you go... >>>>> >>>>> .SUBCKT VControlledCap CAP+ CAP- VC+ VC- PARAMS: C1=1nF C2=100pF >>>>> C_C1 CAP+ N_1 {C1} >>>>> R_NOF1 VC+ 0 1G >>>>> R_NOF2 VC- 0 1G >>>>> V_IM1 N_1 CAP- 0 >>>>> G_G2 CAP+ CAP- VALUE {C2/C1*V(VC+,VC-)*I(V_IM1)} >>>>> .ENDS VControlledCap >>>>> >>>>> When VC=,VC1 is zero, cap value is C1 >>>>> >>>>> When VC=,VC1=+1, cap value is C1+C2 >>>>> >>>>> When VC=,VC1=-1, cap value is C1-C2 >>>>> >>>>> I'll post this to my website in a few days... honey-do projects abound >>>>> ;-) >>>>> >>>>> ...Jim Thompson >>>> >>>> Typos galore, lagging/leading shift key, text should say... >>>> >>>> When VC+,VC- is zero, cap value is C1 >>>> >>>> When VC+,VC- = +1, cap value is C1+C2 >>>> >>>> When VC+,VC- = -1, cap value is C1-C2 >>>> >>> >>> Thanks, Jim. Couldn't make a go of it yet, it errors with "Port(pin) >>> count mismatch between the definition of subcircuit "vcontrolledcap" and >>> instance: "xc1" ... The instance has fewer connection terminals than the >>> definition" >> >> I bet you could build a variable c-multiplier with a capacitor and a >> multiplier, or an e source with the right expression. >> > > >If you dynamically change the value of a capacitor, do you end up with >discontinuities in the stores charge on that cap?I guess the only way to change the voltage across a voltage-dependant capacitor is to apply current, which takes power, so energy is conserved. A varicap doesn't violate conservation of energy. If a c value depended on something independent of the terminal voltage, you could apparently violate COE. Imagine a charged parallel-plate capacitor connected to nothing. If you yank (yank!) the plates apart, c goes down, Q is conserved, V goes up, and more energy is stored in the cap. Pulling the plates apart took mechanical work, which is where the added energy came from. In my proposed c-multiplier, the e source can do work. -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●March 18, 20152015-03-18
On 2015-03-17 7:44 PM, John Larkin wrote:> On Wed, 18 Mar 2015 02:22:11 GMT, Ralph Barone > <address_is@invalid.invalid> wrote: > >> John Larkin <jlarkin@highlandtechnology.com> wrote: >>> On Tue, 17 Mar 2015 17:04:42 -0700, Joerg <news@analogconsultants.com> >>> wrote: >>> >>>> On 2015-03-17 1:24 PM, Jim Thompson wrote: >>>>> On Tue, 17 Mar 2015 13:06:35 -0700, Jim Thompson >>>>> <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >>>>> >>>>>> On Mon, 16 Mar 2015 17:26:44 -0700, Joerg <news@analogconsultants.com> >>>>>> wrote: >>>>>> >>>>>> [snip] >>>>>> >>>>>> Here you go... >>>>>> >>>>>> .SUBCKT VControlledCap CAP+ CAP- VC+ VC- PARAMS: C1=1nF C2=100pF >>>>>> C_C1 CAP+ N_1 {C1} >>>>>> R_NOF1 VC+ 0 1G >>>>>> R_NOF2 VC- 0 1G >>>>>> V_IM1 N_1 CAP- 0 >>>>>> G_G2 CAP+ CAP- VALUE {C2/C1*V(VC+,VC-)*I(V_IM1)} >>>>>> .ENDS VControlledCap >>>>>> >>>>>> When VC=,VC1 is zero, cap value is C1 >>>>>> >>>>>> When VC=,VC1=+1, cap value is C1+C2 >>>>>> >>>>>> When VC=,VC1=-1, cap value is C1-C2 >>>>>> >>>>>> I'll post this to my website in a few days... honey-do projects abound >>>>>> ;-) >>>>>> >>>>>> ...Jim Thompson >>>>> >>>>> Typos galore, lagging/leading shift key, text should say... >>>>> >>>>> When VC+,VC- is zero, cap value is C1 >>>>> >>>>> When VC+,VC- = +1, cap value is C1+C2 >>>>> >>>>> When VC+,VC- = -1, cap value is C1-C2 >>>>> >>>> >>>> Thanks, Jim. Couldn't make a go of it yet, it errors with "Port(pin) >>>> count mismatch between the definition of subcircuit "vcontrolledcap" and >>>> instance: "xc1" ... The instance has fewer connection terminals than the >>>> definition" >>> >>> I bet you could build a variable c-multiplier with a capacitor and a >>> multiplier, or an e source with the right expression. >>> >> >> >> If you dynamically change the value of a capacitor, do you end up with >> discontinuities in the stores charge on that cap? > > I guess the only way to change the voltage across a voltage-dependant > capacitor is to apply current, which takes power, so energy is > conserved. A varicap doesn't violate conservation of energy. > > If a c value depended on something independent of the terminal > voltage, you could apparently violate COE. Imagine a charged > parallel-plate capacitor connected to nothing. If you yank (yank!) the > plates apart, c goes down, Q is conserved, V goes up, and more energy > is stored in the cap. Pulling the plates apart took mechanical work, > which is where the added energy came from. > > In my proposed c-multiplier, the e source can do work. >Guys, I do not want to change the capacitance by changing the voltage at the cap terminals. I want to change the capacitance by a mathematical expression where the control function is a rail (or a voltage) in some other distant land in the schematic. I still do not understand why this works perfectly for a resistor value but it does not for a capacitor value. For the resistor I do not have to make some other model with more terminals, I can just key in expressions such as "R=V(X)" in the value field where X is a rail somewhere else that I assign the label "X". -- Regards, Joerg http://www.analogconsultants.com/
Reply by ●March 18, 20152015-03-18
On Tue, 17 Mar 2015 17:04:42 -0700, Joerg <news@analogconsultants.com> wrote:>On 2015-03-17 1:24 PM, Jim Thompson wrote: >> On Tue, 17 Mar 2015 13:06:35 -0700, Jim Thompson >> <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >> >>> On Mon, 16 Mar 2015 17:26:44 -0700, Joerg <news@analogconsultants.com> >>> wrote: >>> >>> [snip] >>> >>> Here you go... >>> >>> .SUBCKT VControlledCap CAP+ CAP- VC+ VC- PARAMS: C1=1nF C2=100pF >>> C_C1 CAP+ N_1 {C1} >>> R_NOF1 VC+ 0 1G >>> R_NOF2 VC- 0 1G >>> V_IM1 N_1 CAP- 0 >>> G_G2 CAP+ CAP- VALUE {C2/C1*V(VC+,VC-)*I(V_IM1)} >>> .ENDS VControlledCap >>> >>> When VC=,VC1 is zero, cap value is C1 >>> >>> When VC=,VC1=+1, cap value is C1+C2 >>> >>> When VC=,VC1=-1, cap value is C1-C2 >>> >>> I'll post this to my website in a few days... honey-do projects abound >>> ;-) >>> >>> ...Jim Thompson >> >> Typos galore, lagging/leading shift key, text should say... >> >> When VC+,VC- is zero, cap value is C1 >> >> When VC+,VC- = +1, cap value is C1+C2 >> >> When VC+,VC- = -1, cap value is C1-C2 >> > >Thanks, Jim. Couldn't make a go of it yet, it errors with "Port(pin) >count mismatch between the definition of subcircuit "vcontrolledcap" and >instance: "xc1" ... The instance has fewer connection terminals than the >definition"To learn how to do this, search LTspice Help for "automatic symbol"... VControlledCap.asy Version 4 SymbolType BLOCK RECTANGLE Normal -64 -40 80 40 WINDOW 0 8 -40 Bottom 2 WINDOW 3 8 40 Top 2 WINDOW 39 8 64 Top 2 SYMATTR Prefix X SYMATTR Value VControlledCap SYMATTR ModelFile C:\Projects\Expments\BehavioralComponents\ASY Copy of VControlledCap.net SYMATTR SpiceLine C1=1nF C2=100pF PIN -64 -16 LEFT 8 PINATTR PinName CAP+ PINATTR SpiceOrder 1 PIN -64 16 LEFT 8 PINATTR PinName CAP- PINATTR SpiceOrder 2 PIN 80 -16 RIGHT 8 PINATTR PinName VC+ PINATTR SpiceOrder 3 PIN 80 16 RIGHT 8 PINATTR PinName VC- PINATTR SpiceOrder 4 ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●March 18, 20152015-03-18
On Wed, 18 Mar 2015 07:09:56 -0700, Joerg <news@analogconsultants.com> wrote: [snip]>> > >Guys, I do not want to change the capacitance by changing the voltage at >the cap terminals. I want to change the capacitance by a mathematical >expression where the control function is a rail (or a voltage) in some >other distant land in the schematic. I still do not understand why this >works perfectly for a resistor value but it does not for a capacitor >value. For the resistor I do not have to make some other model with more >terminals, I can just key in expressions such as "R=V(X)" in the value >field where X is a rail somewhere else that I assign the label "X".My previously posted subcircuit VControlledCap does exactly as you want. I have just now posted VControlledCap.asy so you can get the pinout correct >:-} ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
