DDS wisdom

On 12/9/2014 8:36 AM, Piotr Wyderski wrote:
> Phil Hobbs wrote:
>
>> Because the signal coming back is at VHF, and using nulling eliminates
>> the need for 2D calibration, as I said.  A DDS is less complicated to
>> use than a 200 MHz ADC, for sure, and it saves me a boatload of Mini
>> Circuits stuff getting the signal down to baseband, and several
>> expensive and phase-distorting filters getting rid of all the attendant
>> spurs.
>
> Just a final remark to close the discussion about this approach:
> undersampling?
>
>      Best regards, Piotr
>
Nope, won't work.  The required waveform accuracy to reach 14 bits of 
amplitude and phase is very difficult to attain, and requires a gigantic 
2-D calibration to fix.  That's the whole basis for using nulling.

What I'm planning to do is to put both the MPD-1 and ECLips Lite D-flops 
on the board, and try both.  I'm too chicken that the strobed comparator 
is going to oscillate fiercely.

Cheers

Phil Hobbs

-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

On 12/8/2014 8:49 PM, rickman wrote:
> On 12/8/2014 7:57 PM, Phil Hobbs wrote:
>> On 12/8/2014 7:10 PM, rickman wrote:
>>> On 12/8/2014 6:57 PM, Phil Hobbs wrote:
>>>>
>>>> If I thought I was always right about everything, I wouldn't need to
>>>> talk to anybody. ;)
>>>
>>> Lol, yeah.  That's a large part of why I'm here, to learn something in
>>> the areas I know less about, like most things analog.  Joerg helped me a
>>> lot a couple of weeks ago to learn about the Miller effect and cascode
>>> circuits.
>>>
>>> Have you figured out what people are referring to when they talk about
>>> the "phase jump" as the accumulator wraps around?  I'm thinking they are
>>> talking about the remainder that results from the non-integral ratio of
>>> the step size and modulus.  It's not really a "jump", but I can see
>>> someone referring to it that way in a conversation.
>>
>> It seems like the issue is that for many choices of the phase increment,
>> there's a spur very close to the carrier, associated with the actual
>> periodicity of the waveform.  With an N-bit accumulator, it's quite
>> possible for this to be many times longer than 2**N clock cycles, i.e.
>> far too long to be visible on frequency-domain instruments such as
>> spectrum analyzers, and long enough to be surprising to even fairly
>> sophisticated users.
>
> Yes, but a spur would not be described as a "phase jump" on "rollover".
>   Do you think this is what they are talking about?  That would be so
> far removed from what *is* happening that it's hard to imagine.
>
>
>>> I find it funny that some don't seem to really understand how a DDS
>>> works.  Joe Gwinn seems to think there is something different about the
>>> way Timing Solutions implemented a non-DDS so it didn't have spurs. "The
>>> actual frequency is tweaked such that there is no glitch when the memory
>>> rolls over."  I believe all they did was use the equivalent of a DDS
>>> circuit with limitations so there was no remainder.   I expect they
>>> incremented the phase by 1 and could only generate outputs that were
>>> integer ratios to the reference clock.
>>
>> The paper referenced upthread that used (instead of a sine LUT) a
>> two-turn CORDIC algorithm with AGC to generate the output is a pretty
>> good read.
>
> I didn't dig into all the papers people referenced.  I looked at some
> and didn't find much to explain what they were talking about.  What Joe
> described was a simple lookup table with sine values in it which is how
> a DDS works.  There are two forms of spurs from digital implementations.
>   One is from phase quantization and the other is from amplitude
> quantization.  Then the DAC has its own type of distortion which can
> also produce spurs but are not directly related to the fact that the
> data is digital.  The other two types are an inherent limitation of
> digital data representation of a sine wave.  The phase quantization can
> be completely eliminated by using only integer ratios between the
> reference clock frequency and the synthesized frequency.  Amplitude
> quantization can not be eliminated and ultimately is imposed by the
> resolution of the DAC.
>
> I designed a DDS a couple of years ago and used a reasonable size LUT
> with linear interpolation.  I think the ultimate sine values were
> accurate to about 20 or maybe 22 bits.  But that was all overkill.  Even
> though I had 24 bit DACs the SNR and SINAD were in the 90s and 100s of
> dB.  At least I was confident it wasn't the digital stuff that limited
> the result.
>
The time-nuts post by Gerhard seemed to say that the very low frequency 
instability is due to the very long period of the actual waveform.  If 
the phase increment M and 2**N are relatively prime, the actual period 
of the output waveform is M * 2**N clocks.

The reference oscillator is pretty important when you get down to that 
level.

Cheers

Phil Hobbs

-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

On Tue, 09 Dec 2014 10:16:07 -0500, Phil Hobbs
<hobbs@electrooptical.net> wrote:

>On 12/9/2014 8:36 AM, Piotr Wyderski wrote:
>> Phil Hobbs wrote:
>>
>>> Because the signal coming back is at VHF, and using nulling eliminates
>>> the need for 2D calibration, as I said.  A DDS is less complicated to
>>> use than a 200 MHz ADC, for sure, and it saves me a boatload of Mini
>>> Circuits stuff getting the signal down to baseband, and several
>>> expensive and phase-distorting filters getting rid of all the attendant
>>> spurs.
>>
>> Just a final remark to close the discussion about this approach:
>> undersampling?
>>
>>      Best regards, Piotr
>>
>Nope, won't work.  The required waveform accuracy to reach 14 bits of 
>amplitude and phase is very difficult to attain, and requires a gigantic 
>2-D calibration to fix.  That's the whole basis for using nulling.
>
>What I'm planning to do is to put both the MPD-1 and ECLips Lite D-flops 
>on the board, and try both.  I'm too chicken that the strobed comparator 
>is going to oscillate fiercely.

If you essentially AGC ahead of the flop, and get the common-mode
voltage right, the analog zero-crossing should be pretty accurate. But
the comparator would obviously be more precise.

The ADCMP ECL comparators have modest gain and nice diff outputs, so
they behave better than single-ended bipolar ones, especially with a
decent-amplitude sinewave or ramp input.


-- 

John Larkin         Highland Technology, Inc
picosecond timing   laser drivers and controllers

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

On 12/9/2014 11:14 AM, John Larkin wrote:
> On Tue, 09 Dec 2014 10:16:07 -0500, Phil Hobbs
> <hobbs@electrooptical.net> wrote:
>
>> On 12/9/2014 8:36 AM, Piotr Wyderski wrote:
>>> Phil Hobbs wrote:
>>>
>>>> Because the signal coming back is at VHF, and using nulling eliminates
>>>> the need for 2D calibration, as I said.  A DDS is less complicated to
>>>> use than a 200 MHz ADC, for sure, and it saves me a boatload of Mini
>>>> Circuits stuff getting the signal down to baseband, and several
>>>> expensive and phase-distorting filters getting rid of all the attendant
>>>> spurs.
>>>
>>> Just a final remark to close the discussion about this approach:
>>> undersampling?
>>>
>>>       Best regards, Piotr
>>>
>> Nope, won't work.  The required waveform accuracy to reach 14 bits of
>> amplitude and phase is very difficult to attain, and requires a gigantic
>> 2-D calibration to fix.  That's the whole basis for using nulling.
>>
>> What I'm planning to do is to put both the MPD-1 and ECLips Lite D-flops
>> on the board, and try both.  I'm too chicken that the strobed comparator
>> is going to oscillate fiercely.
>
> If you essentially AGC ahead of the flop, and get the common-mode
> voltage right, the analog zero-crossing should be pretty accurate. But
> the comparator would obviously be more precise.

There's going to be a limiting amp ahead of the phase digitizer, so I 
should be reasonably okay there, I think.
>
> The ADCMP ECL comparators have modest gain and nice diff outputs, so
> they behave better than single-ended bipolar ones, especially with a
> decent-amplitude sinewave or ramp input.

I believe that--I've just never used one, and (due to various 
difficulties with lawyers) the slack in the schedule is almost gone. 
(I'm actually freelancing a bit with this on account of that fact.  If 
the contract never does get signed, I won't be able to bill for this 
bit, but I'm pretty sure it will eventually.)

I might put one of those comparators on as a third pop option, we'll 
see.  Right now I'm trying to figure out what the group delay in the 
ceramic filters is going to do to the settling behaviour, and whether 
500 kHz bandwidth is enough.  There's not a lot of bandwidth to spare 
with that, if I really want 100 ks/s.  Of course the DFF will do the 
phase comparison in one cycle, which helps--I can use the rest of the 
time to let the IF filter settle.

Cheers

Phil Hobbs

-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

On 12/9/2014 10:23 AM, Phil Hobbs wrote:
> On 12/8/2014 8:49 PM, rickman wrote:
>> On 12/8/2014 7:57 PM, Phil Hobbs wrote:
>>> On 12/8/2014 7:10 PM, rickman wrote:
>>>> On 12/8/2014 6:57 PM, Phil Hobbs wrote:
>>>>>
>>>>> If I thought I was always right about everything, I wouldn't need to
>>>>> talk to anybody. ;)
>>>>
>>>> Lol, yeah.  That's a large part of why I'm here, to learn something in
>>>> the areas I know less about, like most things analog.  Joerg helped
>>>> me a
>>>> lot a couple of weeks ago to learn about the Miller effect and cascode
>>>> circuits.
>>>>
>>>> Have you figured out what people are referring to when they talk about
>>>> the "phase jump" as the accumulator wraps around?  I'm thinking they
>>>> are
>>>> talking about the remainder that results from the non-integral ratio of
>>>> the step size and modulus.  It's not really a "jump", but I can see
>>>> someone referring to it that way in a conversation.
>>>
>>> It seems like the issue is that for many choices of the phase increment,
>>> there's a spur very close to the carrier, associated with the actual
>>> periodicity of the waveform.  With an N-bit accumulator, it's quite
>>> possible for this to be many times longer than 2**N clock cycles, i.e.
>>> far too long to be visible on frequency-domain instruments such as
>>> spectrum analyzers, and long enough to be surprising to even fairly
>>> sophisticated users.
>>
>> Yes, but a spur would not be described as a "phase jump" on "rollover".
>>   Do you think this is what they are talking about?  That would be so
>> far removed from what *is* happening that it's hard to imagine.
>>
>>
>>>> I find it funny that some don't seem to really understand how a DDS
>>>> works.  Joe Gwinn seems to think there is something different about the
>>>> way Timing Solutions implemented a non-DDS so it didn't have spurs.
>>>> "The
>>>> actual frequency is tweaked such that there is no glitch when the
>>>> memory
>>>> rolls over."  I believe all they did was use the equivalent of a DDS
>>>> circuit with limitations so there was no remainder.   I expect they
>>>> incremented the phase by 1 and could only generate outputs that were
>>>> integer ratios to the reference clock.
>>>
>>> The paper referenced upthread that used (instead of a sine LUT) a
>>> two-turn CORDIC algorithm with AGC to generate the output is a pretty
>>> good read.
>>
>> I didn't dig into all the papers people referenced.  I looked at some
>> and didn't find much to explain what they were talking about.  What Joe
>> described was a simple lookup table with sine values in it which is how
>> a DDS works.  There are two forms of spurs from digital implementations.
>>   One is from phase quantization and the other is from amplitude
>> quantization.  Then the DAC has its own type of distortion which can
>> also produce spurs but are not directly related to the fact that the
>> data is digital.  The other two types are an inherent limitation of
>> digital data representation of a sine wave.  The phase quantization can
>> be completely eliminated by using only integer ratios between the
>> reference clock frequency and the synthesized frequency.  Amplitude
>> quantization can not be eliminated and ultimately is imposed by the
>> resolution of the DAC.
>>
>> I designed a DDS a couple of years ago and used a reasonable size LUT
>> with linear interpolation.  I think the ultimate sine values were
>> accurate to about 20 or maybe 22 bits.  But that was all overkill.  Even
>> though I had 24 bit DACs the SNR and SINAD were in the 90s and 100s of
>> dB.  At least I was confident it wasn't the digital stuff that limited
>> the result.
>>
> The time-nuts post by Gerhard seemed to say that the very low frequency
> instability is due to the very long period of the actual waveform.  If
> the phase increment M and 2**N are relatively prime, the actual period
> of the output waveform is M * 2**N clocks.

I'm not clear on this.  As long as there is no truncated bits in the 
phase accumulator, there is no "instability", all the phase values are 
exact.

If you are working in the digital domain, there will be no noise or 
distortion to the signal other than the limited amplitude resolution 
which can be reduced as much as required.  If you are converting to 
analog you are only limited by your DAC and anti-alias filter.


> The reference oscillator is pretty important when you get down to that
> level.

The reference oscillator is *always* important, Fout = Fclock * N/M

-- 

Rick

On 12/09/2014 12:17 PM, rickman wrote:
> On 12/9/2014 10:23 AM, Phil Hobbs wrote:
>> On 12/8/2014 8:49 PM, rickman wrote:
>>> On 12/8/2014 7:57 PM, Phil Hobbs wrote:
>>>> On 12/8/2014 7:10 PM, rickman wrote:
>>>>> On 12/8/2014 6:57 PM, Phil Hobbs wrote:
>>>>>>
>>>>>> If I thought I was always right about everything, I wouldn't need to
>>>>>> talk to anybody. ;)
>>>>>
>>>>> Lol, yeah.  That's a large part of why I'm here, to learn something in
>>>>> the areas I know less about, like most things analog.  Joerg helped
>>>>> me a
>>>>> lot a couple of weeks ago to learn about the Miller effect and cascode
>>>>> circuits.
>>>>>
>>>>> Have you figured out what people are referring to when they talk about
>>>>> the "phase jump" as the accumulator wraps around?  I'm thinking they
>>>>> are
>>>>> talking about the remainder that results from the non-integral
>>>>> ratio of
>>>>> the step size and modulus.  It's not really a "jump", but I can see
>>>>> someone referring to it that way in a conversation.
>>>>
>>>> It seems like the issue is that for many choices of the phase
>>>> increment,
>>>> there's a spur very close to the carrier, associated with the actual
>>>> periodicity of the waveform.  With an N-bit accumulator, it's quite
>>>> possible for this to be many times longer than 2**N clock cycles, i.e.
>>>> far too long to be visible on frequency-domain instruments such as
>>>> spectrum analyzers, and long enough to be surprising to even fairly
>>>> sophisticated users.
>>>
>>> Yes, but a spur would not be described as a "phase jump" on "rollover".
>>>   Do you think this is what they are talking about?  That would be so
>>> far removed from what *is* happening that it's hard to imagine.
>>>
>>>
>>>>> I find it funny that some don't seem to really understand how a DDS
>>>>> works.  Joe Gwinn seems to think there is something different about
>>>>> the
>>>>> way Timing Solutions implemented a non-DDS so it didn't have spurs.
>>>>> "The
>>>>> actual frequency is tweaked such that there is no glitch when the
>>>>> memory
>>>>> rolls over."  I believe all they did was use the equivalent of a DDS
>>>>> circuit with limitations so there was no remainder.   I expect they
>>>>> incremented the phase by 1 and could only generate outputs that were
>>>>> integer ratios to the reference clock.
>>>>
>>>> The paper referenced upthread that used (instead of a sine LUT) a
>>>> two-turn CORDIC algorithm with AGC to generate the output is a pretty
>>>> good read.
>>>
>>> I didn't dig into all the papers people referenced.  I looked at some
>>> and didn't find much to explain what they were talking about.  What Joe
>>> described was a simple lookup table with sine values in it which is how
>>> a DDS works.  There are two forms of spurs from digital implementations.
>>>   One is from phase quantization and the other is from amplitude
>>> quantization.  Then the DAC has its own type of distortion which can
>>> also produce spurs but are not directly related to the fact that the
>>> data is digital.  The other two types are an inherent limitation of
>>> digital data representation of a sine wave.  The phase quantization can
>>> be completely eliminated by using only integer ratios between the
>>> reference clock frequency and the synthesized frequency.  Amplitude
>>> quantization can not be eliminated and ultimately is imposed by the
>>> resolution of the DAC.
>>>
>>> I designed a DDS a couple of years ago and used a reasonable size LUT
>>> with linear interpolation.  I think the ultimate sine values were
>>> accurate to about 20 or maybe 22 bits.  But that was all overkill.  Even
>>> though I had 24 bit DACs the SNR and SINAD were in the 90s and 100s of
>>> dB.  At least I was confident it wasn't the digital stuff that limited
>>> the result.
>>>
>> The time-nuts post by Gerhard seemed to say that the very low frequency
>> instability is due to the very long period of the actual waveform.  If
>> the phase increment M and 2**N are relatively prime, the actual period
>> of the output waveform is M * 2**N clocks.
>
> I'm not clear on this.  As long as there is no truncated bits in the
> phase accumulator, there is no "instability", all the phase values are
> exact.
>
> If you are working in the digital domain, there will be no noise or
> distortion to the signal other than the limited amplitude resolution
> which can be reduced as much as required.  If you are converting to
> analog you are only limited by your DAC and anti-alias filter.

It was an analogue issue, AIUI.  For a general choice of phase increment 
M, the nominal period of the output is 2**N/M, whereas the real period 
(where the DAC values all repeat) is the LCM of M and 2**N.  That can be 
as much as M**2 times longer, and give rise to small phase artifacts 
that the time-nuts folks care about a lot.

Cheers

Phil Hobbs


-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

In article <m65m7a$da2$1@dont-email.me>, rickman <gnuarm@gmail.com>
wrote:

> On 12/8/2014 8:50 PM, Joe Gwinn wrote:
> >
> > I did find the Timing Solutions patent numbers from back in the day.
> > There may be more patents.  Search on the inventor names, and the
> > "referenced by" section in Google Patents and the US Patent Office.
> > Stein pat5315566, Stein pat5155695, Stein pat5128909, Solbrig (Phase
> > Det) pat7227346, Solbrig (DDS) pat7436166, pat7511469, pat6194918, and
> > pat6172533.
> >
> > Rickman - see Solbrig (DDS) pat7436166.
> 
> The Solbrig patent includes a way of designing a DDS (they even call it 
> a DDS) that uses a table of variable size.  But they are still limited 
> to the frequencies they can generate.  They can only produce frequencies 
> that are rationally related to the reference clock frequency.

Yes, they call it a DDS, and it does implement rational ratios, but it
lacks a phase accumulator and clock-driven adder incrementing the
accumulator by the value of the tuning word, et al.  Solbrig uses a
very different approach, one that solves a host of problems.


> The point is that the spurs that were eliminated are not *inherent* in 
> DDS designs.  They arise from trying to generated output frequencies 
> that are not related to the reference clock.

True, but there is more to it than that.

By varying the number of waveform samples and the time increment, one
can get just as close to a specified frequency as a traditional DDS,
without the many imperfections.  Which is why it was worth patenting,
and why the Patent Office saw it that way.


> You never did explain what you meant by the "phase bumps".

Think of it as a retrace, because that's what it looked like.  The root
cause was that the phase truncation error grew linearly until the
48-bit phase accumulator overflowed, whereupon the apparent phase error
abruptly went to the other extreme, and resumed creeping up, time after
time.

This effect is almost impossible to see directly unless one is
comparing very stable signal sources.

Joe Gwinn

On Tue, 09 Dec 2014 19:26:16 -0500, Joe Gwinn <joegwinn@comcast.net>
wrote:

>In article <m65m7a$da2$1@dont-email.me>, rickman <gnuarm@gmail.com>
>wrote:
>
>> On 12/8/2014 8:50 PM, Joe Gwinn wrote:
>> >
>> > I did find the Timing Solutions patent numbers from back in the day.
>> > There may be more patents.  Search on the inventor names, and the
>> > "referenced by" section in Google Patents and the US Patent Office.
>> > Stein pat5315566, Stein pat5155695, Stein pat5128909, Solbrig (Phase
>> > Det) pat7227346, Solbrig (DDS) pat7436166, pat7511469, pat6194918, =
and
>> > pat6172533.
>> >
>> > Rickman - see Solbrig (DDS) pat7436166.
>>=20
>> The Solbrig patent includes a way of designing a DDS (they even call =
it=20
>> a DDS) that uses a table of variable size.  But they are still limited=
=20
>> to the frequencies they can generate.  They can only produce =
frequencies=20
>> that are rationally related to the reference clock frequency.
>
>Yes, they call it a DDS, and it does implement rational ratios, but it
>lacks a phase accumulator and clock-driven adder incrementing the
>accumulator by the value of the tuning word, et al.  Solbrig uses a
>very different approach, one that solves a host of problems.
>
>
>> The point is that the spurs that were eliminated are not *inherent* in=
=20
>> DDS designs.  They arise from trying to generated output frequencies=20
>> that are not related to the reference clock.
>
>True, but there is more to it than that.
>
>By varying the number of waveform samples and the time increment, one
>can get just as close to a specified frequency as a traditional DDS,
>without the many imperfections.  Which is why it was worth patenting,
>and why the Patent Office saw it that way.
>
>
>> You never did explain what you meant by the "phase bumps".
>
>Think of it as a retrace, because that's what it looked like.  The root
>cause was that the phase truncation error grew linearly until the
>48-bit phase accumulator overflowed, whereupon the apparent phase error
>abruptly went to the other extreme, and resumed creeping up, time after
>time.
>
>This effect is almost impossible to see directly unless one is
>comparing very stable signal sources.
>
>Joe Gwinn


I think i finally see what you are talking about.  It is a phase error
created by the artifacts of the true desired frequency not being the same
as the frequency created with nearest phase increment value.  Thus phase
drift/slide.  In this case, some modulation of the phase word can help
some by reducing the final amplitude of the phase error.

?-)
=20

On 12/9/2014 3:34 PM, Phil Hobbs wrote:
> On 12/09/2014 12:17 PM, rickman wrote:
>> On 12/9/2014 10:23 AM, Phil Hobbs wrote:
>>> On 12/8/2014 8:49 PM, rickman wrote:
>>>> On 12/8/2014 7:57 PM, Phil Hobbs wrote:
>>>>> On 12/8/2014 7:10 PM, rickman wrote:
>>>>>> On 12/8/2014 6:57 PM, Phil Hobbs wrote:
>>>>>>>
>>>>>>> If I thought I was always right about everything, I wouldn't need to
>>>>>>> talk to anybody. ;)
>>>>>>
>>>>>> Lol, yeah.  That's a large part of why I'm here, to learn
>>>>>> something in
>>>>>> the areas I know less about, like most things analog.  Joerg helped
>>>>>> me a
>>>>>> lot a couple of weeks ago to learn about the Miller effect and
>>>>>> cascode
>>>>>> circuits.
>>>>>>
>>>>>> Have you figured out what people are referring to when they talk
>>>>>> about
>>>>>> the "phase jump" as the accumulator wraps around?  I'm thinking they
>>>>>> are
>>>>>> talking about the remainder that results from the non-integral
>>>>>> ratio of
>>>>>> the step size and modulus.  It's not really a "jump", but I can see
>>>>>> someone referring to it that way in a conversation.
>>>>>
>>>>> It seems like the issue is that for many choices of the phase
>>>>> increment,
>>>>> there's a spur very close to the carrier, associated with the actual
>>>>> periodicity of the waveform.  With an N-bit accumulator, it's quite
>>>>> possible for this to be many times longer than 2**N clock cycles, i.e.
>>>>> far too long to be visible on frequency-domain instruments such as
>>>>> spectrum analyzers, and long enough to be surprising to even fairly
>>>>> sophisticated users.
>>>>
>>>> Yes, but a spur would not be described as a "phase jump" on "rollover".
>>>>   Do you think this is what they are talking about?  That would be so
>>>> far removed from what *is* happening that it's hard to imagine.
>>>>
>>>>
>>>>>> I find it funny that some don't seem to really understand how a DDS
>>>>>> works.  Joe Gwinn seems to think there is something different about
>>>>>> the
>>>>>> way Timing Solutions implemented a non-DDS so it didn't have spurs.
>>>>>> "The
>>>>>> actual frequency is tweaked such that there is no glitch when the
>>>>>> memory
>>>>>> rolls over."  I believe all they did was use the equivalent of a DDS
>>>>>> circuit with limitations so there was no remainder.   I expect they
>>>>>> incremented the phase by 1 and could only generate outputs that were
>>>>>> integer ratios to the reference clock.
>>>>>
>>>>> The paper referenced upthread that used (instead of a sine LUT) a
>>>>> two-turn CORDIC algorithm with AGC to generate the output is a pretty
>>>>> good read.
>>>>
>>>> I didn't dig into all the papers people referenced.  I looked at some
>>>> and didn't find much to explain what they were talking about.  What Joe
>>>> described was a simple lookup table with sine values in it which is how
>>>> a DDS works.  There are two forms of spurs from digital
>>>> implementations.
>>>>   One is from phase quantization and the other is from amplitude
>>>> quantization.  Then the DAC has its own type of distortion which can
>>>> also produce spurs but are not directly related to the fact that the
>>>> data is digital.  The other two types are an inherent limitation of
>>>> digital data representation of a sine wave.  The phase quantization can
>>>> be completely eliminated by using only integer ratios between the
>>>> reference clock frequency and the synthesized frequency.  Amplitude
>>>> quantization can not be eliminated and ultimately is imposed by the
>>>> resolution of the DAC.
>>>>
>>>> I designed a DDS a couple of years ago and used a reasonable size LUT
>>>> with linear interpolation.  I think the ultimate sine values were
>>>> accurate to about 20 or maybe 22 bits.  But that was all overkill.
>>>> Even
>>>> though I had 24 bit DACs the SNR and SINAD were in the 90s and 100s of
>>>> dB.  At least I was confident it wasn't the digital stuff that limited
>>>> the result.
>>>>
>>> The time-nuts post by Gerhard seemed to say that the very low frequency
>>> instability is due to the very long period of the actual waveform.  If
>>> the phase increment M and 2**N are relatively prime, the actual period
>>> of the output waveform is M * 2**N clocks.
>>
>> I'm not clear on this.  As long as there is no truncated bits in the
>> phase accumulator, there is no "instability", all the phase values are
>> exact.
>>
>> If you are working in the digital domain, there will be no noise or
>> distortion to the signal other than the limited amplitude resolution
>> which can be reduced as much as required.  If you are converting to
>> analog you are only limited by your DAC and anti-alias filter.
>
> It was an analogue issue, AIUI.  For a general choice of phase increment
> M, the nominal period of the output is 2**N/M, whereas the real period
> (where the DAC values all repeat) is the LCM of M and 2**N.  That can be
> as much as M**2 times longer, and give rise to small phase artifacts
> that the time-nuts folks care about a lot.

I'm a bit unclear.  If it is an analog issue, it would have nothing to 
do with the digital portion and in particular the ratios of modulus and 
step size.

There is some misunderstanding.  The issue you are raising, the lack of 
exact digital values repeating on each Fout cycle, will *not* create 
spurs other than the other mechanisms as I have mentioned which include 
amplitude quantization and analog effects.  If it does I would like to 
know the mechanism.

-- 

Rick

On 12/9/2014 7:26 PM, Joe Gwinn wrote:
> In article <m65m7a$da2$1@dont-email.me>, rickman <gnuarm@gmail.com>
> wrote:
>
>> On 12/8/2014 8:50 PM, Joe Gwinn wrote:
>>>
>>> I did find the Timing Solutions patent numbers from back in the day.
>>> There may be more patents.  Search on the inventor names, and the
>>> "referenced by" section in Google Patents and the US Patent Office.
>>> Stein pat5315566, Stein pat5155695, Stein pat5128909, Solbrig (Phase
>>> Det) pat7227346, Solbrig (DDS) pat7436166, pat7511469, pat6194918, and
>>> pat6172533.
>>>
>>> Rickman - see Solbrig (DDS) pat7436166.
>>
>> The Solbrig patent includes a way of designing a DDS (they even call it
>> a DDS) that uses a table of variable size.  But they are still limited
>> to the frequencies they can generate.  They can only produce frequencies
>> that are rationally related to the reference clock frequency.
>
> Yes, they call it a DDS, and it does implement rational ratios, but it
> lacks a phase accumulator and clock-driven adder incrementing the
> accumulator by the value of the tuning word, et al.  Solbrig uses a
> very different approach, one that solves a host of problems.

The "accumulator" is the RAM index counter which includes the adder. 
The *only* difference is that the "tuning word" which I call the step 
size is fixed at 1.

The only thing that Solbrig does that "solves a host of problems" of the 
DDS is to use it in the way that does not create spurs from quantization 
(or call it truncation) of the phase.

I'm sorry, but he is using a DDS that is just like everyone else's DDS 
except less.  He has limited the ratios of input and output clocks to 
integer ratios which does not truncate the phase and so does not add 
phase jitter which creates spurs.


>> The point is that the spurs that were eliminated are not *inherent* in
>> DDS designs.  They arise from trying to generated output frequencies
>> that are not related to the reference clock.
>
> True, but there is more to it than that.
>
> By varying the number of waveform samples and the time increment, one
> can get just as close to a specified frequency as a traditional DDS,
> without the many imperfections.  Which is why it was worth patenting,
> and why the Patent Office saw it that way.

I don't understand what the patent office has to do with it.

Here is what you said that started our conversation...

> The way Symmetricom (actually Timing Solutions, acquired by
> Symmetricom) solved the whole DDS spur and bump problem is by computing
> the sine wave amplitudes directly (no DDS chip) and loading it into a
> clock-indexed RAM unit.  These numbers are fed directly to a digital
> multiplier (replacing an analog mixer). The actual frequency is tweaked
> such that there is no glitch when the memory rolls over.

In another post you said...

> Timing Solutions was not trying to implement a DDS.

Now you provide a patent that shows them using a DDS in a way that 
restricts the output frequencies to specific ratios of the input 
frequency.

So here is my beef.  First, you used the term, "bump problem" without 
explaining what that is or where you heard about it.  I can't find 
anything that does explain it.  What problem are you talking about?

The spur problem is solved by using the DDS in a way that does not 
create spurs.  As I have stated in many posts that is not hard to do. 
The Timing Solutions... solution is to reinvent the DDS with the sine 
table values set at the time you initialize the device rather than 
making them fixed as in a ROM.  I can't say if that was the first time 
anyone had done that or not, although I'd be surprised if it were since 
DDS have been done in FPGAs many, many times before 2005 and that means 
they were always in a RAM table.

But that is a red herring.  They didn't "solve" the DDS spur problem. 
They just used the DDS in a way that restricted the possible output 
frequencies to ones that won't create spurs from truncating the phase. 
They can *only* generate frequencies that are rationally related to the 
input frequency.


>> You never did explain what you meant by the "phase bumps".
>
> Think of it as a retrace, because that's what it looked like.  The root
> cause was that the phase truncation error grew linearly until the
> 48-bit phase accumulator overflowed, whereupon the apparent phase error
> abruptly went to the other extreme, and resumed creeping up, time after
> time.
>
> This effect is almost impossible to see directly unless one is
> comparing very stable signal sources.

It is very easy to see although I don't think you describe it correctly. 
  It has *nothing* to do with the phase accumulator rolling over unless 
that was a coincidence.  It is caused by the remainder growing until it 
adds 1 to the portion of the phase accumulator that does not get 
truncated.  Perhaps someone was considering the phase accumulator to be 
two parts, the part that is truncated and the part that is not 
truncated.  Then they could say the truncated bits "roll over" and carry 
into the non-truncated portion.

You can see this yourself very easily.  Use a spread sheet and create a 
column of "phase accumulator" values where each one is incremented from 
the previous one by some value in another cell.  In the next column do a 
truncated division to get the upper bits which would be used to drive 
the sine table.  In the third column subtract the upper bits from the 
full accumulator and you will see the "remainder" which is the portion 
of the phase accumulator you are talking about that creates the phase 
error.

If you graph these lower bits of the phase register vs the full phase 
value you will get the irregular sawtooth you seem to be talking about. 
  This is the phase error that can be seen when using a DDS.  I know 
because I have done this when designing a DDS.

This phase error is *not* inherent in the operation of a DDS.  If these 
bits in the phase step word are set to zero there will be no sawtooth no 
phase error, no spurs.  If you design your DDS without truncated bits in 
the accumulator, then you won't be able to have phase errors.  That is 
what Timing Solutions did.

-- 

Rick