DDS wisdom

On 12/8/2014 1:44 PM, Phil Hobbs wrote:
> On 12/7/2014 12:00 AM, rickman wrote:
>>
>> I am trying to explain to you that zeros in the lower bits of the phase
>> step is not the same as a zero value in the truncated bits of the step
>> size.  Lets say there are no truncated bits in the phase step or
>> accumulator just to make it easier to talk about.  You are saying that
>> anything you then program into the phase step word will give you a
>> waveform that is exactly the same on each cycle of that waveform.  This
>> is not correct.  Easy example, 4 bit accumulator with a phase step of 3.
>>   Modulus of 16 gives cycles of 0,3,6,9,12,15 - 2,5,8,11,14 -
>> 1,4,7,10,13.  Notice not only  are the cycles not the same, they aren't
>> even the same number of samples.
>>
>> To have each cycle of the output be identical the modulus has to be an
>> integer multiple of the step size.  If you have a remainder when
>> dividing the modulus by the step size, this remainder will be an offset
>> at the start of the next cycle which means it won't be the same as the
>> first cycle.  With a modulus of 2^n that requires the step size to be
>> 2^m.  That is not the same requirement than having zero value in the
>> truncated bits of the step size.
>>
>> In fact, having zero in the truncated portion of the step size is not
>> even a requirement as long as the ratio of the modulus to the step size
>> is an integer.  Again, with a modulus of 2^N, if the msb of the
>> truncated portion of the step size is 1 and the rest of the word is
>> zeros the Fout cycle will repeat exactly each cycle of Fout.  As I said
>> before, you will get larger spurs, but they will all be clock related
>> spurs exactly the same as having no truncated bits with a clock rate
>> half the actual rate.  Easy example - Modulus of 16, 3 bits output, 1
>> truncated bit, step value of 1 - 0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7 and
>> repeat.
>>
>> So we are *not* in violent agreement... and it is you who hasn't
>> noticed... yet.  I hope this covers it.
>>
>
> Quite right, thanks.

That's something you don't see in s.e.d every day, a polite response... 
  lol

BTW, I see my opening sentence was double talk.  I think I  meant to say 
"zeros in the lower bits of the phase step is not the same as the 
modulus being a multiple of the phase step."

Anyway, I'm glad we found common ground.

Now if I could get some of the other posters here to tell me what they 
mean by the mythical "phase jump" when the phase accumulator rolls over.

-- 

Rick

On 12/8/2014 5:37 PM, rickman wrote:
> On 12/8/2014 1:44 PM, Phil Hobbs wrote:
>> On 12/7/2014 12:00 AM, rickman wrote:
>>>
>>> I am trying to explain to you that zeros in the lower bits of the phase
>>> step is not the same as a zero value in the truncated bits of the step
>>> size.  Lets say there are no truncated bits in the phase step or
>>> accumulator just to make it easier to talk about.  You are saying that
>>> anything you then program into the phase step word will give you a
>>> waveform that is exactly the same on each cycle of that waveform.  This
>>> is not correct.  Easy example, 4 bit accumulator with a phase step of 3.
>>>   Modulus of 16 gives cycles of 0,3,6,9,12,15 - 2,5,8,11,14 -
>>> 1,4,7,10,13.  Notice not only  are the cycles not the same, they aren't
>>> even the same number of samples.
>>>
>>> To have each cycle of the output be identical the modulus has to be an
>>> integer multiple of the step size.  If you have a remainder when
>>> dividing the modulus by the step size, this remainder will be an offset
>>> at the start of the next cycle which means it won't be the same as the
>>> first cycle.  With a modulus of 2^n that requires the step size to be
>>> 2^m.  That is not the same requirement than having zero value in the
>>> truncated bits of the step size.
>>>
>>> In fact, having zero in the truncated portion of the step size is not
>>> even a requirement as long as the ratio of the modulus to the step size
>>> is an integer.  Again, with a modulus of 2^N, if the msb of the
>>> truncated portion of the step size is 1 and the rest of the word is
>>> zeros the Fout cycle will repeat exactly each cycle of Fout.  As I said
>>> before, you will get larger spurs, but they will all be clock related
>>> spurs exactly the same as having no truncated bits with a clock rate
>>> half the actual rate.  Easy example - Modulus of 16, 3 bits output, 1
>>> truncated bit, step value of 1 - 0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7 and
>>> repeat.
>>>
>>> So we are *not* in violent agreement... and it is you who hasn't
>>> noticed... yet.  I hope this covers it.
>>>
>>
>> Quite right, thanks.
>
> That's something you don't see in s.e.d every day, a polite response...
>   lol
>
> BTW, I see my opening sentence was double talk.  I think I  meant to say
> "zeros in the lower bits of the phase step is not the same as the
> modulus being a multiple of the phase step."
>
> Anyway, I'm glad we found common ground.
>
> Now if I could get some of the other posters here to tell me what they
> mean by the mythical "phase jump" when the phase accumulator rolls over.
>

If I thought I was always right about everything, I wouldn't need to 
talk to anybody. ;)

Cheers

Phil Hobbs

-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

On 12/8/2014 6:57 PM, Phil Hobbs wrote:
>
> If I thought I was always right about everything, I wouldn't need to
> talk to anybody. ;)

Lol, yeah.  That's a large part of why I'm here, to learn something in 
the areas I know less about, like most things analog.  Joerg helped me a 
lot a couple of weeks ago to learn about the Miller effect and cascode 
circuits.

Have you figured out what people are referring to when they talk about 
the "phase jump" as the accumulator wraps around?  I'm thinking they are 
talking about the remainder that results from the non-integral ratio of 
the step size and modulus.  It's not really a "jump", but I can see 
someone referring to it that way in a conversation.

I find it funny that some don't seem to really understand how a DDS 
works.  Joe Gwinn seems to think there is something different about the 
way Timing Solutions implemented a non-DDS so it didn't have spurs. 
"The actual frequency is tweaked such that there is no glitch when the 
memory rolls over."  I believe all they did was use the equivalent of a 
DDS circuit with limitations so there was no remainder.   I expect they 
incremented the phase by 1 and could only generate outputs that were 
integer ratios to the reference clock.

-- 

Rick

On 12/8/2014 7:10 PM, rickman wrote:
> On 12/8/2014 6:57 PM, Phil Hobbs wrote:
>>
>> If I thought I was always right about everything, I wouldn't need to
>> talk to anybody. ;)
>
> Lol, yeah.  That's a large part of why I'm here, to learn something in
> the areas I know less about, like most things analog.  Joerg helped me a
> lot a couple of weeks ago to learn about the Miller effect and cascode
> circuits.
>
> Have you figured out what people are referring to when they talk about
> the "phase jump" as the accumulator wraps around?  I'm thinking they are
> talking about the remainder that results from the non-integral ratio of
> the step size and modulus.  It's not really a "jump", but I can see
> someone referring to it that way in a conversation.

It seems like the issue is that for many choices of the phase increment, 
there's a spur very close to the carrier, associated with the actual 
periodicity of the waveform.  With an N-bit accumulator, it's quite 
possible for this to be many times longer than 2**N clock cycles, i.e. 
far too long to be visible on frequency-domain instruments such as 
spectrum analyzers, and long enough to be surprising to even fairly 
sophisticated users.

>
> I find it funny that some don't seem to really understand how a DDS
> works.  Joe Gwinn seems to think there is something different about the
> way Timing Solutions implemented a non-DDS so it didn't have spurs. "The
> actual frequency is tweaked such that there is no glitch when the memory
> rolls over."  I believe all they did was use the equivalent of a DDS
> circuit with limitations so there was no remainder.   I expect they
> incremented the phase by 1 and could only generate outputs that were
> integer ratios to the reference clock.

The paper referenced upthread that used (instead of a sine LUT) a 
two-turn CORDIC algorithm with AGC to generate the output is a pretty 
good read.

Cheers

Phil Hobbs


-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

On 12/8/2014 7:57 PM, Phil Hobbs wrote:
> On 12/8/2014 7:10 PM, rickman wrote:
>> On 12/8/2014 6:57 PM, Phil Hobbs wrote:
>>>
>>> If I thought I was always right about everything, I wouldn't need to
>>> talk to anybody. ;)
>>
>> Lol, yeah.  That's a large part of why I'm here, to learn something in
>> the areas I know less about, like most things analog.  Joerg helped me a
>> lot a couple of weeks ago to learn about the Miller effect and cascode
>> circuits.
>>
>> Have you figured out what people are referring to when they talk about
>> the "phase jump" as the accumulator wraps around?  I'm thinking they are
>> talking about the remainder that results from the non-integral ratio of
>> the step size and modulus.  It's not really a "jump", but I can see
>> someone referring to it that way in a conversation.
>
> It seems like the issue is that for many choices of the phase increment,
> there's a spur very close to the carrier, associated with the actual
> periodicity of the waveform.  With an N-bit accumulator, it's quite
> possible for this to be many times longer than 2**N clock cycles, i.e.
> far too long to be visible on frequency-domain instruments such as
> spectrum analyzers, and long enough to be surprising to even fairly
> sophisticated users.

Yes, but a spur would not be described as a "phase jump" on "rollover". 
  Do you think this is what they are talking about?  That would be so 
far removed from what *is* happening that it's hard to imagine.


>> I find it funny that some don't seem to really understand how a DDS
>> works.  Joe Gwinn seems to think there is something different about the
>> way Timing Solutions implemented a non-DDS so it didn't have spurs. "The
>> actual frequency is tweaked such that there is no glitch when the memory
>> rolls over."  I believe all they did was use the equivalent of a DDS
>> circuit with limitations so there was no remainder.   I expect they
>> incremented the phase by 1 and could only generate outputs that were
>> integer ratios to the reference clock.
>
> The paper referenced upthread that used (instead of a sine LUT) a
> two-turn CORDIC algorithm with AGC to generate the output is a pretty
> good read.

I didn't dig into all the papers people referenced.  I looked at some 
and didn't find much to explain what they were talking about.  What Joe 
described was a simple lookup table with sine values in it which is how 
a DDS works.  There are two forms of spurs from digital implementations. 
  One is from phase quantization and the other is from amplitude 
quantization.  Then the DAC has its own type of distortion which can 
also produce spurs but are not directly related to the fact that the 
data is digital.  The other two types are an inherent limitation of 
digital data representation of a sine wave.  The phase quantization can 
be completely eliminated by using only integer ratios between the 
reference clock frequency and the synthesized frequency.  Amplitude 
quantization can not be eliminated and ultimately is imposed by the 
resolution of the DAC.

I designed a DDS a couple of years ago and used a reasonable size LUT 
with linear interpolation.  I think the ultimate sine values were 
accurate to about 20 or maybe 22 bits.  But that was all overkill.  Even 
though I had 24 bit DACs the SNR and SINAD were in the 90s and 100s of 
dB.  At least I was confident it wasn't the digital stuff that limited 
the result.

-- 

Rick

In article <XnsA3FD2DF90694Fidtokenpost@69.16.179.22>, Tom Swift
<spam@me.com> wrote:

> Joe Gwinn <joegwinn@comcast.net> wrote:
> 
> > In article <XnsA3FBE4901679Fidtokenpost@69.16.179.23>, Tom Swift
> > <spam@me.com> wrote:
> 
> >> Theoretically, you can build one from information in the user
> >> manual:
> 
> >> <http://www.miles.io/TimePod_5330A_user_manual.pdf>
> 
> > The manual has no real principles of operation discussion, but it
> > does appear to be the RF front end of the Timing Solutions 5110
> > (40 MHz top end) not the 5115 (400 MHz?).
> 
> Yes. That makes it useless for 100MHz or 1GHz and above. For this
> reason, I have decided to go the E5052A route with quadrature mixers
> and cross-correlation. This requires local oscillators as good as
> what you are trying to measure, so I am very interested in very low
> phase noise synthesizers.
> 
> >> With all these heavyweights and specialized equipment in the
> >> frequency and time field, I am extremely impressed that you
> >> managed to find the problem with no outside support.
> >> Congratulations!
> 
> > Well, thanks, but I didn't come to the issue without any related
> > background in Time. I'm a Time-Nut lurker as well.
> 
> > For the record, I was getting plots like those published by
> > Ulrich, and the regular sawtooth error was a dead giveaway, and a
> > back-of-the-enevelop calculation showed that the sawtooth period
> > was at the rollover rate.
> 
> Your employer is very fortunate to have you. Anyone else would have
> been totally baffled.

Well, the vendor's engineers were baffled to be sure.  They knew about
time, but not so much DDS theory.


> > I recall having that problem when I was looking, circa 2007 when
> > Symmetricom had just purchased TS, and I borrowed and tested their
> > early versions of the 5110. Many of the TS patents were in the
> > name of their founder, Samuel Stein.

On reflection, I think it was more like 2008 or 2009 that I was doing
this, because Timing Solutions was already a part of Symmetricom.


> > Anyway, I'll dig the patent numbers out. I bet there are more
> > patents now.
> 
> Actually, I'm more interested in Holzworth, but I'll be very
> interested in anything you come up with. In the meantime, I'll start
> searching and see if I can find anything useful.

I did find the Timing Solutions patent numbers from back in the day. 
There may be more patents.  Search on the inventor names, and the
"referenced by" section in Google Patents and the US Patent Office.  
Stein pat5315566, Stein pat5155695, Stein pat5128909, Solbrig (Phase
Det) pat7227346, Solbrig (DDS) pat7436166, pat7511469, pat6194918, and
pat6172533.

Rickman - see Solbrig (DDS) pat7436166.


> >> Also, if you happen to come across anything from Holzworth
> >> Instrumentation in Boulder, please let me know. They have a
> >> propretary synthesizer technique that doesn't use plls and
> >> apparently no DDS. They can switch frequencies anywhere from
> >> anywhere to in 50us, and nearby frequencies in 5us. It is driving
> >> me mad to figure out how they do it.
> 
> >> There is apparently nothing in the literature or anything on the
> >> web that talks about anything that can do that.
> 
> > Yeah, I know. Their sales engineers were giving me the
> > I've-got-a-secret routine as well. But the founder (Jason
> > Breitbarth) is the main brain, and as is often the case with small
> > technology companies, the core technology was developed for his
> > PhD thesis, and it's all there:
> 
> > <http://ecee.colorado.edu/microwave/docs/theses/jasonb_phd_thesis.pdf>
> 
> That's a neat trick! I had the privilege of living in Boulder for a
> number of years, and I can see that someone who lives there would be
> reluctant to move. After they get their degree, they'd rather start
> a company if they have any brains. So all you need to do is search
> Boulder University for their thesis. Brilliant!

So, you still live in Boulder?


> I read through the entire thesis but it's basically a 4.6GHZ coaxial
> resonator oscillator and nonlinear transmission lines using a YIG
> filter. There's nothing on wideband synthesizers. Multiplying up
> from 100MHz would create sidebands that would be very hard to
> remove, especially for a variable frequency system.

Hmm.  The mapping from the various boasts about Holtzworth's products
and sales pitches to the thesis seemed pretty clear to me.  If I
recall, he was using a vernier set of frequency combs, arranged such
that it was easy to lock a PLL onto a specified multiple.  After that,
one used mixers.

Joe Gwinn

On 12/8/2014 8:50 PM, Joe Gwinn wrote:
>
> I did find the Timing Solutions patent numbers from back in the day.
> There may be more patents.  Search on the inventor names, and the
> "referenced by" section in Google Patents and the US Patent Office.
> Stein pat5315566, Stein pat5155695, Stein pat5128909, Solbrig (Phase
> Det) pat7227346, Solbrig (DDS) pat7436166, pat7511469, pat6194918, and
> pat6172533.
>
> Rickman - see Solbrig (DDS) pat7436166.

The Solbrig patent includes a way of designing a DDS (they even call it 
a DDS) that uses a table of variable size.  But they are still limited 
to the frequencies they can generate.  They can only produce frequencies 
that are rationally related to the reference clock frequency.

The point is that the spurs that were eliminated are not *inherent* in 
DDS designs.  They arise from trying to generated output frequencies 
that are not related to the reference clock.

You never did explain what you meant by the "phase bumps".

-- 

Rick

On 12/8/2014 1:44 PM, Phil Hobbs wrote:
> On 12/7/2014 12:00 AM, rickman wrote:
>> On 12/6/2014 4:01 PM, Phil Hobbs wrote:
>>> On 12/5/2014 11:24 PM, rickman wrote:
>>>> On 12/5/2014 10:19 PM, John Larkin wrote:
>>>>> On Fri, 05 Dec 2014 21:29:46 -0500, Phil Hobbs
>>>>> <hobbs@electrooptical.net> wrote:
>>>>>
>>>>>> On 12/5/2014 7:44 PM, Joe Gwinn wrote:
>>>>>>> In article <5481273A.6010107@electrooptical.net>, Phil Hobbs
>>>>>>> <hobbs@electrooptical.net> wrote:
>>>>>>>
>>>>>>>> On 12/4/2014 7:44 PM, Joe Gwinn wrote:
>>>>>>>>> In article <cYydnTNwFPGvIx3JnZ2dnUU7-W-dnZ2d@supernews.com>, Phil
>>>>>>>>> Hobbs
>>>>>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>>>>>>
>>>>>>>>>> Hi, all,
>>>>>>>>>>
>>>>>>>>>> I have a gig coming in that will have me revisiting my thesis
>>>>>>>>>> research
>>>>>>>>>> from nearly 30 years ago, on interferometric laser microscopes.
>>>>>>>>>> (Fun.)
>>>>>>>>>>
>>>>>>>>>> Back in the day, I made a nulling-type phase digitizer at 60
>>>>>>>>>> MHz by
>>>>>>>>>> driving a phase shifter with a 12-bit DAC (AD-DAC80), and
>>>>>>>>>> wrapping a
>>>>>>>>>> 13-bit successive approximation loop round it (AM2904 with an
>>>>>>>>>> extra
>>>>>>>>>> flipflop).  With quite a lot of calibration, that got me a
>>>>>>>>>> 13-bit, 2-pi,
>>>>>>>>>> 50 ks/s phase measurement that I was pretty happy with.  (The
>>>>>>>>>> extra bit
>>>>>>>>>> came from deciding which null to head for, which is why I needed
>>>>>>>>>> the
>>>>>>>>>> extra FF.)  It was all interfaced to an HP 9816 computer via a
>>>>>>>>>> GPIO
>>>>>>>>>> card, and (eventually) worked great.  I published one of my only
>>>>>>>>>> two
>>>>>>>>>> instruments papers on it (this was before I realized the total
>>>>>>>>>> futility
>>>>>>>>>> of almost all instruments papers).
>>>>>>>>>>
>>>>>>>>>> The advantage of nulling detection is that you only need 1-D
>>>>>>>>>> calibration
>>>>>>>>>> tables for phase shift and amplitude, whereas getting that
>>>>>>>>>> sort of
>>>>>>>>>> accuracy with I/Q techniques requires a 2-D calibration table,
>>>>>>>>>> which is
>>>>>>>>>> a gigantic pain.
>>>>>>>>>>
>>>>>>>>>> I need to do this again, 2015 style.  The speed requirements are
>>>>>>>>>> set by
>>>>>>>>>> the acoustic delay in the AO scanner, so 50-100 ks/s is about all
>>>>>>>>>> I can
>>>>>>>>>> use.  Rather than all that squishy analogue stuff, I'm planning
>>>>>>>>>> to do
>>>>>>>>>> the SAR in software and use a pair of AD9951 DDS chips, one to
>>>>>>>>>> generate
>>>>>>>>>> the desired signal and one to be the phase shifted comparison
>>>>>>>>>> signal.
>>>>>>>>>>
>>>>>>>>>> So far so straightforward.
>>>>>>>>>>
>>>>>>>>>> What I'm less sure about is being able to keep the two channels
>>>>>>>>>> sufficiently isolated to be able to maintain 12 or ideally 14
>>>>>>>>>> bits of
>>>>>>>>>> phase accuracy.  Even with a full-scale input, I'll need 85 dB of
>>>>>>>>>> isolation to get 14 bits, and it gets harder with weaker signals.
>>>>>>>>>> (There'll be a DLVA/limiter ahead of the phase detector, which
>>>>>>>>>> will help.)
>>>>>>>>>>
>>>>>>>>>> I've never used DDSes before, and I'd appreciate some wisdom from
>>>>>>>>>> folks
>>>>>>>>>> who have.  How hard is that likely to be, and what should I
>>>>>>>>>> particularly
>>>>>>>>>> watch out for?
>>>>>>>>>
>>>>>>>>> DDSs have a forest of rational-multiple (but not necessarily
>>>>>>>>> harmonic)
>>>>>>>>> spurs, and it can be difficult to get them below -60 dBc unless
>>>>>>>>> you can
>>>>>>>>> place some restrictions on the frequency resolution.
>>>>>>>>
>>>>>>>> I can pick my IF to be anything I like, which I expect will help.
>>>>>>>>>
>>>>>>>>> Also beware phase jumps when the DDS phase wheel rolls over.
>>>>>>>>
>>>>>>>> Could you elaborate a bit?  I thought the whole idea was to keep
>>>>>>>> phase
>>>>>>>> continuity.
>>>>>>>
>>>>>>> Lots of people have elaborated on the point, so I won't recite it.
>>>>>>>
>>>>>>> It's true that choosing tuning words with the lower k (one chooses a
>>>>>>> suitable value such that nothing is truncated in lookup tables) bits
>>>>>>> zero will greatly reduce the number of spurs, and get rid of the
>>>>>>> phase
>>>>>>> bump when the phase wheel rolls over, but there will still be
>>>>>>> lots of
>>>>>>> spurs from the limited width of the lookup tables and DACs.
>>>>>>
>>>>>> If the 'hidden' bits in the phase register are always zero, then the
>>>>>> output of the DAC should be strictly periodic at f_out.  That means
>>>>>> that
>>>>>> all, and I mean *all*, of the artifacts will be harmonics of f_out.
>>>>>> Isn't that so?
>>>>>
>>>>> Sure. Absolutely everything repeats at Fout.
>>>>
>>>> No, that's not correct.  All of the phase words will repeat every cycle
>>>> of Fout only if the modulus is a multiple of the phase step which in
>>>> the
>>>> case of a 2^N modulus means the step size is power of 2 as well.  Or in
>>>> other words, the clock rate is a power of 2 harmonic of Fout or
>>>> octaves.
>>>
>>> How is that different from saying that the hidden bits of the phase
>>> accumulator remain constant?  It seems like we're in violent agreement,
>>> except that you haven't noticed yet. ;)
>>>
>>> If the hidden bits are always zero, then in each cycle, all the DAC
>>> codes repeat,  so the waveform is ideally perfectly periodic.  No?
>>
>> I am trying to explain to you that zeros in the lower bits of the phase
>> step is not the same as a zero value in the truncated bits of the step
>> size.  Lets say there are no truncated bits in the phase step or
>> accumulator just to make it easier to talk about.  You are saying that
>> anything you then program into the phase step word will give you a
>> waveform that is exactly the same on each cycle of that waveform.  This
>> is not correct.  Easy example, 4 bit accumulator with a phase step of 3.
>>   Modulus of 16 gives cycles of 0,3,6,9,12,15 - 2,5,8,11,14 -
>> 1,4,7,10,13.  Notice not only  are the cycles not the same, they aren't
>> even the same number of samples.
>>
>> To have each cycle of the output be identical the modulus has to be an
>> integer multiple of the step size.  If you have a remainder when
>> dividing the modulus by the step size, this remainder will be an offset
>> at the start of the next cycle which means it won't be the same as the
>> first cycle.  With a modulus of 2^n that requires the step size to be
>> 2^m.  That is not the same requirement than having zero value in the
>> truncated bits of the step size.
>>
>> In fact, having zero in the truncated portion of the step size is not
>> even a requirement as long as the ratio of the modulus to the step size
>> is an integer.  Again, with a modulus of 2^N, if the msb of the
>> truncated portion of the step size is 1 and the rest of the word is
>> zeros the Fout cycle will repeat exactly each cycle of Fout.  As I said
>> before, you will get larger spurs, but they will all be clock related
>> spurs exactly the same as having no truncated bits with a clock rate
>> half the actual rate.  Easy example - Modulus of 16, 3 bits output, 1
>> truncated bit, step value of 1 - 0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7 and
>> repeat.
>>
>> So we are *not* in violent agreement... and it is you who hasn't
>> noticed... yet.  I hope this covers it.
>>
>
> Quite right, thanks.

Well, I think I have egg on my face.  All of the above discussion was 
based on two assumptions.  One was that the modulus of the phase 
accumulator was 2^N and the other was that a necessary condition for not 
having phase error generated spurs was that the exact same pattern of 
values be produced on each output cycle.  The first is just the 
assumption we made to ease the math and so is fine as long as we 
remember that was our assumption and then consider the more general case 
as well.  But the second assumption was wrong!

The requirement for producing an sine wave without spurs is to produce 
each sample with no errors.  That does *not* imply that each output 
cycle have the exact same data.  For each output cycle to have the same 
data the modulus has to be an integer multiple of the phase step size. 
But any pattern that does not produce a phase error will produce 
perfectly good sine wave values other than the limitations of the finite 
word width (amplitude errors).

Eliminating spurs caused by phase errors actually requires two things, 
to have integer ratios between the modulus and the step size (not hard 
since they are always integers in digital systems) and that the phase 
never be truncated.  Ah!  That is the one that requires the lower order 
bits of the phase step size to be zeros!!!  So we are back to *your* 
original statement of needing zeros in the truncated portion of the 
phase step size.

I guess we are back to *violent* agreement.

-- 

Rick

Joe Gwinn <joegwinn@comcast.net> wrote:

> In article <XnsA3FD2DF90694Fidtokenpost@69.16.179.22>, Tom Swift
> <spam@me.com> wrote:

>> Your employer is very fortunate to have you. Anyone else would have
>> been totally baffled. 
> 
> Well, the vendor's engineers were baffled to be sure.  They knew about
> time, but not so much DDS theory.
 
> I did find the Timing Solutions patent numbers from back in the day. 
> There may be more patents.  Search on the inventor names, and the
> "referenced by" section in Google Patents and the US Patent Office.  
> Stein pat5315566, Stein pat5155695, Stein pat5128909, Solbrig (Phase
> Det) pat7227346, Solbrig (DDS) pat7436166, pat7511469, pat6194918, and
> pat6172533.

Thanks, there are several new ones I haven't seen before.
 
> Rickman - see Solbrig (DDS) pat7436166.

>>>> Also, if you happen to come across anything from Holzworth
>>>> Instrumentation in Boulder, please let me know. They have a
>>>> propretary synthesizer technique that doesn't use plls and
>>>> apparently no DDS. They can switch frequencies anywhere from
>>>> anywhere to in 50us, and nearby frequencies in 5us. It is
>>>> driving me mad to figure out how they do it.

>>>> There is apparently nothing in the literature or anything on
>>>> the web that talks about anything that can do that.
 
>> > Yeah, I know. Their sales engineers were giving me the
>> > I've-got-a-secret routine as well. But the founder (Jason
>> > Breitbarth) is the main brain, and as is often the case with small
>> > technology companies, the core technology was developed for his
>> > PhD thesis, and it's all there:

<http://ecee.colorado.edu/microwave/docs/theses/jasonb_phd_thesis.pdf>

> So, you still live in Boulder?
 
I wish. I moved back to Canada some time ago and often regret it. But my 
green card expired after a year and it would be very difficult to move 
back.
 
>> I read through the entire thesis but it's basically a 4.6GHZ coaxial
>> resonator oscillator and nonlinear transmission lines using a YIG
>> filter. There's nothing on wideband synthesizers. Multiplying up
>> from 100MHz would create sidebands that would be very hard to remove,
>> especially for a variable frequency system. 
> 
> Hmm.  The mapping from the various boasts about Holtzworth's products
> and sales pitches to the thesis seemed pretty clear to me.  If I
> recall, he was using a vernier set of frequency combs, arranged such
> that it was easy to lock a PLL onto a specified multiple.  After that,
> one used mixers.

The thesis talks about NLTL comb generators followed by a YIG filter and  
pll to drive the 4.6GHz oscillator. It reads like an undergrad lab paper 
reviewing old technology. There is nothing new or phd-worthy anywhere in 
the thesis.

The technology I am interested in has no pll and offers reasonable phase 
noise and very fast switching. Here's some numbers from the HS6002A RF 
Synthesizer (8MHz to 6GHz)

Frequency Resolution : 0.001 Hz

Switching Speed

50 us : Any frequency over full instrument BW
5us   : Any frequency within 5% BW

http://www.dqm.it/documentazione/HS6002_Web_Datasheet.pdf

They stress the non-pll design constantly. Here's a blurb from the web 
site:

Holzworth non-PLL Design Overview

Holzworth synthesizers are designed with a digital front end and a
proprietary, direct analog back end. The proprietary architecture
maintains low spurious response while also providing industry
leading phase noise performance, exhibiting signal jitter
performance of far less than 100fs.

The PLL was excluded from the Holzworth designs for optimal signal
stability and fast switching speeds. Unlike PLL designs, there is no
post switch settling time to reach the new frequency. Holzworth
synthesizers exhibit little or no settling time under most switching
scenarios.

http://www.holzworth.com/coherency.html

After reading the thesis, it doesn't seem like Breitbarth could come up 
with something this clever. However, it appears the company was based on 
the new synthesizer design, so it seems like he joined forces with the 
actual inventor who may now be an upper-level executive in the company.

So the next step may be to research the executives, find out where they 
graduated, and get their thesis papers.
 
Thanks for your interest and replies. I really appreciate your comments.

> Joe Gwinn

Phil Hobbs wrote:

> Because the signal coming back is at VHF, and using nulling eliminates
> the need for 2D calibration, as I said.  A DDS is less complicated to
> use than a 200 MHz ADC, for sure, and it saves me a boatload of Mini
> Circuits stuff getting the signal down to baseband, and several
> expensive and phase-distorting filters getting rid of all the attendant
> spurs.

Just a final remark to close the discussion about this approach: 
undersampling?

	Best regards, Piotr