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semiconductor drift

Started by John Larkin December 3, 2014
On Wed, 03 Dec 2014 18:01:04 -0800, John Larkin
<jlarkin@highlandtechnology.com> wrote:

> >We have two 8-channel waveform generators that were shipped 4 months >ago, and came back because the customer ordered too many or something. >We routinely test anything that comes back, before returning them or >returning to stock. > >What's interesting is that all 16 channels have a negative DC offset. >Each channel is a diff-current-output cmos DAC, an opamp diffamp, a >passive LC filter, and an output amp; the opamps are fast bipolars. We >apply a software cal factor to the DAC data (saved in a cal table) to >get the offsets way below 1 mV when we ship. After 4 months, we're >seeing offsets from -5 to -10 mV. These are not actual failures, but I >don't like or understand the trend. > >We'll be doing some tests to try to isolate the drift to dac, diffamp, >or output amp. I figure we could measure things on one board, bake to >accelerate aging, and re-measure. > >My general question, to people who understand semi physics: what are >the physical mechanisms that could make the DAC, or the opamps, have >this ensemble negative drift vs time? > >Parts are DAC2904, LMH6642, and THS3062. > >THS3062 is known to be buggy, latching up if slewed hard at high >frequency, but this board doesn't stress them up there.
Probably the DAC since it's current-output style. Why not have an auto-zero at each power-up? ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Wednesday, December 3, 2014 9:01:11 PM UTC-5, John Larkin wrote:
> We have two 8-channel waveform generators that were shipped 4 months > ago, and came back because the customer ordered too many or something. > We routinely test anything that comes back, before returning them or > returning to stock. > > What's interesting is that all 16 channels have a negative DC offset. > Each channel is a diff-current-output cmos DAC, an opamp diffamp, a > passive LC filter, and an output amp; the opamps are fast bipolars. We > apply a software cal factor to the DAC data (saved in a cal table) to > get the offsets way below 1 mV when we ship. After 4 months, we're > seeing offsets from -5 to -10 mV. These are not actual failures, but I > don't like or understand the trend. > > We'll be doing some tests to try to isolate the drift to dac, diffamp, > or output amp. I figure we could measure things on one board, bake to > accelerate aging, and re-measure. > > My general question, to people who understand semi physics: what are > the physical mechanisms that could make the DAC, or the opamps, have > this ensemble negative drift vs time? > > Parts are DAC2904, LMH6642, and THS3062. > > THS3062 is known to be buggy, latching up if slewed hard at high > frequency, but this board doesn't stress them up there. > >
Do you have any on the shelf that you could compare the returns with? (maybe the original prototype?) George H.
> > -- > > John Larkin Highland Technology, Inc > picosecond timing precision measurement > > jlarkin att highlandtechnology dott com > http://www.highlandtechnology.com
On Thu, 04 Dec 2014 01:55:03 -0500, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

>On Wed, 03 Dec 2014 21:56:40 -0800, the renowned John Larkin ><jlarkin@highlandtechnology.com> wrote: > >> >>Unlikely. The device specs shouldn't allow offsets that big. And all >>in the same direction! >> >>I was curious about what physics can cause drift in linear ICs. >> >> >>-- >> >>John Larkin Highland Technology, Inc >>picosecond timing laser drivers and controllers > >CMOS-input op-amps can develop offset voltages if they see a large >differential voltage for a long time (due to movement of ionic >impurities, IIRC). Could that be happening somewhere?
The DAC is CMOS, so gate threshold shift, from oxide contamination, might conceivably change switch ON resistances.
> >Beta degradation with Vbe breakdown could lead to Vos shift if the >bias currents were changed enough.
I doubt that we are zenering the opamp front-ends. As far as I know, the boards weren't even powered up while at the customer.
> >Firmware glitch that cleared out lower bytes of calibration numbers or >something like that?
We chacked tha cal table, which includes cal date/time and a checksum, and it looks OK. BOTH boards, all 16 channels, are drifting negative! -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Thu, 4 Dec 2014 06:43:28 -0800 (PST), Klaus Kragelund
<klauskvik@hotmail.com> wrote:

>On Thursday, December 4, 2014 3:01:11 AM UTC+1, John Larkin wrote: >> We have two 8-channel waveform generators that were shipped 4 months >> ago, and came back because the customer ordered too many or something. >> We routinely test anything that comes back, before returning them or >> returning to stock. >> >> What's interesting is that all 16 channels have a negative DC offset. >> Each channel is a diff-current-output cmos DAC, an opamp diffamp, a >> passive LC filter, and an output amp; the opamps are fast bipolars. We >> apply a software cal factor to the DAC data (saved in a cal table) to >> get the offsets way below 1 mV when we ship. After 4 months, we're >> seeing offsets from -5 to -10 mV. These are not actual failures, but I >> don't like or understand the trend. >> >> We'll be doing some tests to try to isolate the drift to dac, diffamp, >> or output amp. I figure we could measure things on one board, bake to >> accelerate aging, and re-measure. >> >> My general question, to people who understand semi physics: what are >> the physical mechanisms that could make the DAC, or the opamps, have >> this ensemble negative drift vs time? >> >> Parts are DAC2904, LMH6642, and THS3062. >> >> THS3062 is known to be buggy, latching up if slewed hard at high >> frequency, but this board doesn't stress them up there. >> > >Both the LMH6642 and THS3062 has specified up to 5mV input offset voltage > >So with that wide input offset value, do you think a calibration at beginning of life is going to fix that drift magically over time?
These opamps are spec'd for offset and for offset tempco, but not for longterm drift. It's rare to have such a spec. My question, for people who actually understand semiconductor physics, is about the possible drift mechanisms. Seems lot a lot of drift, too.
> >The parts has defined temperature drift (average), but no lifetime specs > >In a earlier employment we did the same. Just closed our eyes for lifetime drift and did calibration at beginning of life (even temperature calibration). > >I wanted to know more, asked a supplier, got information deep from the IC guys and the response was that when a part was powered up again, at a later time in life, the offset could be anywhere within the specs (I don't know if he was just saying that in order not to disclose too much, but it makes sense that a part with large VOS will have a lot of lifetime drift)
Sounds like butt-covering. -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Thu, 04 Dec 2014 09:54:50 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

>On Wed, 03 Dec 2014 18:01:04 -0800, John Larkin ><jlarkin@highlandtechnology.com> wrote: > >> >>We have two 8-channel waveform generators that were shipped 4 months >>ago, and came back because the customer ordered too many or something. >>We routinely test anything that comes back, before returning them or >>returning to stock. >> >>What's interesting is that all 16 channels have a negative DC offset. >>Each channel is a diff-current-output cmos DAC, an opamp diffamp, a >>passive LC filter, and an output amp; the opamps are fast bipolars. We >>apply a software cal factor to the DAC data (saved in a cal table) to >>get the offsets way below 1 mV when we ship. After 4 months, we're >>seeing offsets from -5 to -10 mV. These are not actual failures, but I >>don't like or understand the trend. >> >>We'll be doing some tests to try to isolate the drift to dac, diffamp, >>or output amp. I figure we could measure things on one board, bake to >>accelerate aging, and re-measure. >> >>My general question, to people who understand semi physics: what are >>the physical mechanisms that could make the DAC, or the opamps, have >>this ensemble negative drift vs time? >> >>Parts are DAC2904, LMH6642, and THS3062. >> >>THS3062 is known to be buggy, latching up if slewed hard at high >>frequency, but this board doesn't stress them up there. > >Probably the DAC since it's current-output style. > >Why not have an auto-zero at each power-up? > > ...Jim Thompson
There's no way to read the output level. We didn't anticipate this sort of drift. It's not a big problem. I was just hoping someone could explain potential drift mechanisms. -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Thu, 4 Dec 2014 09:56:12 -0800 (PST), George Herold
<gherold@teachspin.com> wrote:

>On Wednesday, December 3, 2014 9:01:11 PM UTC-5, John Larkin wrote: >> We have two 8-channel waveform generators that were shipped 4 months >> ago, and came back because the customer ordered too many or something. >> We routinely test anything that comes back, before returning them or >> returning to stock. >> >> What's interesting is that all 16 channels have a negative DC offset. >> Each channel is a diff-current-output cmos DAC, an opamp diffamp, a >> passive LC filter, and an output amp; the opamps are fast bipolars. We >> apply a software cal factor to the DAC data (saved in a cal table) to >> get the offsets way below 1 mV when we ship. After 4 months, we're >> seeing offsets from -5 to -10 mV. These are not actual failures, but I >> don't like or understand the trend. >> >> We'll be doing some tests to try to isolate the drift to dac, diffamp, >> or output amp. I figure we could measure things on one board, bake to >> accelerate aging, and re-measure. >> >> My general question, to people who understand semi physics: what are >> the physical mechanisms that could make the DAC, or the opamps, have >> this ensemble negative drift vs time? >> >> Parts are DAC2904, LMH6642, and THS3062. >> >> THS3062 is known to be buggy, latching up if slewed hard at high >> frequency, but this board doesn't stress them up there. >> >> >Do you have any on the shelf that you could compare the returns with? >(maybe the original prototype?)
We might do that. Just now, we're experimenting with these two boards. We'll bake one to maybe accelerate the aging (and, hopefully, not anneal the drift out.) I have seen drifty-type failure mechanisms that could be fixed, for a few months, by baking. -- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On Thu, 04 Dec 2014 11:30:13 -0800, John Larkin wrote:

> On Thu, 4 Dec 2014 06:43:28 -0800 (PST), Klaus Kragelund > <klauskvik@hotmail.com> wrote: > >>On Thursday, December 4, 2014 3:01:11 AM UTC+1, John Larkin wrote: >>> We have two 8-channel waveform generators that were shipped 4 months >>> ago, and came back because the customer ordered too many or something. >>> We routinely test anything that comes back, before returning them or >>> returning to stock. >>> >>> What's interesting is that all 16 channels have a negative DC offset. >>> Each channel is a diff-current-output cmos DAC, an opamp diffamp, a >>> passive LC filter, and an output amp; the opamps are fast bipolars. We >>> apply a software cal factor to the DAC data (saved in a cal table) to >>> get the offsets way below 1 mV when we ship. After 4 months, we're >>> seeing offsets from -5 to -10 mV. These are not actual failures, but I >>> don't like or understand the trend. >>> >>> We'll be doing some tests to try to isolate the drift to dac, diffamp, >>> or output amp. I figure we could measure things on one board, bake to >>> accelerate aging, and re-measure. >>> >>> My general question, to people who understand semi physics: what are >>> the physical mechanisms that could make the DAC, or the opamps, have >>> this ensemble negative drift vs time? >>> >>> Parts are DAC2904, LMH6642, and THS3062. >>> >>> THS3062 is known to be buggy, latching up if slewed hard at high >>> frequency, but this board doesn't stress them up there. >>> >> >>Both the LMH6642 and THS3062 has specified up to 5mV input offset voltage >> >>So with that wide input offset value, do you think a calibration at beginning of life is going to fix that drift magically over time? > > These opamps are spec'd for offset and for offset tempco, but not for > longterm drift. It's rare to have such a spec. My question, for people > who actually understand semiconductor physics, is about the possible > drift mechanisms. > > Seems lot a lot of drift, too. > > > > >> >>The parts has defined temperature drift (average), but no lifetime specs >> >>In a earlier employment we did the same. Just closed our eyes for lifetime drift and did calibration at beginning of life (even temperature calibration). >> >>I wanted to know more, asked a supplier, got information deep from the IC guys and the response was that when a part was powered up again, at a later time in life, the offset could be anywhere within the specs (I don't know if he was just saying that in order not to disclose too much, but it makes sense that a part with large VOS will have a lot of lifetime drift) > > Sounds like butt-covering.
How about showing your circuit - or at least telling us how much opamp offsets would be required to cause its output to change by 10mV?
On Thu, 4 Dec 2014 19:46:32 +0000 (UTC), Frank Miles
<fpm@u.washington.edu> wrote:

>On Thu, 04 Dec 2014 11:30:13 -0800, John Larkin wrote: > >> On Thu, 4 Dec 2014 06:43:28 -0800 (PST), Klaus Kragelund >> <klauskvik@hotmail.com> wrote: >> >>>On Thursday, December 4, 2014 3:01:11 AM UTC+1, John Larkin wrote: >>>> We have two 8-channel waveform generators that were shipped 4 months >>>> ago, and came back because the customer ordered too many or something. >>>> We routinely test anything that comes back, before returning them or >>>> returning to stock. >>>> >>>> What's interesting is that all 16 channels have a negative DC offset. >>>> Each channel is a diff-current-output cmos DAC, an opamp diffamp, a >>>> passive LC filter, and an output amp; the opamps are fast bipolars. We >>>> apply a software cal factor to the DAC data (saved in a cal table) to >>>> get the offsets way below 1 mV when we ship. After 4 months, we're >>>> seeing offsets from -5 to -10 mV. These are not actual failures, but I >>>> don't like or understand the trend. >>>> >>>> We'll be doing some tests to try to isolate the drift to dac, diffamp, >>>> or output amp. I figure we could measure things on one board, bake to >>>> accelerate aging, and re-measure. >>>> >>>> My general question, to people who understand semi physics: what are >>>> the physical mechanisms that could make the DAC, or the opamps, have >>>> this ensemble negative drift vs time? >>>> >>>> Parts are DAC2904, LMH6642, and THS3062. >>>> >>>> THS3062 is known to be buggy, latching up if slewed hard at high >>>> frequency, but this board doesn't stress them up there. >>>> >>> >>>Both the LMH6642 and THS3062 has specified up to 5mV input offset voltage >>> >>>So with that wide input offset value, do you think a calibration at beginning of life is going to fix that drift magically over time? >> >> These opamps are spec'd for offset and for offset tempco, but not for >> longterm drift. It's rare to have such a spec. My question, for people >> who actually understand semiconductor physics, is about the possible >> drift mechanisms. >> >> Seems lot a lot of drift, too. >> >> >> >> >>> >>>The parts has defined temperature drift (average), but no lifetime specs >>> >>>In a earlier employment we did the same. Just closed our eyes for lifetime drift and did calibration at beginning of life (even temperature calibration). >>> >>>I wanted to know more, asked a supplier, got information deep from the IC guys and the response was that when a part was powered up again, at a later time in life, the offset could be anywhere within the specs (I don't know if he was just saying that in order not to disclose too much, but it makes sense that a part with large VOS will have a lot of lifetime drift) >> >> Sounds like butt-covering. > >How about showing your circuit - or at least telling us how much opamp offsets >would be required to cause its output to change by 10mV?
Here it is: https://dl.dropboxusercontent.com/u/53724080/Circuits/VME/22S340B_sh2.pdf The overall gain from the DAC diff output, to the final unloaded output, is about 13, so, if the drift is at the front end, it's maybe 500 uV. If it's in U8, it's equivalent to about 1 mV. We are doing some tests to see who is drifting. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Martin Riddle wrote:


> Could it be moisture related? FR4 can absorb moisture, a certain % of > its weight per month. Maybe put the boards under vacuum and draw it > out and look at the difference. Do you use any High impedance > resistors in there? Low bias current amps?
It's not just FR4. Pretty much EVERYTHING absorbs moisture. If the units were calibrated within a day after assembly of the boards, all the 1% resistors will still be settling down. Take a 1% resistor, heat it as if soldering both leads, and then test with a sensitive Ohmmeter for a couple hours. You be amazed at how long it continues to drift! Obviously, there is a mechanism that goes WAY beyond just the cooling off after reaching soldering temp. Maybe the one time I really did this experiment, I had some truly crummy resistors, but I was STUNNED by the magnitude of the drift immediately after the resistors were back to room temperature, they remained some 10% or more out of tolerance! After an hour, they were close to being back in tolerance, but continued to drift for several more hours, until well within the 1% band. Jon
John Larkin wrote:


> Just now, we're experimenting with these two boards. > We'll bake one to maybe accelerate the aging (and, hopefully, not > anneal the drift out.)
And that might just reset the drift back to zero, and start the process all over again. Jon