Den torsdag den 4. december 2014 23.52.44 UTC+1 skrev Phil Hobbs:> On 12/04/2014 03:18 PM, John Larkin wrote: > > On Thu, 4 Dec 2014 19:46:32 +0000 (UTC), Frank Miles > > <fpm@u.washington.edu> wrote: > > > >> On Thu, 04 Dec 2014 11:30:13 -0800, John Larkin wrote: > >> > >>> On Thu, 4 Dec 2014 06:43:28 -0800 (PST), Klaus Kragelund > >>> <klauskvik@hotmail.com> wrote: > >>> > >>>> On Thursday, December 4, 2014 3:01:11 AM UTC+1, John Larkin wrote: > >>>>> We have two 8-channel waveform generators that were shipped 4 month=s> >>>>> ago, and came back because the customer ordered too many or somethi=ng.> >>>>> We routinely test anything that comes back, before returning them o=r> >>>>> returning to stock. > >>>>> > >>>>> What's interesting is that all 16 channels have a negative DC offse=t.> >>>>> Each channel is a diff-current-output cmos DAC, an opamp diffamp, a > >>>>> passive LC filter, and an output amp; the opamps are fast bipolars.=We> >>>>> apply a software cal factor to the DAC data (saved in a cal table) =to> >>>>> get the offsets way below 1 mV when we ship. After 4 months, we're > >>>>> seeing offsets from -5 to -10 mV. These are not actual failures, bu=t I> >>>>> don't like or understand the trend. > >>>>> > >>>>> We'll be doing some tests to try to isolate the drift to dac, diffa=mp,> >>>>> or output amp. I figure we could measure things on one board, bake =to> >>>>> accelerate aging, and re-measure. > >>>>> > >>>>> My general question, to people who understand semi physics: what ar=e> >>>>> the physical mechanisms that could make the DAC, or the opamps, hav=e> >>>>> this ensemble negative drift vs time? > >>>>> > >>>>> Parts are DAC2904, LMH6642, and THS3062. > >>>>> > >>>>> THS3062 is known to be buggy, latching up if slewed hard at high > >>>>> frequency, but this board doesn't stress them up there. > >>>>> > >>>> > >>>> Both the LMH6642 and THS3062 has specified up to 5mV input offset vo=ltage> >>>> > >>>> So with that wide input offset value, do you think a calibration at =beginning of life is going to fix that drift magically over time?> >>> > >>> These opamps are spec'd for offset and for offset tempco, but not for > >>> longterm drift. It's rare to have such a spec. My question, for peopl=e> >>> who actually understand semiconductor physics, is about the possible > >>> drift mechanisms. > >>> > >>> Seems lot a lot of drift, too. > >>> > >>> > >>> > >>> > >>>> > >>>> The parts has defined temperature drift (average), but no lifetime s=pecs> >>>> > >>>> In a earlier employment we did the same. Just closed our eyes for li=fetime drift and did calibration at beginning of life (even temperature cal= ibration).> >>>> > >>>> I wanted to know more, asked a supplier, got information deep from t=he IC guys and the response was that when a part was powered up again, at a= later time in life, the offset could be anywhere within the specs (I don't= know if he was just saying that in order not to disclose too much, but it = makes sense that a part with large VOS will have a lot of lifetime drift)> >>> > >>> Sounds like butt-covering. > >> > >> How about showing your circuit - or at least telling us how much opamp=offsets> >> would be required to cause its output to change by 10mV? > > > > > > Here it is: > > > > https://dl.dropboxusercontent.com/u/53724080/Circuits/VME/22S340B_sh2.p=df> > > > The overall gain from the DAC diff output, to the final unloaded > > output, is about 13, so, if the drift is at the front end, it's maybe > > 500 uV. If it's in U8, it's equivalent to about 1 mV. > > > > We are doing some tests to see who is drifting. > > > > > > > > >=20 > I gather L1 and L2 are a pop option. If not, there's your trouble. ;) >=20yeh, I guess * means not mounted :) -Lasse
semiconductor drift
Started by ●December 3, 2014
Reply by ●December 4, 20142014-12-04
Reply by ●December 4, 20142014-12-04
On Thu, 4 Dec 2014 15:03:22 -0800 (PST), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>Den torsdag den 4. december 2014 23.52.44 UTC+1 skrev Phil Hobbs: >> On 12/04/2014 03:18 PM, John Larkin wrote: >> > On Thu, 4 Dec 2014 19:46:32 +0000 (UTC), Frank Miles >> > <fpm@u.washington.edu> wrote: >> > >> >> On Thu, 04 Dec 2014 11:30:13 -0800, John Larkin wrote: >> >> >> >>> On Thu, 4 Dec 2014 06:43:28 -0800 (PST), Klaus Kragelund >> >>> <klauskvik@hotmail.com> wrote: >> >>> >> >>>> On Thursday, December 4, 2014 3:01:11 AM UTC+1, John Larkin wrote: >> >>>>> We have two 8-channel waveform generators that were shipped 4 months >> >>>>> ago, and came back because the customer ordered too many or something. >> >>>>> We routinely test anything that comes back, before returning them or >> >>>>> returning to stock. >> >>>>> >> >>>>> What's interesting is that all 16 channels have a negative DC offset. >> >>>>> Each channel is a diff-current-output cmos DAC, an opamp diffamp, a >> >>>>> passive LC filter, and an output amp; the opamps are fast bipolars. We >> >>>>> apply a software cal factor to the DAC data (saved in a cal table) to >> >>>>> get the offsets way below 1 mV when we ship. After 4 months, we're >> >>>>> seeing offsets from -5 to -10 mV. These are not actual failures, but I >> >>>>> don't like or understand the trend. >> >>>>> >> >>>>> We'll be doing some tests to try to isolate the drift to dac, diffamp, >> >>>>> or output amp. I figure we could measure things on one board, bake to >> >>>>> accelerate aging, and re-measure. >> >>>>> >> >>>>> My general question, to people who understand semi physics: what are >> >>>>> the physical mechanisms that could make the DAC, or the opamps, have >> >>>>> this ensemble negative drift vs time? >> >>>>> >> >>>>> Parts are DAC2904, LMH6642, and THS3062. >> >>>>> >> >>>>> THS3062 is known to be buggy, latching up if slewed hard at high >> >>>>> frequency, but this board doesn't stress them up there. >> >>>>> >> >>>> >> >>>> Both the LMH6642 and THS3062 has specified up to 5mV input offset voltage >> >>>> >> >>>> So with that wide input offset value, do you think a calibration at beginning of life is going to fix that drift magically over time? >> >>> >> >>> These opamps are spec'd for offset and for offset tempco, but not for >> >>> longterm drift. It's rare to have such a spec. My question, for people >> >>> who actually understand semiconductor physics, is about the possible >> >>> drift mechanisms. >> >>> >> >>> Seems lot a lot of drift, too. >> >>> >> >>> >> >>> >> >>> >> >>>> >> >>>> The parts has defined temperature drift (average), but no lifetime specs >> >>>> >> >>>> In a earlier employment we did the same. Just closed our eyes for lifetime drift and did calibration at beginning of life (even temperature calibration). >> >>>> >> >>>> I wanted to know more, asked a supplier, got information deep from the IC guys and the response was that when a part was powered up again, at a later time in life, the offset could be anywhere within the specs (I don't know if he was just saying that in order not to disclose too much, but it makes sense that a part with large VOS will have a lot of lifetime drift) >> >>> >> >>> Sounds like butt-covering. >> >> >> >> How about showing your circuit - or at least telling us how much opamp offsets >> >> would be required to cause its output to change by 10mV? >> > >> > >> > Here it is: >> > >> > https://dl.dropboxusercontent.com/u/53724080/Circuits/VME/22S340B_sh2.pdf >> > >> > The overall gain from the DAC diff output, to the final unloaded >> > output, is about 13, so, if the drift is at the front end, it's maybe >> > 500 uV. If it's in U8, it's equivalent to about 1 mV. >> > >> > We are doing some tests to see who is drifting. >> > >> > >> > >> > >> >> I gather L1 and L2 are a pop option. If not, there's your trouble. ;) >> > >yeh, I guess * means not mounted :) > > >-LasseI have "parts" in my PSpice library with assignable values, but labeled "DNF" (do not fill), that show on the schematic, but don't netlist, to handle options. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●December 4, 20142014-12-04
Den fredag den 5. december 2014 00.21.11 UTC+1 skrev Jim Thompson:> On Thu, 4 Dec 2014 15:03:22 -0800 (PST), Lasse Langwadt Christensen > <langwadt@fonz.dk> wrote: >=20 > >Den torsdag den 4. december 2014 23.52.44 UTC+1 skrev Phil Hobbs: > >> On 12/04/2014 03:18 PM, John Larkin wrote: > >> > On Thu, 4 Dec 2014 19:46:32 +0000 (UTC), Frank Miles > >> > <fpm@u.washington.edu> wrote: > >> > > >> >> On Thu, 04 Dec 2014 11:30:13 -0800, John Larkin wrote: > >> >> > >> >>> On Thu, 4 Dec 2014 06:43:28 -0800 (PST), Klaus Kragelund > >> >>> <klauskvik@hotmail.com> wrote: > >> >>> > >> >>>> On Thursday, December 4, 2014 3:01:11 AM UTC+1, John Larkin wrote=:> >> >>>>> We have two 8-channel waveform generators that were shipped 4 mo=nths> >> >>>>> ago, and came back because the customer ordered too many or some=thing.> >> >>>>> We routinely test anything that comes back, before returning the=m or> >> >>>>> returning to stock. > >> >>>>> > >> >>>>> What's interesting is that all 16 channels have a negative DC of=fset.> >> >>>>> Each channel is a diff-current-output cmos DAC, an opamp diffamp=, a> >> >>>>> passive LC filter, and an output amp; the opamps are fast bipola=rs. We> >> >>>>> apply a software cal factor to the DAC data (saved in a cal tabl=e) to> >> >>>>> get the offsets way below 1 mV when we ship. After 4 months, we'=re> >> >>>>> seeing offsets from -5 to -10 mV. These are not actual failures,=but I> >> >>>>> don't like or understand the trend. > >> >>>>> > >> >>>>> We'll be doing some tests to try to isolate the drift to dac, di=ffamp,> >> >>>>> or output amp. I figure we could measure things on one board, ba=ke to> >> >>>>> accelerate aging, and re-measure. > >> >>>>> > >> >>>>> My general question, to people who understand semi physics: what=are> >> >>>>> the physical mechanisms that could make the DAC, or the opamps, =have> >> >>>>> this ensemble negative drift vs time? > >> >>>>> > >> >>>>> Parts are DAC2904, LMH6642, and THS3062. > >> >>>>> > >> >>>>> THS3062 is known to be buggy, latching up if slewed hard at high > >> >>>>> frequency, but this board doesn't stress them up there. > >> >>>>> > >> >>>> > >> >>>> Both the LMH6642 and THS3062 has specified up to 5mV input offset=voltage> >> >>>> > >> >>>> So with that wide input offset value, do you think a calibration =at beginning of life is going to fix that drift magically over time?> >> >>> > >> >>> These opamps are spec'd for offset and for offset tempco, but not =for> >> >>> longterm drift. It's rare to have such a spec. My question, for pe=ople> >> >>> who actually understand semiconductor physics, is about the possib=le> >> >>> drift mechanisms. > >> >>> > >> >>> Seems lot a lot of drift, too. > >> >>> > >> >>> > >> >>> > >> >>> > >> >>>> > >> >>>> The parts has defined temperature drift (average), but no lifetim=e specs> >> >>>> > >> >>>> In a earlier employment we did the same. Just closed our eyes for=lifetime drift and did calibration at beginning of life (even temperature = calibration).> >> >>>> > >> >>>> I wanted to know more, asked a supplier, got information deep fro=m the IC guys and the response was that when a part was powered up again, a= t a later time in life, the offset could be anywhere within the specs (I do= n't know if he was just saying that in order not to disclose too much, but = it makes sense that a part with large VOS will have a lot of lifetime drift= )> >> >>> > >> >>> Sounds like butt-covering. > >> >> > >> >> How about showing your circuit - or at least telling us how much op=amp offsets> >> >> would be required to cause its output to change by 10mV? > >> > > >> > > >> > Here it is: > >> > > >> > https://dl.dropboxusercontent.com/u/53724080/Circuits/VME/22S340B_sh=2.pdf> >> > > >> > The overall gain from the DAC diff output, to the final unloaded > >> > output, is about 13, so, if the drift is at the front end, it's mayb=e> >> > 500 uV. If it's in U8, it's equivalent to about 1 mV. > >> > > >> > We are doing some tests to see who is drifting. > >> > > >> > > >> > > >> > > >>=20 > >> I gather L1 and L2 are a pop option. If not, there's your trouble. ;) > >>=20 > > > >yeh, I guess * means not mounted :) > > > > > >-Lasse >=20 > I have "parts" in my PSpice library with assignable values, but > labeled "DNF" (do not fill), that show on the schematic, but don't > netlist, to handle options. >=20on our schematics it is an attribute, when set it puts a "not mounted" next= to the component and removes it from the parts list, placements file etc. -Lasse
Reply by ●December 4, 20142014-12-04
On Thu, 4 Dec 2014 15:09:23 -0600, "Tim Williams" <tiwill@seventransistorlabs.com> wrote:>You're trying to ask, > >"My car pulls slightly to the right on the highway. To people who >understand automobiles: what are the physical mechanisms that could do >that?" > >You already very well know, there are a hundred things in either case >which could individually explain it, all of which depend utterly on the >internal construction of the system. The design notes of which are >unspecified and unavailable, so it's useless to even ask. > >And more than likely, it's not even the fault of the system at all, but >"did you notice your left arm is shorter than your right?", or, "no >wonder, your right tires are balled". Like the resistors others have >mentioned. > >Come on John, you should know better than to ask such silly questions to a >public group. If you just want to give fodder to JT, why don't you e-mail >him and save us the trouble. > >TimAs I stated, I am interested in the mechanisms that can make analog ICs drift. The only silly thing about my question was asking it here, where nobody seems to know much about semiconductor physics. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●December 4, 20142014-12-04
On Thu, 4 Dec 2014 15:03:22 -0800 (PST), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>Den torsdag den 4. december 2014 23.52.44 UTC+1 skrev Phil Hobbs: >> On 12/04/2014 03:18 PM, John Larkin wrote: >> > On Thu, 4 Dec 2014 19:46:32 +0000 (UTC), Frank Miles >> > <fpm@u.washington.edu> wrote: >> > >> >> On Thu, 04 Dec 2014 11:30:13 -0800, John Larkin wrote: >> >> >> >>> On Thu, 4 Dec 2014 06:43:28 -0800 (PST), Klaus Kragelund >> >>> <klauskvik@hotmail.com> wrote: >> >>> >> >>>> On Thursday, December 4, 2014 3:01:11 AM UTC+1, John Larkin wrote: >> >>>>> We have two 8-channel waveform generators that were shipped 4 months >> >>>>> ago, and came back because the customer ordered too many or something. >> >>>>> We routinely test anything that comes back, before returning them or >> >>>>> returning to stock. >> >>>>> >> >>>>> What's interesting is that all 16 channels have a negative DC offset. >> >>>>> Each channel is a diff-current-output cmos DAC, an opamp diffamp, a >> >>>>> passive LC filter, and an output amp; the opamps are fast bipolars. We >> >>>>> apply a software cal factor to the DAC data (saved in a cal table) to >> >>>>> get the offsets way below 1 mV when we ship. After 4 months, we're >> >>>>> seeing offsets from -5 to -10 mV. These are not actual failures, but I >> >>>>> don't like or understand the trend. >> >>>>> >> >>>>> We'll be doing some tests to try to isolate the drift to dac, diffamp, >> >>>>> or output amp. I figure we could measure things on one board, bake to >> >>>>> accelerate aging, and re-measure. >> >>>>> >> >>>>> My general question, to people who understand semi physics: what are >> >>>>> the physical mechanisms that could make the DAC, or the opamps, have >> >>>>> this ensemble negative drift vs time? >> >>>>> >> >>>>> Parts are DAC2904, LMH6642, and THS3062. >> >>>>> >> >>>>> THS3062 is known to be buggy, latching up if slewed hard at high >> >>>>> frequency, but this board doesn't stress them up there. >> >>>>> >> >>>> >> >>>> Both the LMH6642 and THS3062 has specified up to 5mV input offset voltage >> >>>> >> >>>> So with that wide input offset value, do you think a calibration at beginning of life is going to fix that drift magically over time? >> >>> >> >>> These opamps are spec'd for offset and for offset tempco, but not for >> >>> longterm drift. It's rare to have such a spec. My question, for people >> >>> who actually understand semiconductor physics, is about the possible >> >>> drift mechanisms. >> >>> >> >>> Seems lot a lot of drift, too. >> >>> >> >>> >> >>> >> >>> >> >>>> >> >>>> The parts has defined temperature drift (average), but no lifetime specs >> >>>> >> >>>> In a earlier employment we did the same. Just closed our eyes for lifetime drift and did calibration at beginning of life (even temperature calibration). >> >>>> >> >>>> I wanted to know more, asked a supplier, got information deep from the IC guys and the response was that when a part was powered up again, at a later time in life, the offset could be anywhere within the specs (I don't know if he was just saying that in order not to disclose too much, but it makes sense that a part with large VOS will have a lot of lifetime drift) >> >>> >> >>> Sounds like butt-covering. >> >> >> >> How about showing your circuit - or at least telling us how much opamp offsets >> >> would be required to cause its output to change by 10mV? >> > >> > >> > Here it is: >> > >> > https://dl.dropboxusercontent.com/u/53724080/Circuits/VME/22S340B_sh2.pdf >> > >> > The overall gain from the DAC diff output, to the final unloaded >> > output, is about 13, so, if the drift is at the front end, it's maybe >> > 500 uV. If it's in U8, it's equivalent to about 1 mV. >> > >> > We are doing some tests to see who is drifting. >> > >> > >> > >> > >> >> I gather L1 and L2 are a pop option. If not, there's your trouble. ;) >> > >yeh, I guess * means not mounted :) > > >-LasseIt means "optional on different dash numbers." We only have one released schematic for various versions. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●December 4, 20142014-12-04
On Thu, 4 Dec 2014 16:30:05 -0800 (PST), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>Den fredag den 5. december 2014 00.21.11 UTC+1 skrev Jim Thompson: >> On Thu, 4 Dec 2014 15:03:22 -0800 (PST), Lasse Langwadt Christensen >> <langwadt@fonz.dk> wrote: >> >> >Den torsdag den 4. december 2014 23.52.44 UTC+1 skrev Phil Hobbs: >> >> On 12/04/2014 03:18 PM, John Larkin wrote: >> >> > On Thu, 4 Dec 2014 19:46:32 +0000 (UTC), Frank Miles >> >> > <fpm@u.washington.edu> wrote: >> >> > >> >> >> On Thu, 04 Dec 2014 11:30:13 -0800, John Larkin wrote: >> >> >> >> >> >>> On Thu, 4 Dec 2014 06:43:28 -0800 (PST), Klaus Kragelund >> >> >>> <klauskvik@hotmail.com> wrote: >> >> >>> >> >> >>>> On Thursday, December 4, 2014 3:01:11 AM UTC+1, John Larkin wrote: >> >> >>>>> We have two 8-channel waveform generators that were shipped 4 months >> >> >>>>> ago, and came back because the customer ordered too many or something. >> >> >>>>> We routinely test anything that comes back, before returning them or >> >> >>>>> returning to stock. >> >> >>>>> >> >> >>>>> What's interesting is that all 16 channels have a negative DC offset. >> >> >>>>> Each channel is a diff-current-output cmos DAC, an opamp diffamp, a >> >> >>>>> passive LC filter, and an output amp; the opamps are fast bipolars. We >> >> >>>>> apply a software cal factor to the DAC data (saved in a cal table) to >> >> >>>>> get the offsets way below 1 mV when we ship. After 4 months, we're >> >> >>>>> seeing offsets from -5 to -10 mV. These are not actual failures, but I >> >> >>>>> don't like or understand the trend. >> >> >>>>> >> >> >>>>> We'll be doing some tests to try to isolate the drift to dac, diffamp, >> >> >>>>> or output amp. I figure we could measure things on one board, bake to >> >> >>>>> accelerate aging, and re-measure. >> >> >>>>> >> >> >>>>> My general question, to people who understand semi physics: what are >> >> >>>>> the physical mechanisms that could make the DAC, or the opamps, have >> >> >>>>> this ensemble negative drift vs time? >> >> >>>>> >> >> >>>>> Parts are DAC2904, LMH6642, and THS3062. >> >> >>>>> >> >> >>>>> THS3062 is known to be buggy, latching up if slewed hard at high >> >> >>>>> frequency, but this board doesn't stress them up there. >> >> >>>>> >> >> >>>> >> >> >>>> Both the LMH6642 and THS3062 has specified up to 5mV input offset voltage >> >> >>>> >> >> >>>> So with that wide input offset value, do you think a calibration at beginning of life is going to fix that drift magically over time? >> >> >>> >> >> >>> These opamps are spec'd for offset and for offset tempco, but not for >> >> >>> longterm drift. It's rare to have such a spec. My question, for people >> >> >>> who actually understand semiconductor physics, is about the possible >> >> >>> drift mechanisms. >> >> >>> >> >> >>> Seems lot a lot of drift, too. >> >> >>> >> >> >>> >> >> >>> >> >> >>> >> >> >>>> >> >> >>>> The parts has defined temperature drift (average), but no lifetime specs >> >> >>>> >> >> >>>> In a earlier employment we did the same. Just closed our eyes for lifetime drift and did calibration at beginning of life (even temperature calibration). >> >> >>>> >> >> >>>> I wanted to know more, asked a supplier, got information deep from the IC guys and the response was that when a part was powered up again, at a later time in life, the offset could be anywhere within the specs (I don't know if he was just saying that in order not to disclose too much, but it makes sense that a part with large VOS will have a lot of lifetime drift) >> >> >>> >> >> >>> Sounds like butt-covering. >> >> >> >> >> >> How about showing your circuit - or at least telling us how much opamp offsets >> >> >> would be required to cause its output to change by 10mV? >> >> > >> >> > >> >> > Here it is: >> >> > >> >> > https://dl.dropboxusercontent.com/u/53724080/Circuits/VME/22S340B_sh2.pdf >> >> > >> >> > The overall gain from the DAC diff output, to the final unloaded >> >> > output, is about 13, so, if the drift is at the front end, it's maybe >> >> > 500 uV. If it's in U8, it's equivalent to about 1 mV. >> >> > >> >> > We are doing some tests to see who is drifting. >> >> > >> >> > >> >> > >> >> > >> >> >> >> I gather L1 and L2 are a pop option. If not, there's your trouble. ;) >> >> >> > >> >yeh, I guess * means not mounted :) >> > >> > >> >-Lasse >> >> I have "parts" in my PSpice library with assignable values, but >> labeled "DNF" (do not fill), that show on the schematic, but don't >> netlist, to handle options. >> > >on our schematics it is an attribute, when set it puts a "not mounted" next to the component and removes it from the parts list, placements file etc. > >-LasseGood idea. I'll change it to an attribute which will insert * in front of the netlist line. I've done that for test vehicles that i step... don't know why I didn't consider it for DNF. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●December 4, 20142014-12-04
On Thursday, December 4, 2014 3:18:33 PM UTC-5, John Larkin wrote:> On Thu, 4 Dec 2014 19:46:32 +0000 (UTC), Frank Miles > <fpm@u.washington.edu> wrote: >=20 > >On Thu, 04 Dec 2014 11:30:13 -0800, John Larkin wrote: > > > >> On Thu, 4 Dec 2014 06:43:28 -0800 (PST), Klaus Kragelund > >> <klauskvik@hotmail.com> wrote: > >>=20 > >>>On Thursday, December 4, 2014 3:01:11 AM UTC+1, John Larkin wrote: > >>>> We have two 8-channel waveform generators that were shipped 4 months > >>>> ago, and came back because the customer ordered too many or somethin=g.> >>>> We routinely test anything that comes back, before returning them or > >>>> returning to stock. > >>>>=20 > >>>> What's interesting is that all 16 channels have a negative DC offset=.> >>>> Each channel is a diff-current-output cmos DAC, an opamp diffamp, a > >>>> passive LC filter, and an output amp; the opamps are fast bipolars. =We> >>>> apply a software cal factor to the DAC data (saved in a cal table) t=o> >>>> get the offsets way below 1 mV when we ship. After 4 months, we're > >>>> seeing offsets from -5 to -10 mV. These are not actual failures, but=I> >>>> don't like or understand the trend. > >>>>=20 > >>>> We'll be doing some tests to try to isolate the drift to dac, diffam=p,> >>>> or output amp. I figure we could measure things on one board, bake t=o> >>>> accelerate aging, and re-measure. > >>>>=20 > >>>> My general question, to people who understand semi physics: what are > >>>> the physical mechanisms that could make the DAC, or the opamps, have > >>>> this ensemble negative drift vs time?=20 > >>>>=20 > >>>> Parts are DAC2904, LMH6642, and THS3062. > >>>>=20 > >>>> THS3062 is known to be buggy, latching up if slewed hard at high > >>>> frequency, but this board doesn't stress them up there. > >>>>=20 > >>> > >>>Both the LMH6642 and THS3062 has specified up to 5mV input offset volt=age> >>> > >>>So with that wide input offset value, do you think a calibration at be=ginning of life is going to fix that drift magically over time?> >>=20 > >> These opamps are spec'd for offset and for offset tempco, but not for > >> longterm drift. It's rare to have such a spec. My question, for people > >> who actually understand semiconductor physics, is about the possible > >> drift mechanisms. > >>=20 > >> Seems lot a lot of drift, too. > >>=20 > >>=20 > >>=20 > >>=20 > >>> > >>>The parts has defined temperature drift (average), but no lifetime spe=cs> >>> > >>>In a earlier employment we did the same. Just closed our eyes for life=time drift and did calibration at beginning of life (even temperature calib= ration).=20> >>> > >>>I wanted to know more, asked a supplier, got information deep from the=IC guys and the response was that when a part was powered up again, at a l= ater time in life, the offset could be anywhere within the specs (I don't k= now if he was just saying that in order not to disclose too much, but it ma= kes sense that a part with large VOS will have a lot of lifetime drift)> >>=20 > >> Sounds like butt-covering. > > > >How about showing your circuit - or at least telling us how much opamp o=ffsets> >would be required to cause its output to change by 10mV? >=20 >=20 > Here it is: >=20 > https://dl.dropboxusercontent.com/u/53724080/Circuits/VME/22S340B_sh2.pdfNice, is there a different make of resistor somewhere?=20 I had some 0.1%R's that weren't.=20 George H.=20>=20 > The overall gain from the DAC diff output, to the final unloaded > output, is about 13, so, if the drift is at the front end, it's maybe > 500 uV. If it's in U8, it's equivalent to about 1 mV. >=20 > We are doing some tests to see who is drifting. >=20 >=20 >=20 >=20 > --=20 >=20 > John Larkin Highland Technology, Inc > picosecond timing precision measurement=20 >=20 > jlarkin att highlandtechnology dott com > http://www.highlandtechnology.com
Reply by ●December 5, 20142014-12-05
John Larkin wrote:> > As I stated, I am interested in the mechanisms that can make analog > ICs drift. The only silly thing about my question was asking it here, > where nobody seems to know much about semiconductor physics. > >WTF? Didn't you read my post? I explained what can cause semiconductors to drift. Sheesh. Here it is again. ------------------------ Sodium contamination at the factory can cause drift. Less likely would be heavy metals. Sodium is a handling issue. Metals are due to defective fab equipment. I don't know if it exists on the internet, but if you could see the scribe channel side profile, it would show the amount of work that goes into guarding the edges of a chip from contamination. Also a large voltage applied at the input of the op amp (diff pair) can leave an offset. That is why they diode clamp the inputs. ----------------- Man, you get some clown in the fab or wafer test that touches a wafer and all hell breaks loose in the analog world. Or the assembly house DI water isn't really DI because they are in some shit hole sweat shop in Asia. Besides the wafer saw, there is also the back lap process which needs to be clean. Surface mount devices get extreme backlap. Semiconductor manufacturing requires countless steps that must be performed precisely if you want a repeatable product. Now people claim you can't "test in quality", but you can sure weed out products where some clown didn't do their part of the process correctly. I suppose to blather on further, all chips prior to release to production will have to pass burn in. But once the product is qual'd, it will not receive burn in unless you pay for it. Even if you do pay for burn in, it may not be all that dynamic unless the chip is designed with a burn in mode (i.e. factory test mode).
Reply by ●December 5, 20142014-12-05
On Wed, 03 Dec 2014 18:01:04 -0800, John Larkin <jlarkin@highlandtechnology.com> wrote:> >We have two 8-channel waveform generators that were shipped 4 months >ago, and came back because the customer ordered too many or something. >We routinely test anything that comes back, before returning them or >returning to stock. > >What's interesting is that all 16 channels have a negative DC offset. >Each channel is a diff-current-output cmos DAC, an opamp diffamp, a >passive LC filter, and an output amp; the opamps are fast bipolars. We >apply a software cal factor to the DAC data (saved in a cal table) to >get the offsets way below 1 mV when we ship. After 4 months, we're >seeing offsets from -5 to -10 mV. These are not actual failures, but I >don't like or understand the trend. > >We'll be doing some tests to try to isolate the drift to dac, diffamp, >or output amp. I figure we could measure things on one board, bake to >accelerate aging, and re-measure. > >My general question, to people who understand semi physics: what are >the physical mechanisms that could make the DAC, or the opamps, have >this ensemble negative drift vs time?=20 > >Parts are DAC2904, LMH6642, and THS3062. > >THS3062 is known to be buggy, latching up if slewed hard at high >frequency, but this board doesn't stress them up there.Please remember that drift tends to have a curve like 1-e^kt curves with = k being like 1/month to 1/year values. ?-) =20
Reply by ●December 5, 20142014-12-05
On Friday, December 5, 2014 1:34:21 AM UTC+1, John Larkin wrote:> On Thu, 4 Dec 2014 15:09:23 -0600, "Tim Williams" > <tiwill@seventransistorlabs.com> wrote: > > >You're trying to ask, > > > >"My car pulls slightly to the right on the highway. To people who > >understand automobiles: what are the physical mechanisms that could do > >that?" > > > >You already very well know, there are a hundred things in either case > >which could individually explain it, all of which depend utterly on the > >internal construction of the system. The design notes of which are > >unspecified and unavailable, so it's useless to even ask. > > > >And more than likely, it's not even the fault of the system at all, but > >"did you notice your left arm is shorter than your right?", or, "no > >wonder, your right tires are balled". Like the resistors others have > >mentioned. > > > >Come on John, you should know better than to ask such silly questions to a > >public group. If you just want to give fodder to JT, why don't you e-mail > >him and save us the trouble. > > > >Tim > > As I stated, I am interested in the mechanisms that can make analog > ICs drift. The only silly thing about my question was asking it here, > where nobody seems to know much about semiconductor physics. >Some information on the subject: http://www.ti.com/lit/an/sloa059/sloa059.pdf Have you tried to do thermal cycling on a part, with a lot of cycles per day, that should accelerate the drift, since on of the stated reasons for drift in VOS is the thermal expansion of the die Cheers Klaus
