On Tuesday, September 23, 2014 8:24:06 PM UTC-7, josephkk wrote:> On Sat, 20 Sep 2014 06:48:52 -0700 (PDT), edward.ming.lee@gmail.com wrote=:>=20 > >>Actually, this is too unstable. The FSM would work if it's already in =one of the 6 states, out of 64. But if it's not, it won't drop in. I am s= witching to decoding a 3 bits Johnson counter:>=20 > >> > Q0 :=3D Q1 > >> > Q1 :=3D Q2 > >> > Q2 :=3D /Q0 =20 > >> > AHI =3D Q2 * /Q1 * /Q0 + Q2 * Q1 * /Q0 > >> > ALO =3D /Q2 * Q1 * Q0 + /Q2 * /Q1 * Q0 > >> > BHI =3D /Q2 * /Q1 * /Q0 + /Q2 * /Q1 * Q0 > >> > BLO =3D Q2 * Q1 * /Q0 + Q2 * Q1 * Q0 > >> > CHI =3D Q2 * Q1 * Q0 + /Q2 * Q1 * Q0 > >> > CLO =3D /Q2 * /Q1 * /Q0 + Q2 * /Q1 * /Q0 >=20 > >> >> You might also think about whether you need any "dead time" at the =clock transition to prevent currents flowing in unexpected ways...>=20 > >> >In that case, it would be 6 bits 12 states Johnson, with alternating =rest state. The Johnson counter should work in theory, but the open source= galemu is not showing the right output. The emulator could be wrong. I a= m still digging up old books and web pages to verify the design by hand.>=20 > >> I know it is a test book nit, but guard against 010/101 states. >=20 > >It should transition to a valid state within one or two clock pulses. A=s long as the outputs are zero during the invalid states, we are OK.>=20 > But it does not. Check it out. Then talk.Yes, it does not. That's why we need a CLR to bring it back to 000. D5 is= ENB and D6 is CLR in this diagram: http://173.224.223.62/motor/wave.jpg
BLDC controller and ATF16V8B/GAL16V8B/PAL16V8B
Started by ●September 17, 2014
Reply by ●September 24, 20142014-09-24
Reply by ●September 24, 20142014-09-24
On 2014-09-24, edward.ming.lee@gmail.com <edward.ming.lee@gmail.com> wrote:> On Tuesday, September 23, 2014 8:24:06 PM UTC-7, josephkk wrote: >> On Sat, 20 Sep 2014 06:48:52 -0700 (PDT), edward.ming.lee@gmail.com wrote: >> >> >>Actually, this is too unstable. The FSM would work if it's already in one of the 6 states, out of 64. But if it's not, it won't drop in. I am switching to decoding a 3 bits Johnson counter: >> >> >> > Q0 := Q1 >> >> > Q1 := Q2 >> >> > Q2 := /Q0>> But it does not. Check it out. Then talk. > > Yes, it does not. That's why we need a CLR to bring it back to 000. D5 is ENB and D6 is CLR in this diagram:nah, you just an escape from the illegal states.. Q1=Q2*(/Q0 + Q1)> http://173.224.223.62/motor/wave.jpg-- umop apisdn --- news://freenews.netfront.net/ - complaints: news@netfront.net ---
Reply by ●September 24, 20142014-09-24
> nah, you just an escape from the illegal states.. > > Q1=Q2*(/Q0 + Q1)Thanks, it works, but with a twist. I have to use up the last macro cell Q9. Macro cell Q6 Q7 Q8 corresponds to the Johnson state machine. Starting with /Q7=1: http://173.224.223.62/motor/wave1.jpg /Q9 goes low: http://173.224.223.62/motor/wave2.jpg /Q6 /Q7 /Q8 go low: http://173.224.223.62/motor/wave3.jpg /Q8 go back high: http://173.224.223.62/motor/wave4.jpg Unfortunately, during these 4 cycles, all the outputs are high. The problem is due to the negative logic. Now, i have to figure out how to deal with invalid outputs, rather than invalid states. Perhaps the gate drivers can handle it and block both high and low sides active. If not, i have to figure out how to enable the GAL22V10 output inverters.
