> > Mr. Johnson might be better. No chance of KILL (HI and LO on) output s=tates.>=20 > > Q0 :=3D Q1 > > Q1 :=3D Q2 > > Q2 :=3D /Q0 =20 >=20 > Is there room for 3 d-flops in the chip? the only state is in the output=metacells and there are only 2 spares, Have to use the bigger chip GAL22V10 with 10 registers/outputs. They are a= bout $1. Lattice stops making them, but there are plenty of existing new a= nd used stock. Atmel is still making ATF22V10. But the high voltage progr= ammed parts tends to keep the configuration data better.> also if you start that with 0,1,0 it alternates with 1,0,1=20Also need to feed the asynchronous clear from these states. Fortunately, t= hese states are less likely to happen by itself. 000 and 111 are more like= ly.> So instead of Johnson using a binary counter with bit 2 (value 4) connec=ted to the ALO output might work better, except for the glitches :( Or value 6 with asynchronous clear.
BLDC controller and ATF16V8B/GAL16V8B/PAL16V8B
Started by ●September 17, 2014
Reply by ●September 21, 20142014-09-21
Reply by ●September 21, 20142014-09-21
> > It should transition to a valid state within one or two clock pulses.> Ideally should, as desctibed above, does not..Yes, will need a clear input and output disable (for PWM current control)> As long as the outputs are zero during the invalid states, we are OK. > Yes, "no drive" is better than "a fire", =20Q5 to Q0 should be off with invalid states.> > The driving frequency is 3x the RPM cycle. > word salad. >=20 > the counter clock frequency is 6 times the rotational frequency, Or in dr=ive frequency in Hertz is 360 time the spindle speed in RPM Yes, my mind was driven with 3 phases at that time. Should be 6x. The 10 cells GAL22V10 would be ideal, with 6 phase drivers, 3 FSM bits, 1 C= lear bit and 1 output enable. However, I can only simulate the 8 cell PAL1= 6R8 for the moment. I am still rev. eng. the PALs and GALs. BTW, there do= esn't seems to be any different between clocked ":=3D" and unclocked "=3D" = equations, as least for PAL16R8. PAL16R8 compiled with PALASM20.for (c)1983 MMI on Linux f77/f2c. GAL22V10 compiled with fgal assembler (c)1997 ChaN on Win 7 dos. PAL16R8 Jedec bit stream simulated with sim (c)2014 on Linnix. /Q8 :=3D /Q6 * /I0 # JSM2 I0 =3D Clea= r /Q7 :=3D Q8 * /I0 # JSM1 /Q6 :=3D Q7 * /I0 # JSM0 /Q5 =3D Q8 * /Q7 * /Q6 + Q8 * Q7 * /Q6 # Q5 =3D AH /Q4 =3D /Q8 * Q7 * Q6 + /Q8 * /Q7 * Q6 # Q4 =3D AL /Q3 =3D /Q8 * /Q7 * /Q6 + /Q8 * /Q7 * Q6 # Q3 =3D BH /Q2 =3D Q8 * Q7 * /Q6 + Q8 * Q7 * Q6 # Q2 =3D BL /Q1 =3D Q8 * Q7 * Q6 + /Q8 * Q7 * Q6 # Q1 =3D CH /Q0 =3D /Q8 * /Q7 * /Q6 + Q8 * /Q7 * /Q6 # Q0 =3D CL _____ _____ _____ _____ _____ =20 /8/ \_____/ \_____/ \_____/ \_____/ \____ _____ _____ _____ _____ _____ =20 /7\_/ \_____/ \_____/ \_____/ \_____/ \_ _____ _____ _____ _____ ____ /6\___/ \_____/ \_____/ \_____/ \_____/ =20 ___ ___ ___ ___ ___=20 /5\_/ \_______/ \_______/ \_______/ \_______/ \__ ___ ___ ___ ___ =20 /4\_______/ \_______/ \_______/ \_______/ \_______/ _ ___ ___ ___ ___ =20 /3/ \_______/ \_______/ \_______/ \_______/ \______ ___ ___ ___ ___ ___ /2\___/ \_______/ \_______/ \_______/ \_______/ =20 ___ ___ ___ ___ _ /1\_____/ \_______/ \_______/ \_______/ \_______/
Reply by ●September 22, 20142014-09-22
On 09/21/2014 04:56 PM, edward.ming.lee@gmail.com wrote: [...]> > Or value 6 with asynchronous clear. >Be sure to test the output states and reset on actual hardware. From what I remember, PALASM(the version from the web) requires some hacking to get the output polarities right...
Reply by ●September 22, 20142014-09-22
On Monday, September 22, 2014 12:27:21 AM UTC-7, Johann Klammer wrote:> On 09/21/2014 04:56 PM, edward.ming.lee@gmail.com wrote: >=20 > [...] >=20 > > Or value 6 with asynchronous clear. >=20 > Be sure to test the output states and reset on actual hardware. From what=I remember, PALASM(the version from the web) requires some hacking to get = the output polarities right... The problem is PALASM's design of active low logic. However, it should not= stop us from using external pull-up active high, since it's only driving M= OSFET gate anyway. I tried adding GAL22V10 to it, but the original code ba= se is not very flexible, I ended up rewriting a limited simulator (only 2 = out of 8 product terms) and probably the synthesizer eventually,
Reply by ●September 22, 20142014-09-22
On 09/22/2014 04:24 PM, edward.ming.lee@gmail.com wrote:> On Monday, September 22, 2014 12:27:21 AM UTC-7, Johann Klammer wrote: >> On 09/21/2014 04:56 PM, edward.ming.lee@gmail.com wrote: >> >> [...] >> >>> Or value 6 with asynchronous clear. >> >> Be sure to test the output states and reset on actual hardware. From whatI remember, PALASM(the version from the web) requires some hacking to get the output polarities right...> > The problem is PALASM's design of active low logic. However, it shouldnot stop us from using external pull-up active high, since it's only driving MOSFET gate anyway. I tried adding GAL22V10 to it, but the original code base is not very flexible, I ended up rewriting a limited simulator (only 2 out of 8 product terms) and probably the synthesizer eventually,>Sorry, there seem to be multiple versions of PALASM on the net... I was using the binaries(for DOS, works in dosbox). It's also on the web. Supports 22V10 but needs some lattice tool, paltogal, which can also be found on the net, to convert to GAL format. That one caused me problems with 22V10. there's also other software around(that I haven't tried). *ChaNs FGAL *Atmel's WinCUPL. No need to register to use the cmdline tools, will run in wine. but has different syntax. *GALASM <https://github.com/dwery/galasm> For simulating I've tried galpal. <https://github.com/ezrec/galpal> (works via verilog) I've forked it to fix a bug in 22V10 simulation, add timing and a testvector generator. <https://github.com/klammerj/galpal> I did not bother to verify on actual hardware, so it may still be broken....
Reply by ●September 22, 20142014-09-22
On 09/21/2014 04:37 AM, edward.ming.lee@gmail.com wrote:> On Saturday, September 20, 2014 12:33:58 PM UTC-7, Don Y wrote: >> On 9/20/2014 12:07 PM, Lasse Langwadt Christensen wrote: >> >>> but what's the point? it's just more unnecessary hardware six pins on a micro and you are done >> >> You can put an MCU on the board in less space and for less total cost (DM+DL) than an MCU *and* aPAL/GAL! Just condition the outputs (pullups/downs/inverters/buffers) so the MCU's outputs can't sit in an unhappy state if the MCU refuses to start up.> > The micro needs to be in two different places. So, it's either micro + micro or micro + gal/pal. > >> Bring the smarts *into* the field instead of dealing with cables, etc. (what happens if the cable is unplugged?) > > Then no signal, and the motor would be free running, or stop eventually. >With the block commutation that you seem to be doing, you can try to add another input to the GAL for PWM and combine that signal with the driver outputs for the upper FETs. Using a small uC is probably a better Idea. you just need power and UART lines...
Reply by ●September 22, 20142014-09-22
Den mandag den 22. september 2014 16.24.21 UTC+2 skrev edward....@gmail.com= :> On Monday, September 22, 2014 12:27:21 AM UTC-7, Johann Klammer wrote: >=20 > > On 09/21/2014 04:56 PM, edward.ming.lee@gmail.com wrote: >=20 > >=20 >=20 > > [...] >=20 > >=20 >=20 > > > Or value 6 with asynchronous clear. >=20 > >=20 >=20 > > Be sure to test the output states and reset on actual hardware. From wh=at I remember, PALASM(the version from the web) requires some hacking to ge= t the output polarities right...>=20 >=20 >=20 > The problem is PALASM's design of active low logic. However, it should n=ot stop us from using external pull-up active high, since it's only driving= MOSFET gate anyway. I tried adding GAL22V10 to it, but the original code = base is not very flexible, I ended up rewriting a limited simulator (only = 2 out of 8 product terms) and probably the synthesizer eventually, So you are going to use an obsolete GAL with half baked or broken tools and= no programmer, then add a bunch of hardware to detect multiple logic level= s=20 to do the job that is much better served by 6 pins on a micro or at worst a= =20 $0.50 micro ? What is the logic behind that? -Lasse
Reply by ●September 22, 20142014-09-22
=20> > The problem is PALASM's design of active low logic. However, it should=not stop us from using external pull-up active high, since it's only drivi= ng MOSFET gate anyway. I tried adding GAL22V10 to it, but the original cod= e base is not very flexible, I ended up rewriting a limited simulator (onl= y 2 out of 8 product terms) and probably the synthesizer eventually,>=20 > So you are going to use an obsolete GAL with half baked or broken toolsGalasm works fine for GAL22V10. Atmel is still making the compatible ATF22= V10.> and no programmer,=20We can buy the chip with it pre-programmed. Once programmed, we don't expe= ct to change this code much.> then add a bunch of hardware to detect multiple logic levels to do the jo=b that is much better served by 6 pins on a micro or at worst a $0.50 micro= ? We would still drive this and others (for example, an LED counter) from a s= ingle micro. BTW, i never found any usable micro for $0.50.
Reply by ●September 22, 20142014-09-22
Den mandag den 22. september 2014 22.59.56 UTC+2 skrev edward....@gmail.com= :> > > The problem is PALASM's design of active low logic. However, it shou=ld not stop us from using external pull-up active high, since it's only dri= ving MOSFET gate anyway. I tried adding GAL22V10 to it, but the original c= ode base is not very flexible, I ended up rewriting a limited simulator (o= nly 2 out of 8 product terms) and probably the synthesizer eventually,>=20 > >=20 >=20 > > So you are going to use an obsolete GAL with half baked or broken tools >=20 >=20 >=20 > Galasm works fine for GAL22V10. Atmel is still making the compatible ATF=22V10.>=20 >=20 >=20 > > and no programmer,=20 >=20 >=20 >=20 > We can buy the chip with it pre-programmed. Once programmed, we don't ex=pect to change this code much.>=20 >=20 >=20 > > then add a bunch of hardware to detect multiple logic levels to do the =job that is much better served by 6 pins on a micro or at worst a $0.50 mic= ro ?>=20 >=20 >=20 > We would still drive this and others (for example, an LED counter) from a=single micro. BTW, i never found any usable micro for $0.50. so you'll go through all that trouble just to (maybe) save a few pins on=20 a micro? if you buy one no, if you buy a few 1000 you can get a 48MHz Cortex=AE-M0 f= or $0.50 In singles $1.50 will buy you an AVR that Atmel has already written code fo= r=20 to drive a BLDC sensorless=20 -Lasse
Reply by ●September 22, 20142014-09-22
On Monday, September 22, 2014 2:32:27 PM UTC-7, Lasse Langwadt Christensen = wrote:> Den mandag den 22. september 2014 22.59.56 UTC+2 skrev edward....@gmail.c=om:>=20 > > > > The problem is PALASM's design of active low logic. However, it sh=ould not stop us from using external pull-up active high, since it's only d= riving MOSFET gate anyway. I tried adding GAL22V10 to it, but the original= code base is not very flexible, I ended up rewriting a limited simulator = (only 2 out of 8 product terms) and probably the synthesizer eventually,>=20 > > > So you are going to use an obsolete GAL with half baked or broken too=ls=20>Galasm works fine for GAL22V10. Atmel is still making the compatible ATF2=2V10. and no programmer,=20>=20 > > We can buy the chip with it pre-programmed. Once programmed, we don't =expect to change this code much.>=20 > > > then add a bunch of hardware to detect multiple logic levels to do th=e job that is much better served by 6 pins on a micro or at worst a $0.50 m= icro ?>=20 > > We would still drive this and others (for example, an LED counter) from=a single micro. BTW, i never found any usable micro for $0.50.>=20 > so you'll go through all that trouble just to (maybe) save a few pins on =a micro? To avoid programming multiple micros.>=20 > if you buy one no, if you buy a few 1000 you can get a 48MHz Cortex=AE-M0=for $0.50 =20> In singles $1.50 will buy you an AVR that Atmel has already written code =for to drive a BLDC sensorless=20 This would be a dedicated micro. We still need to figure out how to commun= icate between this and the main micro.
