On Fri, 30 May 2014 18:18:57 -0700, josephkk <joseph_barrett@sbcglobal.net> wrote:>On Fri, 30 May 2014 16:02:21 +0100, "Kevin Aylward" ><ExtractkevinRemove@kevinaylward.co.uk> wrote: > >>"josephkk" wrote in message >>news:78rfo9tv2o96hobi7nlts8e221c3co93g2@4ax.com... >> >> >>>>Name a deficiency. >>> >>>Well, for one its a bloody 1G download, which I have just done to see >>>whether or not my considerations are valid. I haven't use PSpice for over >>>10 >>>years. >>> >>>>I will give it a look over. It doesn't look like it can install in >>>>Program >>>>Files. I pressed the install, and now notice it installed in C:\ This is >>>>pretty much unacceptable for seconds. Assuming, as it looks, that >>>>everything >>>>is installed there, and that only one of those files gets modified by the >>>>program, it wont run as it should if installed in program files. >>> >>>Non-issue. Lotus notes did not install in "Program Files" long after the >>>issues were solved simply because it was not needed, the install in >>>C:\Notes worked too well to bother changing it. >> >>Its fingers nails down the blackboard. Programs/Software writers should know >>how to write programs that correctly use the operating system. >> >>The Program Files and Program Data directories are a good idea, and most >>competent programs use them correctly. >> >>> >>>>Does it have an equivalent to Cadences "view switch"? That is, the ability >>>>to to switch with one change what set of schematics is actually attached >>>>to >>>>their symbols? >> >>>Is that something like the standard hierarchal view that many tools >>>provide? >> >>No. View switches are indispensible for doing full chip design. One key >>function is that it allows all the lowest level transistor level schematic >>to be switched with a behavioural version allowing 1000 times faster >>functional simulations of the full chip, but still using full pin for pin >>and routing matching. >> >>> >>>>Spent 15 mins so far, and cant even get an example schematic displayed. >> >>>Silly comment. >> >>Nonsense. >> >>>Some 20 years ago i had to learn Microstation out of >>>books. It was about 3 days to get enough down to get basic functionality >>>working and about 3 months to get to basic proficiency. Ecpecting to >>>learn an equally complex program in 15 minutes is inappropriate. >>> >> >>Erhammm... well... I do know a tad about simulation, er.. hint: SuperSpice. >> >>A program should not be complex to use, irrespective of internal complexity. >> >>If a *schematic* *program* loads in its project file, it is absolutely >>nonsensical that the *schematic* does not get immediately displayed. The >>"Schematic" folder is not even visible in its file trees until "Design >>Resources is opened". The schematic is the driver. >> >>Kevin Aylward B.Sc. >>www.kevinaylward.co.uk >>www.anasoft.co.uk - SuperSpice >> >I am mighty sure that JT does not have that experience because he does NOT >use what he calls it "Crapture". Please try the tools he actually uses >for a fair comparison. If i thought i could get a copy of his tools from >him i would be at his place mighty fast. > >?-) >You can. Surf for PSpice Student Version... that'll have the schematic capture I use. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Headphone amp simulation
Started by ●May 26, 2014
Reply by ●May 30, 20142014-05-30
Reply by ●May 31, 20142014-05-31
>"josephkk" wrote in message >news:aabio99qunakhi9sl7ok0ibg8uttqubuo8@4ax.com...>>If a *schematic* *program* loads in its project file, it is absolutely >>nonsensical that the *schematic* does not get immediately displayed. The >>"Schematic" folder is not even visible in its file trees until "Design >>Resources is opened". The schematic is the driver.>I am mighty sure that JT does not have that experience because he does NOT >use what he calls it "Crapture". Please try the tools he actually uses >for a fair comparison. If i thought i could get a copy of his tools from >him i would be at his place mighty fast.As noted elsewhere, I have yet to be able to get PSpice Schematics to install. I used it 15 years ago, and I thought it was very good for PCB based Analog design, which is what I did then. I don't believe that it has the hooks that pro ic design tools have. For example, a "Fully Integrated" system like Cadence has Schematics and Layout all "integrated". Layout to Schematic verification (LVS) is pretty much a button press. x-probing layout to schematic is button presses. Parasitic extraction to schematic simulation with those parasitics is button presses. Schematic/Layout design reviews are significantly harder with a hodge podge of disparate tools and much more likely to result in errors. Its key to be able to do top level simulations and know that the schematic being simulated is exactly the same one as in layout. 1 wire off in millions will fail the chip and cost a huge bunch of green ones. No one in their right mind would design a uP with layout and design in two different data bases. I just don't see it as debatable that tools such as PSpice with mix and match layout tools is viable for general, professional mainstream IC design, and that is why, by and large, no one does it. They spend the money on Cadence and Mentor, because it is truly what is actually needed when a mask set costs �1M+. There are to many other issues to enumerate, but one other example, PSpice does not have Periodic Steady State Phase Noise. This makes it, essentially, impossible to reliably, 1st time pass, design any system where phase noise matters. Kevin Aylward B.Sc. www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
Reply by ●May 31, 20142014-05-31
"Maynard A. Philbrook Jr." wrote in message news:MPG.2df2abc1febfdeab989904@news.eternal-september.org... In article <sZ6dneIAv-Q6SRXOnZ2dnUVZ8mqdnZ2d@bt.com>, ExtractkevinRemove@kevinaylward.co.uk says...> > You are an exception... > >> ASIC design is done in teams. It needs a common database and environment >> where all can work (and view) on different schematics and layouts of the >> same project all at the same time, with appropriate automatic file >> locking.> Then i guess you don't use Windows much on that level :)Indeed, at that level its all Linux/Unix. I do use SuperSpice on Windows as a complement to the main work though. Kevin Aylward B.Sc. www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
Reply by ●May 31, 20142014-05-31
On Fri, 30 May 2014 15:53:22 -0400, "Maynard A. Philbrook Jr." <jamie_ka1lpa@charter.net> wrote:>In article <sZ6dneIAv-Q6SRXOnZ2dnUVZ8mqdnZ2d@bt.com>, >ExtractkevinRemove@kevinaylward.co.uk says... >> >> You are an exception... >> >> ASIC design is done in teams. It needs a common database and environment >> where all can work (and view) on different schematics and layouts of the >> same project all at the same time, with appropriate automatic file locking. >> >> Kevin Aylward B.Sc. >> www.kevinaylward.co.uk >> www.anasoft.co.uk - SuperSpice > > Then i guess you don't use Windows much on that level :) >Version control databases are available on Windows, too. CVS, for example, is available on many platforms, as is Agile.
Reply by ●May 31, 20142014-05-31
>-----Original Message----- >From: Jim Thompson >Sent: Friday, May 30, 2014 7:26 PM Newsgroups: sci.electronics.design >Subject: Re: Headphone amp simulation> <http://www.analog-innovations.com/SED/Sample_Custom_Chip_Design.pdf>Main Bias Generator: I'm guessing that VREF is around 1.25V, giving 100ua in your master bias generator outputs. That seems rather high. Not a low power product I gather? 1ua is usually the norm. I like to draw the bias generator transistors in Cadence parallel device ref designator notation of e.g. M1<10:0> with a buss output ibias<10:0>. It makes it easier to add and subtract sources as the design progresses by changing 1 number instead re-drawing. It looks like all transistors are connected as isolated devices with source to their backgates. For diff pairs I would do that, but for the bias cascodes, I would typically use non isolated to save space. Off hand, the start-up current turn off (Q1 diode) looks a tad interesting. Relies on having a large double Vgs on the cascode bias transistors so that VBIAS > VCC - Vbe. So, VBIAS wants to be high to ensure turn off, but this limits the output voltage operation range of the current sources. Oh...its VDD not VCC. This shows your bipolar disorder age... Kevin Aylward B.Sc. www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
Reply by ●May 31, 20142014-05-31
On Sat, 31 May 2014 08:35:37 +0100, "Kevin Aylward" <ExtractkevinRemove@kevinaylward.co.uk> wrote:>>"josephkk" wrote in message >>news:aabio99qunakhi9sl7ok0ibg8uttqubuo8@4ax.com... > >>>If a *schematic* *program* loads in its project file, it is absolutely >>>nonsensical that the *schematic* does not get immediately displayed. The >>>"Schematic" folder is not even visible in its file trees until "Design >>>Resources is opened". The schematic is the driver. > >>I am mighty sure that JT does not have that experience because he does NOT >>use what he calls it "Crapture". Please try the tools he actually uses >>for a fair comparison. If i thought i could get a copy of his tools from >>him i would be at his place mighty fast. > >As noted elsewhere, I have yet to be able to get PSpice Schematics to >install. I used it 15 years ago, and I thought it was very good for PCB >based Analog design, which is what I did then. I don't believe that it has >the hooks that pro ic design tools have. > >For example, a "Fully Integrated" system like Cadence has Schematics and >Layout all "integrated". Layout to Schematic verification (LVS) is pretty >much a button press. x-probing layout to schematic is button presses. >Parasitic extraction to schematic simulation with those parasitics is button >presses. Schematic/Layout design reviews are significantly harder with a >hodge podge of disparate tools and much more likely to result in errors. Its >key to be able to do top level simulations and know that the schematic being >simulated is exactly the same one as in layout. 1 wire off in millions will >fail the chip and cost a huge bunch of green ones. No one in their right >mind would design a uP with layout and design in two different data bases. > >I just don't see it as debatable that tools such as PSpice with mix and >match layout tools is viable for general, professional mainstream IC design, >and that is why, by and large, no one does it. They spend the money on >Cadence and Mentor, because it is truly what is actually needed when a mask >set costs �1M+. > >There are to many other issues to enumerate, but one other example, PSpice >does not have Periodic Steady State Phase Noise. This makes it, essentially, >impossible to reliably, 1st time pass, design any system where phase noise >matters. > >Kevin Aylward B.Sc. >www.kevinaylward.co.uk >www.anasoft.co.uk - SuperSpiceI'm sure it matters a lot in automotive and industrial control systems>:-}LVS is what everyone _not_ in the know throws out there as the reason you need Cadence. Baloney! I can effortlessly and error-free generate any netlist syntax known to man... get an _old_ copy of PSpice (before the ruination of OrCAD and Cadence) and look up "templates". If I couldn't, how did this... <http://www.analog-innovations.com/SED/Sample_Custom_Chip_Design.pdf> get laid out, masks made, processed, packaged, and come up working first pass ?>:-} And one I can't yet show (NDA hasn't expired), summer of 2011, I had an on-site gig in Huntington, Long Island (where I sipped a few with Martin Riddle :-). Carried my little Lenovo laptop with me. Customer had the full Cadence toolset. I quickly showed that I could run circles around the Cadence stuff using my laptop, so I designed all the analog portions of the chip (Mark Tse did the digital... another analog contractor on the team bailed because he couldn't keep up... besides he was of the "every function requires an OpAmp" crowd :-) A junior engineer (older than me :-) was assigned to transfer it to Cadence for documentation purposes, but layout was done using my LVS netlists. Worked first pass! ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●May 31, 20142014-05-31
On Sat, 31 May 2014 15:46:48 +0100, "Kevin Aylward" <ExtractkevinRemove@kevinaylward.co.uk> wrote:>>-----Original Message----- >>From: Jim Thompson >>Sent: Friday, May 30, 2014 7:26 PM Newsgroups: sci.electronics.design >>Subject: Re: Headphone amp simulation > >> <http://www.analog-innovations.com/SED/Sample_Custom_Chip_Design.pdf> > >Main Bias Generator: > >I'm guessing that VREF is around 1.25V, giving 100ua in your master bias >generator outputs. That seems rather high. Not a low power product I gather? >1ua is usually the norm.Depends on the application and the resistor types available. A trade-off between resistor area and current consumption.> >I like to draw the bias generator transistors in Cadence parallel device ref >designator notation of e.g. M1<10:0> with a buss output ibias<10:0>. It >makes it >easier to add and subtract sources as the design progresses by changing 1 >number instead re-drawing. > >It looks like all transistors are connected as isolated devices with source >to their backgates. For diff pairs I would do that, but for the bias >cascodes, I would typically use non isolated to save space.Accuracy was the driving force here. (VGA)> >Off hand, the start-up current turn off (Q1 diode) looks a tad interesting. >Relies on having a large double Vgs on the cascode bias transistors so that >VBIAS > VCC - Vbe. So, VBIAS wants to be high to ensure turn off, but this >limits the output voltage operation range of the current sources. > >Oh...its VDD not VCC. This shows your bipolar disorder age...Shows your ignorance, VCC is for analog, VDD for digital.> >Kevin Aylward B.Sc. >www.kevinaylward.co.uk >www.anasoft.co.uk - SuperSpiceYou're becoming a horse's ass approaching Larkin-level. What's your problem? ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●May 31, 20142014-05-31
In article <b5rjo95uttogfb33gj2s9sqvge8871be74@4ax.com>, To-Email-Use- The-Envelope-Icon@On-My-Web-Site.com says...> I'm sure it matters a lot in automotive and industrial control systems > >:-} > > LVS is what everyone _not_ in the know throws out there as the reason > you need Cadence. Baloney! I can effortlessly and error-free > generate any netlist syntax known to man... get an _old_ copy of > PSpice (before the ruination of OrCAD and Cadence) and look up > "templates". > > If I couldn't, how did this... > > <http://www.analog-innovations.com/SED/Sample_Custom_Chip_Design.pdf> > > get laid out, masks made, processed, packaged, and come up working > first pass ?>:-} > > And one I can't yet show (NDA hasn't expired), summer of 2011, I had > an on-site gig in Huntington, Long Island (where I sipped a few with > Martin Riddle :-). Carried my little Lenovo laptop with me. Customer > had the full Cadence toolset. I quickly showed that I could run > circles around the Cadence stuff using my laptop, so I designed all > the analog portions of the chip (Mark Tse did the digital... another > analog contractor on the team bailed because he couldn't keep up... > besides he was of the "every function requires an OpAmp" crowd :-) A > junior engineer (older than me :-) was assigned to transfer it to > Cadence for documentation purposes, but layout was done using my LVS > netlists. Worked first pass! > > ...Jim Thompson > -- > >I don't know what the world is going to do with out you Jim? guess we'll have to go back to morse code and dry cell batteries to communicate! At least all you need there is some wire wrapped around a thread bobbin held in place via a nail with the spring hammer hanging on top. Jamie
Reply by ●May 31, 20142014-05-31
"Jim Thompson" wrote in message news:b5rjo95uttogfb33gj2s9sqvge8871be74@4ax.com... On Sat, 31 May 2014 08:35:37 +0100, "Kevin Aylward" <ExtractkevinRemove@kevinaylward.co.uk> wrote:>>"josephkk" wrote in message >>news:aabio99qunakhi9sl7ok0ibg8uttqubuo8@4ax.com... >>LVS is what everyone _not_ in the know throws out there as the reason >you need Cadence. Baloney! I can effortlessly and error-free >generate any netlist syntax known to man... get an _old_ copy of >PSpice (before the ruination of OrCAD and Cadence) and look up >"templates".>If I couldn't, how did this...I am not claiming that its absolutely impossible to do without a full integrated system in all cases, I am saying that it is much, much harder, such that it is not really a realistic option for mainstream professional design. Its pretty much a non debateable fact that designing a modern uP would without the appropriate tools would be impossible. PSpice and micky mouse layout tools just wont cut it there.>Cadence for documentation purposes, but layout was done using my LVS >netlists. Worked first pass!So, you were not doing 10 GHz with parasitic extraction then. Kevin Aylward B.Sc. www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
Reply by ●May 31, 20142014-05-31
>"Jim Thompson" wrote in message >news:6jsjo95p6dklru3r8d4lb12f18ulumt1q7@4ax.com...>Shows your ignorance, VCC is for analog, VDD for digital.Oh... ? VCC - Voltage Collector Collector, VDD Voltage Drain Drain, VEE Emitter Emitter, VSS Voltage Source Source older guys = bipolar design = VCC/VEE younger guys = mos design = VDD/VSS I have never heard of any reference to VDD as a digital designator. When was TTL ever VDD ? Kevin Aylward B.Sc. www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
