SP > AFAIUI chips are normally passivated SP > (there's effectively a layer of glass- SP > actually SiOx/SiNx- on top of the SP > chip with "holes" for the bonding pads. SP > Conformal coating at the chip level. SP > So, moisture is unlikely to be an SP > issue in a low impedance circuit. Did somebody skip that process on a batch? Was Mr. Larkin's high temp bake hot enough to have that annealing effect you described?
Never Buy Maxim (again)
Started by ●October 13, 2013
Reply by ●October 17, 20132013-10-17
Reply by ●October 17, 20132013-10-17
Reply by ●October 17, 20132013-10-17
On Thu, 17 Oct 2013 11:01:10 -0700, John Larkin <jlarkin@highlandtechnology.com> wrote:>On Wed, 16 Oct 2013 19:54:29 -0700, miso <miso@sushi.com> wrote: > >>On 10/15/2013 7:09 AM, John Larkin wrote: >>> On Mon, 14 Oct 2013 21:53:29 -0700, miso <miso@sushi.com> wrote: >>> >>>> On 10/14/2013 2:51 PM, John Larkin wrote: >>>>> On Mon, 14 Oct 2013 17:20:03 -0400, "tm" <No_one_home@white-house.gov> >>>>> wrote: >>>>> >>>>>> >>>>>> "miso" <miso@sushi.com> wrote in message >>>>>> news:l3hi8e$ql7$1@speranza.aioe.org... >>>>>>> On 10/13/2013 12:34 PM, John Larkin wrote: >>>>>>>> >>>>>>>> These opamps, like most Maxim parts, have nonstandard pinout. I built a >>>>>>>> test >>>>>>>> fixture to measure Cin. With power off, I measured 1.4 pF on the >>>>>>>> non-inverting >>>>>>>> input pin. >>>>>>> Who measures capacitance of a part that is powered down? Doh! There are >>>>>>> diodes that need to be reverse biased ya know. >>>>>>> >>>>>>> Do you have someone who works for you that is, well you know, a competent >>>>>>> electrical engineer? Perhaps you are not suited for electrical >>>>>>> engineering. Have you considered software? >>>>>>> >>>>>>> >>>>>>> >>>>>> >>>>>> It's called "characterizing the part". It is way beyond a libtard such as >>>>>> yourself to understand. >>>>>> >>>>> >>>>> I'm curious about things like ESD capacitance. Given a test setup, why >>>>> would anyone *not* want to measure the power-off capacitance, and then >>>>> determine the C-V behavior? >>>>> >>>>> >>>> >>>> ESD capacitance? We are now making up specifications? >>> >>> Don't be tedious. ESD capacitance is the capacitance of the ESD diodes. What >>> else would I be measuring? >> >>Unless you have a test structure, you are not measuring the capacitance >>of the ESD diodes, but rather whatever is on that pin, which would >>include the input device. [Most chips only use one diode these days >>since there is a tendency for boards with mixed supply voltages. Diodes >>to the positive rail can be a problem if the board designer is sloppy in >>supply sequencing (which is usually the case). >> >>> >>>> >>>> The ESD structure is part of the pin capacitance. However, nobody >>>> specifies the capacitance of the part that is not in a normal operating >>>> state. >>> >>> So that is, apparently, something that you adamantly don't want to ever measure >>> or know. Cover up that C-meter so you don't accidentally find out. >>> >>> >> >>I don't make useless measurements. > >I make all sorts of "useless" measurements. Some of them turn out to >be very useful. > >You define yourself by the things that you are not interested in.You define yourself by the BS you constantly spin. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●October 18, 20132013-10-18
On Thu, 17 Oct 2013 12:18:27 -0700 (PDT) Greegor <greegor47@gmail.com> wrote in Message id: <f736e03f-c852-4e35-8d95-1749de13a9a2@googlegroups.com>:> >In the middle 80's there were reports >of water droplets inside of DRAM chips >causing intermittent failures.I remember we were using 256kb DRAMs from TI that had a very high failure rate - is this what you're referring to?
Reply by ●October 18, 20132013-10-18
On Thursday, October 17, 2013 9:07:34 PM UTC-5, Greegor wrote:> ccon67 > Anyone knows why it didn't wake up? > > > > No activity power saver function?Input has its signal, so I wouldn't call this "no activity"
Reply by ●October 18, 20132013-10-18
G > In the middle 80's there were reports G > of water droplets inside of DRAM chips G > causing intermittent failures. JW > I remember we were using 256kb DRAMs JW > from TI that had a very high failure JW > rate - is this what you're referring to? It could be, but I was more curious about what the mechanism of failure was. How could water end up inside the chips? What caused the TI DRAMs to fail so much?
Reply by ●October 18, 20132013-10-18
ccon67> Anyone knows why it didn't wake up? G > No activity power saver function? ccon67> Input has its signal, so I wouldn't ccon67> call this "no activity" You hinted at the answer when you used words like "wake up" (or sleep?). LOL
Reply by ●October 18, 20132013-10-18
On 10/16/2013 10:06 PM, John Larkin wrote:>>> >> I wouldn't connect the capacitance meter until the circuit was powered up. > > Or just scrunch your eyes closed really, really hard, to minimize what you > learn. > >I don't give a shit about parts that are not powered up. Nor do I stare at my navel for hours on end.
Reply by ●October 18, 20132013-10-18
On 10/17/2013 7:27 AM, John Larkin wrote:>> And what did FA say? Well assuming you contacted them. It is quite easy >> to find damage to chips given tools like emission microscopes. Generally >> failed parts are due to the customer, and you can get some good >> diagnostics by asking the factory how the part failed. > > The outputs got erratic at high temperature, looked like a problem in the latch > circuit. As the parts aged, the fail temperature descended, ultimately reaching > room temp after about a year. All the parts did this. A good hi-temp bake would > push the fail temperature up, and it would begin slowly descending again from > there. What would cause that? > > Our first indication that something was wrong was when parts wouldn't ship, with > no explanation. Then the part was discontinued, delivery infinite days ARO, > again without explanation. That was about the time they started failing. > > I eventually found a guy at Maxim who explained the Minnesota problem. He sent > me 3000 samples of the MAX9691. The 9691 is a *comparator* with back-to-back > diodes across the inputs (!!!!???) which is why we had to make the adapter > boards. > >None of which answers what FA said.
Reply by ●October 18, 20132013-10-18
On 10/17/2013 7:02 PM, Greegor wrote:> SP > AFAIUI chips are normally passivated > SP > (there's effectively a layer of glass- > SP > actually SiOx/SiNx- on top of the > SP > chip with "holes" for the bonding pads. > SP > Conformal coating at the chip level. > SP > So, moisture is unlikely to be an > SP > issue in a low impedance circuit. > > Did somebody skip that process on a batch? > > Was Mr. Larkin's high temp bake hot enough > to have that annealing effect you described? >Passivation is CVD with a bit of thermal oxide. [This is foo only fab knows exactly.] It really isn't a bake. I can't speak for bipolar wafers, but ion contamination is usually the killer in MOS. When tweezers were actually tweezers (as in a mechanical device that gripped the wafer from the side), one dirty tweezer could whack a lot of wafers. You get a little sodium on the tweezer and it shoots right into the lattice. Tweezers have been vacuum devices that grip the back for some time. But it is possible VTC was a sloppy fab. Needless to say those photos of some CEO holding a wafer with their hands means that wafer was a junker in the first place.
