It is amazing at what they don't tell you at places where you are 
employed. If you don't need to know it, the fab will not tell you. [IBM 
wafer fabrication isn't exactly like the dog eat dog world of commercial 
semiconductors.] There are a number of latch-up prevention schemes I 
stumbled across having material companies do analysis. Probably the only 
one safe to reveal was one company that used to ion implant their wafers 
from the back to make what amounted to a low resistivity layer, like a 
faux epi wafer. This was easy to find since the sheet rho measured 
didn't match the published value. [The published value was at the 
surface of the wafer.] Since everyone uses real epi these days, there is 
no harm in revealing that one. Some companies use beta killing schemes, 
which could still be in use.

On 10/18/2013 4:29 PM, John Larkin wrote:
> On Fri, 18 Oct 2013 14:50:38 -0700, miso <miso@sushi.com> wrote:
>
>> On 10/16/2013 10:06 PM, John Larkin wrote:
>>>>>
>>>> I wouldn't connect the capacitance meter until the circuit was powered up.
>>>
>>> Or just scrunch your eyes closed really, really hard, to minimize what you
>>> learn.
>>>
>>>
>> I don't give a shit about parts that are not powered up.
>
>
> So you have no interest in diodes, resistors, capacitors, or
> inductors. And no interest in the C-V behavior of ESD diodes.
>
> Fine by me.
>
>

You are confusing passive and active components. Think before you post. 
Note I said "powered up." Think. You can do it.

Am 18.10.2013 18:07, schrieb Greegor:
> G > In the middle 80's there were reports
> G > of water droplets inside of DRAM chips
> G > causing intermittent failures.
>
> JW > I remember we were using 256kb DRAMs
> JW > from TI that had a very high failure
> JW > rate - is this what you're referring to?
>
> It could be, but I was more curious
> about what the mechanism of failure was.
>
> How could water end up inside the chips?

There was water set free when melting the
glass of those CERDIP packages ( the ones
made from top & bottom ceramic with a glass
layer in between where pins came out)
Often seen on Eproms.

There was no problem with the sidebrazed
ceramic packages.

regards, Gerhard

On Fri, 18 Oct 2013 09:07:36 -0700 (PDT) Greegor <greegor47@gmail.com>
wrote in Message id:
<a6a15603-4d43-4f3c-9df8-6c399bcdf2a3@googlegroups.com>:

>G > In the middle 80's there were reports
>G > of water droplets inside of DRAM chips
>G > causing intermittent failures. 
> 
>JW > I remember we were using 256kb DRAMs
>JW > from TI that had a very high failure
>JW > rate - is this what you're referring to?
> 
>It could be, but I was more curious
>about what the mechanism of failure was.
> 
>How could water end up inside the chips?
> 
>What caused the TI DRAMs to fail so much?

I have no idea, I was just wondering if that was what you were referring
to.

On 10/18/2013 8:11 PM, miso wrote:
> On 10/18/2013 3:24 PM, Phil Hobbs wrote:
>> On 10/18/2013 6:03 PM, miso wrote:
>>> On 10/17/2013 7:02 PM, Greegor wrote:
>>>> SP > AFAIUI chips are normally passivated
>>>> SP > (there's effectively a layer of glass-
>>>> SP > actually SiOx/SiNx- on top of the
>>>> SP > chip with "holes" for the bonding pads.
>>>> SP > Conformal coating at the chip level.
>>>> SP > So, moisture is unlikely to be an
>>>> SP > issue in a low impedance circuit.
>>>>
>>>> Did somebody skip that process on a batch?
>>>>
>>>> Was Mr. Larkin's high temp bake hot enough
>>>> to have that annealing effect you described?
>>>>
>>>
>>> Passivation is CVD with a bit of thermal oxide. [This is foo only fab
>>> knows exactly.] It really isn't a bake.
>>
>> Usually TEOS (tetraethyl orthosilicate) spin-on glass, I think, but
>> maybe sometimes LTO oxide.  It has to be low temperature because it's
>> going on top of the back end, so anything above about 300 C is verboten.
>>   (At least in the IBM processes I used to know about.)
>>
>> Cheers
>>
>> Phil Hobbs
>>
>>>
>>> I can't speak for bipolar wafers, but ion contamination is usually the
>>> killer in MOS. When tweezers were actually tweezers (as in a mechanical
>>> device that gripped the wafer from the side), one dirty tweezer could
>>> whack a lot of wafers. You get a little sodium on the tweezer and it
>>> shoots right into the lattice. Tweezers have been vacuum devices that
>>> grip the back for some time. But it is possible VTC was a sloppy fab.
>>>
>>> Needless to say those photos of some CEO holding a wafer with their
>>> hands means that wafer was a junker in the first place.
>>>
>>>
>>>
>>
>>
> Because passivation is a rel issue and not an electrical spec, nobody
> really tells you their foo. The only thing you can do is pay one of the
> valley materials labs and they will figure it out. But CVD variants are
> common, as is the silane process you mentioned.
>
> But after the wafer is diced, the side is now exposed. That is where
> more foo comes in. There is all sorts of foo in the scribe to keep (so
> they say) contaminants out. The scribe rules are proprietary in theory
> to the factory, but they can't be kept very secret since layout needs to
> know them, and of course the mask shop will know how you do your scribe.
> These rules are as secure as a NDA.
>
>

I used to work at IBM Research, where an enormous amount of the basic 
science and development for both advanced bipolar and CMOS was done.
(In fact, I had a fairly major HF leak from the fab upstairs into the 
core behind my lab at one point.)

When I branched out into silicon photonics a dozen or so years ago, I 
did my own process development, including writing dozens of my own run 
sheets for up to 300 process steps, front end and back end.  So I know a 
lot of the details without needing an NDA, though I'm nobody's idea of a 
CMOS expert.

It's amazing what you can get done when you can walk down the hall and 
bug the world's expert on some topic.  I used to share the back wall of 
my office with Bob Dennard, the inventor of DRAM among many other 
things, and there were others like him in many other fields.

Of course now there's a lot more software done there than hardware, but 
it was a great place to work back in the day.

Cheers

Phil Hobbs

-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058

hobbs at electrooptical dot net
http://electrooptical.net

On 10/18/2013 3:24 PM, Phil Hobbs wrote:
> On 10/18/2013 6:03 PM, miso wrote:
>> On 10/17/2013 7:02 PM, Greegor wrote:
>>> SP > AFAIUI chips are normally passivated
>>> SP > (there's effectively a layer of glass-
>>> SP > actually SiOx/SiNx- on top of the
>>> SP > chip with "holes" for the bonding pads.
>>> SP > Conformal coating at the chip level.
>>> SP > So, moisture is unlikely to be an
>>> SP > issue in a low impedance circuit.
>>>
>>> Did somebody skip that process on a batch?
>>>
>>> Was Mr. Larkin's high temp bake hot enough
>>> to have that annealing effect you described?
>>>
>>
>> Passivation is CVD with a bit of thermal oxide. [This is foo only fab
>> knows exactly.] It really isn't a bake.
>
> Usually TEOS (tetraethyl orthosilicate) spin-on glass, I think, but
> maybe sometimes LTO oxide.  It has to be low temperature because it's
> going on top of the back end, so anything above about 300 C is verboten.
>   (At least in the IBM processes I used to know about.)
>
> Cheers
>
> Phil Hobbs
>
>>
>> I can't speak for bipolar wafers, but ion contamination is usually the
>> killer in MOS. When tweezers were actually tweezers (as in a mechanical
>> device that gripped the wafer from the side), one dirty tweezer could
>> whack a lot of wafers. You get a little sodium on the tweezer and it
>> shoots right into the lattice. Tweezers have been vacuum devices that
>> grip the back for some time. But it is possible VTC was a sloppy fab.
>>
>> Needless to say those photos of some CEO holding a wafer with their
>> hands means that wafer was a junker in the first place.
>>
>>
>>
>
>
Because passivation is a rel issue and not an electrical spec, nobody 
really tells you their foo. The only thing you can do is pay one of the 
valley materials labs and they will figure it out. But CVD variants are 
common, as is the silane process you mentioned.

But after the wafer is diced, the side is now exposed. That is where 
more foo comes in. There is all sorts of foo in the scribe to keep (so 
they say) contaminants out. The scribe rules are proprietary in theory 
to the factory, but they can't be kept very secret since layout needs to 
know them, and of course the mask shop will know how you do your scribe. 
These rules are as secure as a NDA.

On Fri, 18 Oct 2013 14:50:38 -0700, miso <miso@sushi.com> wrote:

>On 10/16/2013 10:06 PM, John Larkin wrote:
>>>>
>>> I wouldn't connect the capacitance meter until the circuit was powered up.
>>
>> Or just scrunch your eyes closed really, really hard, to minimize what you
>> learn.
>>
>>
>I don't give a shit about parts that are not powered up. 


So you have no interest in diodes, resistors, capacitors, or
inductors. And no interest in the C-V behavior of ESD diodes.

Fine by me.


-- 

John Larkin         Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro   acquisition and simulation

On 10/18/2013 6:03 PM, miso wrote:
> On 10/17/2013 7:02 PM, Greegor wrote:
>> SP > AFAIUI chips are normally passivated
>> SP > (there's effectively a layer of glass-
>> SP > actually SiOx/SiNx- on top of the
>> SP > chip with "holes" for the bonding pads.
>> SP > Conformal coating at the chip level.
>> SP > So, moisture is unlikely to be an
>> SP > issue in a low impedance circuit.
>>
>> Did somebody skip that process on a batch?
>>
>> Was Mr. Larkin's high temp bake hot enough
>> to have that annealing effect you described?
>>
>
> Passivation is CVD with a bit of thermal oxide. [This is foo only fab
> knows exactly.] It really isn't a bake.

Usually TEOS (tetraethyl orthosilicate) spin-on glass, I think, but 
maybe sometimes LTO oxide.  It has to be low temperature because it's 
going on top of the back end, so anything above about 300 C is verboten. 
  (At least in the IBM processes I used to know about.)

Cheers

Phil Hobbs

>
> I can't speak for bipolar wafers, but ion contamination is usually the
> killer in MOS. When tweezers were actually tweezers (as in a mechanical
> device that gripped the wafer from the side), one dirty tweezer could
> whack a lot of wafers. You get a little sodium on the tweezer and it
> shoots right into the lattice. Tweezers have been vacuum devices that
> grip the back for some time. But it is possible VTC was a sloppy fab.
>
> Needless to say those photos of some CEO holding a wafer with their
> hands means that wafer was a junker in the first place.
>
>
>


-- 
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058

hobbs at electrooptical dot net
http://electrooptical.net