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differential Manchester decoder and FIFO

Started by p September 22, 2013
I need to make a bi-phase / differential Manchester decoder (max. 
frequency of recovered clock about 10MHz) and asynchronous FIFO 1 bit * 
~100...~1000.
How can I do this and what is best suitable to do it ?

Thanks in advance.
On Sun, 22 Sep 2013 22:53:43 +0200, p <1@2.3> wrote:

>I need to make a bi-phase / differential Manchester decoder (max. >frequency of recovered clock about 10MHz) and asynchronous FIFO 1 bit * >~100...~1000. >How can I do this and what is best suitable to do it ? > >Thanks in advance.
Simple async Manchester decoder: Make a transition detector (delay and XOR) and use it to fire a non-retriggerable one-shot on every data transition. Make the one-shot duration 3/4 of the bit time. It will soon settle down to firing on just the center-cell transition. Use the one-shot output to clock the data. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
> Simple async Manchester decoder: > > Make a transition detector (delay and XOR) and use it to fire a > non-retriggerable one-shot on every data transition. Make the one-shot duration > 3/4 of the bit time. It will soon settle down to firing on just the center-cell > transition. Use the one-shot output to clock the data.
Thank you, but recovered frequncy is any in range ~1..~10MHz. Circuit must be able to decode without any changes with this condition.
On Mon, 23 Sep 2013 02:15:10 +0200, p <1@2.3> wrote:

>> Simple async Manchester decoder: >> >> Make a transition detector (delay and XOR) and use it to fire a >> non-retriggerable one-shot on every data transition. Make the one-shot duration >> 3/4 of the bit time. It will soon settle down to firing on just the center-cell >> transition. Use the one-shot output to clock the data. > >Thank you, but recovered frequncy is any in range ~1..~10MHz. Circuit >must be able to decode without any changes with this condition.
Sounds like FPGA turf, then. Grunt work. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
On Mon, 23 Sep 2013 02:15:10 +0200, p <1@2.3> wrote:

>> Simple async Manchester decoder: >> >> Make a transition detector (delay and XOR) and use it to fire a >> non-retriggerable one-shot on every data transition. Make the one-shot duration >> 3/4 of the bit time. It will soon settle down to firing on just the center-cell >> transition. Use the one-shot output to clock the data. > >Thank you, but recovered frequncy is any in range ~1..~10MHz. Circuit >must be able to decode without any changes with this condition.
FPGA Look at the HD-6409, I've used this in another life. <http://www.intersil.com/content/dam/Intersil/documents/tb46/tb463.pdf> You'll have to do a auto baud measurement on the sync data, the 6409 has a pre-amble to sync the data clock. There is no whay to sync with out missing the first bits. Cheers
On 9/22/2013 8:15 PM, p wrote:
>> Simple async Manchester decoder: >> >> Make a transition detector (delay and XOR) and use it to fire a >> non-retriggerable one-shot on every data transition. Make the one-shot >> duration >> 3/4 of the bit time. It will soon settle down to firing on just the >> center-cell >> transition. Use the one-shot output to clock the data. > > Thank you, but recovered frequncy is any in range ~1..~10MHz. Circuit > must be able to decode without any changes with this condition.
That could be tough. I did a design similar to this in an FPGA. It received a simple bit stream and had to sync to the transitions. But it had a timing setting to establish the base frequency approximately. This design used a locked loop to adjust the NCO to the bit rate. Since the base frequency was set by the user the search mode is not overly aggressive. In your case you might need to use a rather aggressive search mode to set the base frequency very quickly, or even do a frequency measurement for a direct setting. Do you have a spec on the data stream format you will need to sync to? As others have indicated, there should be a preamble which would be a stream of bits which produce a single transition in the Manchester encoded stream. Knowing the length of this preamble will give you an idea of how quickly your circuit will need to adapt to the data frequency and lock up to the data stream. -- Rick
On Mon, 23 Sep 2013 01:36:31 -0400, rickman <gnuarm@gmail.com> wrote:

>On 9/22/2013 8:15 PM, p wrote: >>> Simple async Manchester decoder: >>> >>> Make a transition detector (delay and XOR) and use it to fire a >>> non-retriggerable one-shot on every data transition. Make the one-shot >>> duration >>> 3/4 of the bit time. It will soon settle down to firing on just the >>> center-cell >>> transition. Use the one-shot output to clock the data. >> >> Thank you, but recovered frequncy is any in range ~1..~10MHz. Circuit >> must be able to decode without any changes with this condition. > >That could be tough. I did a design similar to this in an FPGA. It >received a simple bit stream and had to sync to the transitions. But it >had a timing setting to establish the base frequency approximately. > >This design used a locked loop to adjust the NCO to the bit rate. Since >the base frequency was set by the user the search mode is not overly >aggressive. In your case you might need to use a rather aggressive >search mode to set the base frequency very quickly, or even do a >frequency measurement for a direct setting. > >Do you have a spec on the data stream format you will need to sync to? >As others have indicated, there should be a preamble which would be a >stream of bits which produce a single transition in the Manchester >encoded stream. Knowing the length of this preamble will give you an >idea of how quickly your circuit will need to adapt to the data >frequency and lock up to the data stream.
An FPGA could just count the widths of the high and low signals, with maybe a 100 MHz clock, and then do the math. Hey, determine the probable bit period, not hard to do, and then fake my 3/4 period one-shot decoder. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
Thanks for respone.

> FPGA
I've never done anything with FPGA (and CPLD). I was thinking about Lattice. I don't know whether this is a good choice. I don't know what to choose (design software and device).
> Look at the HD-6409, I've used this in another life. > <http://www.intersil.com/content/dam/Intersil/documents/tb46/tb463.pdf> > You'll have to do a auto baud measurement on the sync data, the 6409 > has a pre-amble to sync the data clock.
Very interesting, but max. data rate = 1Mbit/s.
> There is no whay to sync with out missing the first bits.
Missing the first bits (even ~1000) is no problem.
On Mon, 23 Sep 2013 18:58:25 +0200, p <1@2.3> wrote:

>Thanks for respone. > >> FPGA > >I've never done anything with FPGA (and CPLD). I was thinking about Lattice. >I don't know whether this is a good choice. I don't know what to choose >(design software and device). > >> Look at the HD-6409, I've used this in another life. >> <http://www.intersil.com/content/dam/Intersil/documents/tb46/tb463.pdf> >> You'll have to do a auto baud measurement on the sync data, the 6409 >> has a pre-amble to sync the data clock. > >Very interesting, but max. data rate = 1Mbit/s. > >> There is no whay to sync with out missing the first bits. > >Missing the first bits (even ~1000) is no problem.
There is another M en/decoder that runs at 10mhz. HD-15???? Cheers
On Sun, 22 Sep 2013 22:53:43 +0200, p <1@2.3> wrote:

>I need to make a bi-phase / differential Manchester decoder (max. >frequency of recovered clock about 10MHz) and asynchronous FIFO 1 bit * >~100...~1000. >How can I do this and what is best suitable to do it ? > >Thanks in advance.
I puzzled over you might automate determining the data rate. Turns out if you do an integrate and dump on the Manchester signal... http://www.analog-innovations.com/SED/DifferentialManchesterEncoder.pdf you get an average value proportional to data rate. Since you have a very wide frequency range I'd suggest AGC'ing the integrate current to keep the integration from clipping, then use a replica of that same current to time the 0.75*TB one-shots to restore the clocks. All Analog ;-) No FPGA's. ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.