Pinging 74HC4046 Users

On Oct 19, 4:00=A0am, Phil Hobbs
<pcdhSpamMeSensel...@electrooptical.net> wrote:
> On 10/17/2012 10:19 PM, Bill Sloman wrote:
> > On Oct 18, 2:56 am, Phil Hobbs
> > <pcdhSpamMeSensel...@electrooptical.net> =A0wrote:
> >> On 10/16/2012 11:33 PM, Bill Sloman wrote:
> >>> On Oct 17, 1:12 pm, John Larkin
> >>> <jjlar...@highNOTlandTHIStechnologyPART.com> =A0 wrote:
> >>>> On Tue, 16 Oct 2012 10:54:01 -0500, Tim Wescot
> >>>> <t...@seemywebsite.please> =A0 wrote:
> >>>>> On Tue, 16 Oct 2012 11:45:09 -0400, Phil Hobbs wrote:
> >>>>>> On 10/15/2012 09:40 PM, Jim Thompson wrote:
> >>>>>>> On Mon, 15 Oct 2012 21:22:04 -0400, Phil Hobbs
> >>>>>>> <pcdhSpamMeSensel...@electrooptical.net> =A0 =A0 wrote:
> >>>>>>>> On 10/15/2012 9:16 PM, Nico Coesel wrote:
> >>>>>>>>> Jim Thompson<To-Email-Use-The-Envelope-I...@On-My-Web-Site.com>
> >>>>>>>>> wrote:
>
> > <snip>
>
> >>>>>>> It occurs to me that the variable current input quits at about 1*=
VTH.
> >>>>>>> So you were trying to get to zero frequency ?:-)
>
> >>>>>>> Add some offset current and it won't quit oscillating.
>
> >>>>>> The metal gate version works over about 1000:1 range, and is very
> >>>>>> respectably linear--a few percent IIRC, which is much better than =
good
> >>>>>> enough for inside a PLL. =A0It's really quite pretty in a small wa=
y.
>
> >>>>>> The HC parts' nonlinearity is all over the map depending on the ve=
ndor,
> >>>>>> and that messes up the loop dynamics really badly. =A0Spicing the =
HC4046
> >>>>>> oscillator will definitely be "a trap for young players", as Dave =
Jones
> >>>>>> says.
>
> >>>>>> With the loop gain varying 3:1 with control voltage, and the centr=
e
> >>>>>> frequency being a very poorly controlled function of the RC, =A0yo=
u have
> >>>>>> to make HC4046 loops ridiculously overdamped in the normal case to=
 avoid
> >>>>>> loop instability. =A0If you're using lead-lag compensation, you ha=
ve to
> >>>>>> put the zero a factor of at least 5 below the nominal unity gain c=
ross,
> >>>>>> whereas with a well-behaved VCO, you can put it right at the unity=
 gain
> >>>>>> cross and have 45 degrees' phase margin.
>
> >>>>>> I'd far rather use an OTA integrator/Schmitt trigger oscillator or
> >>>>>> something like that, with the 4046 PDII.
>
> >>>>>> The HC4046 has its uses, but not nearly as many as if it were real=
ly a
> >>>>>> faster CD4046.
>
> >>>>> Oh, I should know -- OTA Integrator?
>
> >>>>> I wish someone would take the 3-state phase detector from the 4046 =
and
> >>>>> put it into a 6-pin SOT and call it TinyLogic or whatever. =A0It wo=
uld save
> >>>>> ever so much board space.
>
> >>>> We build something like the charge-pump detector into FPGAs. We use =
an
> >>>> external dual schottky diode for the pump-up and pump-down blips, to
> >>>> avoid the deadband that tri-state charge pumps tend to create. We ca=
n
> >>>> also delta-sigma those outputs to control our VXCO open-loop.
>
> >>>> The little function generator chips make nice wide-range, low
> >>>> frequency VCOs. Exar, Maxim?
>
> >>> And there used to be a fairly wide range of chips available that were
> >>> designed to be very linear VCOs, intended for use as voltage-to-
> >>> frequency A/D converters. Analog Devices still seems to be in the
> >>> business
>
> >>>http://www.analog.com/en/analog-to-digital-converters/voltage-to-freq.=
..
>
> >>> Phil Hobbs probably should be using the AD650 - though I can't
> >>> recommend it on the basis of personal expereience
>
> >> Fifteen bucks for a 1-MHz V-F converter? =A0Not me, especially not ins=
ide
> >> a PLL where 1% linearity is way better than good enough.
>
> > The point was that these are legacy parts, and correspondingly
> > expensive. The LM331 which offers even better linearity, but only goes
> > to 100kHz, turns out to be still available to, but at $6 each in small
> > quantities. I was rather hoping to provoke a response from somebody
> > who is still using that kind of part.
>
> >> I'd happily use a metal-gate 4046 at frequencies where they work--all
> >> you need is a resistor to ground from the PD2 output to pull it off th=
e
> >> dead zone.
>
> >> Above a megahertz or so, a current-programmed triangle wave oscillator
> >> is good,
>
> > Sure. A 1GHz gbw op amp could take you quite a way above 1MHz.
>
> >> or else a linearized LC VCO. =A0You can get linearities of better
> >> than 10% in varactor-tuned VCOs by putting in a couple of off-stage
> >> resonances.
>
> > Messy. I'd be thinking of a digitally controlled Direct Digital
> > Synthesis chip, which would be a lot tidier and would probably have a
> > lower jitter (if you low-pass filtered the synthesised sine wave
> > properly). For a seriously low jitter option, a DDS-like system
> > including an MC100E195 might be interesting - if complicated. Coping
> > with the temperature dependence of the delay through the MC100E195
> > might require Peltier junction or a self-calibrating scheme if you
> > really wanted to exploit the full capacity of the MC100E195.
>
> Digital PLLs don't have the performance of analogue ones,

Probably not generally true.

> and are far, far more complicated

Probably true, but our business is burying the complication so nobody
else has to worry about it.

> and power hungry.

I'm not sure about that as a general statement. I've alway been take
with the low power consumption of the Philips/NXP now Xilinx
CoolRunner CMOS parts - when you didn't tray and run them too fast -
which is why I've got a stick of 15 of them in my cupboard here,
waiting for a project to exploit them

>=A0My usual use for PLLs is
> demodulation rather than frequency synthesis, so DDSes are pretty much
> beside the point.

Why?

> You can get inductors in 2% tolerances, and the varactors of course are
> variable (and also good to +-5% to 8%), so you don't need tweaks to get
> a very respectable linearity improvement. =A0That means that you can be
> more aggressive on the loop compensation, and the improved performance
> is worth a lot.

But there's a great deal of manual labour tweaking each example to get
it's particular linearity respectable. Physicists have graduate
students to do that sort of labour. Engineers designing for production
can't afford them.

--
Bill Sloman, Sydney

On Oct 19, 12:22=A0am, George Herold <gher...@teachspin.com> wrote:
> On Oct 17, 3:08=A0pm, Phil Hobbs
>
>
>
> <pcdhSpamMeSensel...@electrooptical.net> wrote:
> > On 10/16/2012 09:11 AM, George Herold wrote:
>
> > > On Oct 15, 7:59 pm, Jim Thompson<To-Email-Use-The-Envelope-I...@On-My=
-
> > > Web-Site.com> =A0wrote:
> > >> Finally zeroing in on modeling the 74HC4046 after finding a
> > >> unpublished AppNote that gave more details on the innards. =A0This i=
s
> > >> what a fixed frequency looks like, simulation-wise...
>
> > >>http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf
>
> > >> Comments? =A0Scalings? =A0(This is based on AppNote and Datasheets
> > >> claiming trip at VDD/2).
>
> > >> First release will be VCO only and will be in LTspice format. =A0Onc=
e
> > >> you approve that, the PFD is virtually all logic.
>
> > >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0...Jim Thompson
> > >> --
> > >> | James E.Thompson, CTO =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0| =A0 =A0mens =A0 =A0 |
> > >> | Analog Innovations, Inc. =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 | =A0 =A0 et =A0 =A0 =A0|
> > >> | Analog/Mixed-Signal ASIC's and Discrete Systems =A0| =A0 =A0manus =
=A0 =A0|
> > >> | Phoenix, Arizona =A085048 =A0 =A0Skype: Contacts Only =A0| =A0 =A0=
 =A0 =A0 =A0 =A0 |
> > >> | Voice:(480)460-2350 =A0Fax: Available upon request | =A0Brass Rat =
=A0|
> > >> | E-mail Icon athttp://www.analog-innovations.com|=A0 =A01962 =A0 =
=A0 |
>
> > >> I love to cook with wine. =A0 =A0 Sometimes I even put it in the foo=
d.
>
> > > Hi Jim, Phil. =A0Here s a plot for a 74HC4046
>
> > >http://bayimg.com/kAEhEaAec
>
> > > And for different charging resistors.
>
> > >http://bayimg.com/kAehmaaEC
>
> > > The lines were just drawn by eye.
>
> > > As Phil says the oscillations stop if the control voltage falls below
> > > ~1Volt.
> > > (I never used the metal can version so don t know what I m missing.)
>
> > Those aren't too bad looking, but check out the NXP HC7046 datasheet, p=
.
> > 24 ofhttp://tinyurl.com/c3xgcgq, or =A0the TI one, P. 14 ofhttp://tinyu=
rl.com/cghq2yb.
>
> > Even the much-ballyhooed HC9046 has the same sorts of worries, see P.24
> > ofhttp://tinyurl.com/chlkgwv. Many of the typical curves are probably
> > acceptably linear for most PLL uses, but I for one do not get a warm
> > fuzzy feeling about the unit-to-unit repeatability, based on those curv=
es.
>
> > And check out the actual HC4046--first in a Chinese knockoff,http://tin=
yurl.com/buvdkbyP. 490,
> > then the TI version, P. 14 ofhttp://tinyurl.com/ckz4ezv,
> > and then in the ON semi versions, P. 11 ofhttp://tinyurl.com/cyymxsl.
>
> > Compare that with the HEF4046 (NXP metal gate version)--check out the
> > VCO linearity error plot on P. 15 ofhttp://tinyurl.com/cl3c7vv. =A0The
> > TI CD4046B claims 0.7% linearity from 2.5V to 7.5V with a 10V supply,ht=
tp://tinyurl.com/cpd3skg.
>
> > The HC versions are all over the map.
>
> > Cheers
>
> > Phil Hobbs
>
> > --
> > Dr Philip C D Hobbs
> > Principal Consultant
> > ElectroOptical Innovations LLC
> > Optics, Electro-optics, Photonics, Analog Electronics
>
> > 160 North State Road #203
> > Briarcliff Manor NY 10510
>
> > hobbs at electrooptical dot nethttp://electrooptical.net-Hide quoted te=
xt -
>
> > - Show quoted text -
>
> Thanks for all the links Phil, =A0I was just checking on which 'flavor'
> my data is from.
>
> So the data I took was for TI's 4046... and I now notice that someone
> in production purchased the more expensive NXP flavor.... grumble, I
> should go back and re-measure.
> (Why do people always have to 'piss a bit in the pot' and change
> things?)

Buyers get bribed by sales people. Junior engineers get snowed by
sales people - it's the latest design so it must be better - and so
forth. Sometimes the more modern parts are simply cheaper, and still
good enough - soemtimes better on every parameter except the one that
matters.

I used to field a lot of that kind of query from purchasing when I was
at Cambridge Instruments - I tried to answer them fast so that they
wouldn't have any excuse for leaving enegineering out of the loop.

--
Bill Sloman, Sydney

On Oct 19, 4:06=A0am, Phil Hobbs
<pcdhSpamMeSensel...@electrooptical.net> wrote:
> On 10/18/2012 07:06 AM, Allan Herriman wrote:
>
>
>
> > On Wed, 17 Oct 2012 15:57:57 -0700, Jim Thompson wrote:
>
> >> On Tue, 16 Oct 2012 16:19:44 -0400, Phil Hobbs
> >> <pcdhSpamMeSensel...@electrooptical.net> =A0wrote:
>
> >>> On 10/16/2012 02:30 PM, Jim Thompson wrote:
> >>>> On Tue, 16 Oct 2012 14:02:39 -0400, Phil Hobbs
> >>>> <pcdhSpamMeSensel...@electrooptical.net> =A0 wrote:
>
> >>>>> On 10/16/2012 11:56 AM, Jim Thompson wrote:
> >>>>>> On Tue, 16 Oct 2012 11:25:52 -0400, Phil Hobbs
> >>>>>> <pcdhSpamMeSensel...@electrooptical.net> =A0 =A0wrote:
>
> >>>>>>> On 10/15/2012 07:59 PM, Jim Thompson wrote:
> >>>>>>>> Finally zeroing in on modeling the 74HC4046 after finding a
> >>>>>>>> unpublished AppNote that gave more details on the innards. =A0Th=
is
> >>>>>>>> is what a fixed frequency looks like, simulation-wise...
>
> >>>>>>>>http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf
>
> >>>>>>>> Comments? =A0Scalings? =A0(This is based on AppNote and Datashee=
ts
> >>>>>>>> claiming trip at VDD/2).
>
> >>>>>>>> First release will be VCO only and will be in LTspice format.
> >>>>>>>> Once you approve that, the PFD is virtually all logic.
>
> >>>>>>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 ...Jim Thompson
>
> >>>>>>> Different manufacturers give you a wide variety of ridiculously
> >>>>>>> nonlinear tuning curves for the VCO--the tuning sensitivity varie=
s
> >>>>>>> like 3:1,
>
> >>>>>> I don't think most users fret over the incremental slope. =A0The
> >>>>>> "follower" variation is trivial to fix by adding an OpAmp. =A0Sink=
ing
> >>>>>> one end of the capacitor into the substrate diode every half cycle
> >>>>>> is something you have to live with if you like 4046's. =A0I'm doin=
g
> >>>>>> this for fun (and requests from this group)... I wouldn't use one
> >>>>>> myself. Get my MC4024 if you want better linearity. =A0I think the=
re's
> >>>>>> also a PECL copy, but I don't remember the part number off the top
> >>>>>> of my head. =A0Or use a V-to-F chip.
>
> >>>>>>> and the oscillator quits below about 0.7-1.1V (@VDD=3D5) dependin=
g on
> >>>>>>> the device.
>
> >>>>>> That's noted on the data sheet. =A0Why does that give you such
> >>>>>> heartburn? =A0Do you really need zero frequency?
>
> >>>>>>> Which did you pick? ;)
>
> >>>>>> I have the most complete data on the TI 'HC4046, but I was aiming
> >>>>>> sort of average ;-) since I'm building it from behavioral blocks.
>
> >>>>>> I would guess that you're one of the few people in the world that
> >>>>>> would need a flat-ass accurate fit to one particular version.
>
> >>>>>>> (The metal gate 4046-style oscillators all stink on ice--HC4046,
> >>>>>>> HC7046,
> >>>>>>> HC9046, all makers, all horrible. =A0PD2 is nice if you stay out =
of
> >>>>>>> the dead zone.)
>
> >>>>>>> Cheers
>
> >>>>>>> Phil Hobbs
>
> >>>>>> What do you really need? =A0An accurate V-to-F?
>
> >>>>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0...Jim Thompson
>
> >>>>> The loop gain is proportional to K_VCO * K_phi, so if the tuning
> >>>>> sensitivity varies all over the map like that, so does the frequenc=
y
> >>>>> compensation of the loop. =A0That's what makes the HC4046 and its
> >>>>> brethren so sucky.
>
> >>>>> Cheers
>
> >>>>> Phil Hobbs
>
> >>>> I've not even played with one, except to measure some DC. =A0The dat=
a
> >>>> sheets would seem to indicate that the non-linearity occurs at the
> >>>> tuning extremes. =A0Just bound your control voltage if you're gettin=
g
> >>>> lock-in issues<:-|
>
> >>> Just what I need, another opportunity for a little turd-polishing. ;)
>
> >>> The HC4046 isn't impossible to use, it's just sucky for no good reaso=
n.
> >>> =A0 Since the frequency vs RC spec is so loose, keeping away from the
> >>> edges is hard even in a narrowband application. =A0You just have to u=
se
> >>> really tame loop compensation (which is fine for some things).
>
> >>>> I don't know why the "designers" of the 4046 didn't do a better job =
of
> >>>> copying the PECL core of my MC4024 (~1965). =A0All current mode, no
> >>>> diode clamping, etc.
>
> >>> Or even the metal gate CD4046.
>
> >>> Cheers
>
> >>> Phil Hobbs
>
> >> Try this...
>
> >>http://www.analog-innovations.com/SED/Oscillator_AnotherArchitecture.pd=
f
>
> >> Note the frequency, ~46MHz, and the current consumption ;-)
>
> >> It is immaculately linear in frequency versus control current.
>
> >> Now I'm yanking your chain just a wee bit, this is on a 0.18um process=
,
> >> but I'll try it on a 5V process and see how it behaves.
>
> >> But would anyone buy it?
>
> > I would have bought it up to about seven years ago. =A0That was the las=
t
> > time I used a '46 (actually a '9046 with its better phase detector).
> > I left the oscillator disabled.
>
> > These days, for the sorts of things I design, I'm more likely to replac=
e
> > the entire application with something like this:
> >http://www.silabs.com/products/clocksoscillators/clocks/Pages/Any-Rat...
>
> > Regards,
> > Allan
>
> Wow, $35? =A0I can buy a lot of good analogue stuff for that!

Then spend $35 worth of labour tweeking it to get the linearity right.

--
Bill Sloman, Sydney

Jim Thompson wrote:
>
> Taking note that I'm not a logic designer, I'm not sure your version
> covers all states.

It passed your sim with slightly different frequencies at each input to 
create a walking phase shift.

You did need to match the gates.  If they were simmed as discrete 7400's 
then you had to take the 4 on the left from one package.


>  It took Ron Treadway NINE gates back in the
> mid-60's in the MC4044...
>
>    http://www.analog-innovations.com/SED/MC4044_MC4344.pdf

I know.  That's why I was surprised it worked with 8 as quoted:

==========quote==========
Newsgroups: 
alt.binaries.schematics.electronic,sci.electronics.cad,sci.electronics.design,sci.electronics.misc
Sent: Monday, August 27, 2001 10:26 PM
Subject: Re: Help an Analog Guy with a Digital Problem

|> The internal feedback disabled the pulse too soon. The resulting
|> pulse width at the final latch was about 1/2 of what it is with
|> feedback from the output (~2.5nS vs 5nS).
|
|Ok. So was your testing of the last circuit sucessful under full load?
|

You bet...you're now in a product...E-Mail for details.
=========================


-- 

Reply in group, but if emailing add one more
zero, and remove the last word. 

Bill Sloman wrote:

> On Oct 19, 4:00 am, Phil Hobbs
> <pcdhSpamMeSensel...@electrooptical.net> wrote:
>

<snip>

>
> > My usual use for PLLs is
> > demodulation rather than frequency synthesis, so DDSes are pretty much
> > beside the point.
>
> Why?

Because driving them in a demodulator loop is a completely needless hassle, and won't
do as good a job when you're done.  Analogue loops rock.  Doing it digitally makes as
much sense as emulating an op amp using an ADC, a DAC, and an FPGA, i.e. none.

>
>
> > You can get inductors in 2% tolerances, and the varactors of course are
> > variable (and also good to +-5% to 8%), so you don't need tweaks to get
> > a very respectable linearity improvement.  That means that you can be
> > more aggressive on the loop compensation, and the improved performance
> > is worth a lot.
>
> But there's a great deal of manual labour tweaking each example to get
> it's particular linearity respectable. Physicists have graduate
> students to do that sort of labour. Engineers designing for production
> can't afford them.

Not true--read what I wrote above.  Inexpensive close-tolerance inductors do just
fine.

How are you liking being back in OZ?  Run into Phil A. yet?

Cheers

Phil Hobbs

On Fri, 19 Oct 2012 08:09:38 -0400, "Tom Del Rosso"
<td_03@verizon.net.invalid> wrote:

>Jim Thompson wrote:
>>
>> Taking note that I'm not a logic designer, I'm not sure your version
>> covers all states.
>
>It passed your sim with slightly different frequencies at each input to 
>create a walking phase shift.
>
>You did need to match the gates.  If they were simmed as discrete 7400's 
>then you had to take the 4 on the left from one package.
>
>
>>  It took Ron Treadway NINE gates back in the
>> mid-60's in the MC4044...
>>
>>    http://www.analog-innovations.com/SED/MC4044_MC4344.pdf
>
>I know.  That's why I was surprised it worked with 8 as quoted:
>
>==========quote==========
>Newsgroups: 
>alt.binaries.schematics.electronic,sci.electronics.cad,sci.electronics.design,sci.electronics.misc
>Sent: Monday, August 27, 2001 10:26 PM
>Subject: Re: Help an Analog Guy with a Digital Problem
>
>|> The internal feedback disabled the pulse too soon. The resulting
>|> pulse width at the final latch was about 1/2 of what it is with
>|> feedback from the output (~2.5nS vs 5nS).
>|
>|Ok. So was your testing of the last circuit sucessful under full load?
>|
>
>You bet...you're now in a product...E-Mail for details.
>=========================

Thanks, Tom!  I'll have to try that.  Does it have deadband?
		
                                        ...Jim Thompson
-- 
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

On a sunny day (Fri, 19 Oct 2012 08:59:28 -0400) it happened Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote in
<50814EB0.FE38E8B7@electrooptical.net>:

>
>
>Bill Sloman wrote:
>
>> On Oct 19, 4:00 am, Phil Hobbs
>> <pcdhSpamMeSensel...@electrooptical.net> wrote:
>>
>
><snip>
>
>>
>> > My usual use for PLLs is
>> > demodulation rather than frequency synthesis, so DDSes are pretty much
>> > beside the point.
>>
>> Why?
>
>Because driving them in a demodulator loop is a completely needless hassle, and won't
>do as good a job when you're done.  Analogue loops rock.  Doing it digitally makes as
>much sense as emulating an op amp using an ADC, a DAC, and an FPGA, i.e. none.

mm
:-)
See my posting in s.e.d today with subject:
 GPS frequency counter + PLL PIC based

On Oct 19, 11:59=A0pm, Phil Hobbs
<pcdhSpamMeSensel...@electrooptical.net> wrote:
> BillSlomanwrote:
> > On Oct 19, 4:00 am, Phil Hobbs
> > <pcdhSpamMeSensel...@electrooptical.net> wrote:
>
> <snip>
>
> > > My usual use for PLLs is
> > > demodulation rather than frequency synthesis, so DDSes are pretty muc=
h
> > > beside the point.
>
> > Why?
>
> Because driving them in a demodulator loop is a completely needless hassl=
e, and won't
> do as good a job when you're done.

Why do you think that? The DDS syntheisised sine wave is likely to
have a lower jitter than you'd get from most VCOs, and you've got a
whole lot better idea of the frequency you are synthesising.

>Analogue loops rock. =A0Doing it digitally makes as
> much sense as emulating an op amp using an ADC, a DAC, and an FPGA, i.e. =
none.

There are occasion when an ADC plus digital signal processing plus a
DAC do make sense - as soon as you want a non-linear or - worse - a
non-monotonic relationship between input and output. For phase-locked
loops this happens quite often - as Floyd M Gardener pointed out, the
sort of phase-sensitive detector that gives you the best lock doesn't
necessarily get you into lock as fast as you'd like.

The DDS approach comes into its own when you want several sine wave
sources at once - for detecting at twice the frequency or both in-
phase and in quadrature. The analogue techniques for doing this are no
less messy and generally  give you a poorer quality sine wave.

> > > You can get inductors in 2% tolerances, and the varactors of course a=
re
> > > variable (and also good to +-5% to 8%), so you don't need tweaks to g=
et
> > > a very respectable linearity improvement. =A0That means that you can =
be
> > > more aggressive on the loop compensation, and the improved performanc=
e
> > > is worth a lot.
>
> > But there's a great deal of manual labour tweaking each example to get
> > it's particular linearity respectable. Physicists have graduate
> > students to do that sort of labour. Engineers designing for production
> > can't afford them.
>
> Not true--read what I wrote above. =A0Inexpensive close-tolerance inducto=
rs do just
> fine.

Inexpensive close tolerance varactors don't seem to be as readily
available. And the tuning range available is rarely impressive.

Varactors have a roughly hyperbolic capacitance to voltage
relationship, so getting the tuning loop critically damped isn't going
to be all that easy.

> How are you liking being back in OZ? =A0Run into Phil A. yet?

Phil Allison does live in Sydney, but I don't expect to run into him -
I did suggest (here) that we get together over a coffee a few years
ago but he didn't like the idea.

Oz has been fine so far, but we're not yet entirely out of jet-lag.
We've been keeping a low profile. I did apply for two jobs yesterday,
but that was more to get my name on the books than in any expectation
that I'd get anything. My wife wants to buy a car today, which is
going to take a while.

--
Bill Sloman, Nijmegen

On Fri, 19 Oct 2012 15:02:51 -0700 (PDT), Bill Sloman
<bill.sloman@ieee.org> wrote:

>On Oct 19, 11:59&#4294967295;pm, Phil Hobbs
><pcdhSpamMeSensel...@electrooptical.net> wrote:
>> BillSlomanwrote:
>> > On Oct 19, 4:00 am, Phil Hobbs
>> > <pcdhSpamMeSensel...@electrooptical.net> wrote:
>>
>> <snip>
>>
>> > > My usual use for PLLs is
>> > > demodulation rather than frequency synthesis, so DDSes are pretty much
>> > > beside the point.
>>
>> > Why?
>>
>> Because driving them in a demodulator loop is a completely needless hassle, and won't
>> do as good a job when you're done.
>
>Why do you think that? The DDS syntheisised sine wave is likely to
>have a lower jitter than you'd get from most VCOs, and you've got a
>whole lot better idea of the frequency you are synthesising.

DDSs suck for jitter. Unfiltered, looking at the phase accumulator
MSB, they have a full clock of p-p jitter. DAC'd and filtered, into a
comparator, it's more complex, but much below the LPF cutoff, you're
basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.

The real nuisance in a DDS is the damned lowpass filter. 

VCOs can be a lot better, and VCXOs hugely better.



-- 

John Larkin         Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro   acquisition and simulation

John Larkin wrote:
> On Fri, 19 Oct 2012 15:02:51 -0700 (PDT), Bill Sloman
> <bill.sloman@ieee.org> wrote:
> 
> 
>>On Oct 19, 11:59 pm, Phil Hobbs
>><pcdhSpamMeSensel...@electrooptical.net> wrote:
>>
>>>BillSlomanwrote:
>>>
>>>>On Oct 19, 4:00 am, Phil Hobbs
>>>><pcdhSpamMeSensel...@electrooptical.net> wrote:
>>>
>>><snip>
>>>
>>>>>My usual use for PLLs is
>>>>>demodulation rather than frequency synthesis, so DDSes are pretty much
>>>>>beside the point.
>>>
>>>>Why?
>>>
>>>Because driving them in a demodulator loop is a completely needless hassle, and won't
>>>do as good a job when you're done.
>>
>>Why do you think that? The DDS syntheisised sine wave is likely to
>>have a lower jitter than you'd get from most VCOs, and you've got a
>>whole lot better idea of the frequency you are synthesising.
> 
> 
> DDSs suck for jitter. Unfiltered, looking at the phase accumulator
> MSB, they have a full clock of p-p jitter. DAC'd and filtered, into a
> comparator, it's more complex, but much below the LPF cutoff, you're
> basically quantized to the DAC resolution. Jitter like 1 part in
> 20,000 is common for a 16-bit system.
> 
> The real nuisance in a DDS is the damned lowpass filter. 
> 
> VCOs can be a lot better, and VCXOs hugely better.
> 
> 
> 
  Slugman is like the yellow line on the road, he's always in the 
middle,  can't take either side but yet, his lines seem to break left or 
right at
every turning post.

  He just can't maintain solid facts or lines.

Jamie