On Oct 17, 3:08=A0pm, Phil Hobbs <pcdhSpamMeSensel...@electrooptical.net> wrote:> On 10/16/2012 09:11 AM, George Herold wrote: > > > > > > > On Oct 15, 7:59 pm, Jim Thompson<To-Email-Use-The-Envelope-I...@On-My- > > Web-Site.com> =A0wrote: > >> Finally zeroing in on modeling the 74HC4046 after finding a > >> unpublished AppNote that gave more details on the innards. =A0This is > >> what a fixed frequency looks like, simulation-wise... > > >>http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf > > >> Comments? =A0Scalings? =A0(This is based on AppNote and Datasheets > >> claiming trip at VDD/2). > > >> First release will be VCO only and will be in LTspice format. =A0Once > >> you approve that, the PFD is virtually all logic. > > >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ==A0 =A0 =A0 =A0...Jim Thompson> >> -- > >> | James E.Thompson, CTO =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ==A0 =A0 =A0| =A0 =A0mens =A0 =A0 |> >> | Analog Innovations, Inc. =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0==A0 | =A0 =A0 et =A0 =A0 =A0|> >> | Analog/Mixed-Signal ASIC's and Discrete Systems =A0| =A0 =A0manus ==A0 =A0|> >> | Phoenix, Arizona =A085048 =A0 =A0Skype: Contacts Only =A0| =A0 =A0 ==A0 =A0 =A0 =A0 |> >> | Voice:(480)460-2350 =A0Fax: Available upon request | =A0Brass Rat ==A0|> >> | E-mail Icon athttp://www.analog-innovations.com|=A0 =A01962 =A0 =A0 =|> > >> I love to cook with wine. =A0 =A0 Sometimes I even put it in the food. > > > Hi Jim, Phil. =A0Here s a plot for a 74HC4046 > > >http://bayimg.com/kAEhEaAec > > > And for different charging resistors. > > >http://bayimg.com/kAehmaaEC > > > The lines were just drawn by eye. > > > As Phil says the oscillations stop if the control voltage falls below > > ~1Volt. > > (I never used the metal can version so don t know what I m missing.) > > Those aren't too bad looking, but check out the NXP HC7046 datasheet, p. > 24 ofhttp://tinyurl.com/c3xgcgq, or =A0the TI one, P. 14 ofhttp://tinyurl=.com/cghq2yb.> > Even the much-ballyhooed HC9046 has the same sorts of worries, see P.24 > ofhttp://tinyurl.com/chlkgwv. Many of the typical curves are probably > acceptably linear for most PLL uses, but I for one do not get a warm > fuzzy feeling about the unit-to-unit repeatability, based on those curves=.> > And check out the actual HC4046--first in a Chinese knockoff,http://tinyu=rl.com/buvdkbyP. 490,> then the TI version, P. 14 ofhttp://tinyurl.com/ckz4ezv, > and then in the ON semi versions, P. 11 ofhttp://tinyurl.com/cyymxsl. > > Compare that with the HEF4046 (NXP metal gate version)--check out the > VCO linearity error plot on P. 15 ofhttp://tinyurl.com/cl3c7vv. =A0The > TI CD4046B claims 0.7% linearity from 2.5V to 7.5V with a 10V supply,http=://tinyurl.com/cpd3skg.> > The HC versions are all over the map. > > Cheers > > Phil Hobbs > > -- > Dr Philip C D Hobbs > Principal Consultant > ElectroOptical Innovations LLC > Optics, Electro-optics, Photonics, Analog Electronics > > 160 North State Road #203 > Briarcliff Manor NY 10510 > > hobbs at electrooptical dot nethttp://electrooptical.net- Hide quoted tex=t -> > - Show quoted text -Thanks for all the links Phil, I was just checking on which 'flavor' my data is from. So the data I took was for TI's 4046... and I now notice that someone in production purchased the more expensive NXP flavor.... grumble, I should go back and re-measure. (Why do people always have to 'piss a bit in the pot' and change things?) George H.
Pinging 74HC4046 Users
Started by ●October 15, 2012
Reply by ●October 18, 20122012-10-18
Reply by ●October 18, 20122012-10-18
Phil Hobbs wrote:> On 10/15/2012 07:59 PM, Jim Thompson wrote: > > Finally zeroing in on modeling the 74HC4046 after finding a > > unpublished AppNote that gave more details on the innards. This is > > what a fixed frequency looks like, simulation-wise... > > > > http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf > > > > Comments? Scalings? (This is based on AppNote and Datasheets > > claiming trip at VDD/2). > > > > First release will be VCO only and will be in LTspice format. Once > > you approve that, the PFD is virtually all logic. > > > > ...Jim Thompson > > Different manufacturers give you a wide variety of ridiculously > nonlinear tuning curves for the VCO--the tuning sensitivity varies > like 3:1, and the oscillator quits below about 0.7-1.1V (@VDD=5) > depending on the device. > > Which did you pick? ;) > > (The metal gate 4046-style oscillators all stink on ice--HC4046, > HC7046, HC9046, all makers, all horrible. PD2 is nice if you stay > out of the dead zone.)I always wondered what the "phase pulses" were good for. If you don't need them, my 8-gate wonder* would do, and I don't think it has a dead zone. * SET -----+------------------------| | |NAND>--+ +-------| +--| | |NAND>--+-----+ | +--| | | | | | +----------|--+ | | | | +----------+ | | | | | +--| | | |NAND>-----+ | +-------| +--| Q | |NAND>--+------- +--------------------------------+--| | | | +----------|--+ | | +----------+ | | | _ +--------------------------------+--| | Q | |NAND>-----+---- +-------| +--| |NAND>--+ | +--| | | | | | +----------|--+ | | | | +----------+ | | | | | +--| | | |NAND>-----+--+ | +-------| +--| | | |NAND>--+ RESET -----+------------------------| -- Reply in group, but if emailing add one more zero, and remove the last word.
Reply by ●October 18, 20122012-10-18
On Thu, 18 Oct 2012 11:21:12 -0400, "Tom Del Rosso" <td_03@verizon.net.invalid> wrote:>Phil Hobbs wrote: >> On 10/15/2012 07:59 PM, Jim Thompson wrote: >> > Finally zeroing in on modeling the 74HC4046 after finding a >> > unpublished AppNote that gave more details on the innards. This is >> > what a fixed frequency looks like, simulation-wise... >> > >> > http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf >> > >> > Comments? Scalings? (This is based on AppNote and Datasheets >> > claiming trip at VDD/2). >> > >> > First release will be VCO only and will be in LTspice format. Once >> > you approve that, the PFD is virtually all logic. >> > >> > ...Jim Thompson >> >> Different manufacturers give you a wide variety of ridiculously >> nonlinear tuning curves for the VCO--the tuning sensitivity varies >> like 3:1, and the oscillator quits below about 0.7-1.1V (@VDD=5) >> depending on the device. >> >> Which did you pick? ;) >> >> (The metal gate 4046-style oscillators all stink on ice--HC4046, >> HC7046, HC9046, all makers, all horrible. PD2 is nice if you stay >> out of the dead zone.) > >I always wondered what the "phase pulses" were good for. If you don't need >them, my 8-gate wonder* would do, and I don't think it has a dead zone. > > >* > SET -----+------------------------| > | |NAND>--+ > +-------| +--| | > |NAND>--+-----+ | > +--| | | > | | | > +----------|--+ | > | | | > +----------+ | | > | | | > +--| | | > |NAND>-----+ | > +-------| +--| Q > | |NAND>--+------- > +--------------------------------+--| | > | | > +----------|--+ > | | > +----------+ | > | | _ > +--------------------------------+--| | Q > | |NAND>-----+---- > +-------| +--| > |NAND>--+ | > +--| | | > | | | > +----------|--+ | > | | | > +----------+ | | > | | | > +--| | | > |NAND>-----+--+ | > +-------| +--| | > | |NAND>--+ >RESET -----+------------------------|Taking note that I'm not a logic designer, I'm not sure your version covers all states. It took Ron Treadway NINE gates back in the mid-60's in the MC4044... http://www.analog-innovations.com/SED/MC4044_MC4344.pdf ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●October 18, 20122012-10-18
On 10/17/2012 10:19 PM, Bill Sloman wrote:> On Oct 18, 2:56 am, Phil Hobbs > <pcdhSpamMeSensel...@electrooptical.net> wrote: >> On 10/16/2012 11:33 PM, Bill Sloman wrote: >>> On Oct 17, 1:12 pm, John Larkin >>> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>>> On Tue, 16 Oct 2012 10:54:01 -0500, Tim Wescot >>>> <t...@seemywebsite.please> wrote: >>>>> On Tue, 16 Oct 2012 11:45:09 -0400, Phil Hobbs wrote: >>>>>> On 10/15/2012 09:40 PM, Jim Thompson wrote: >>>>>>> On Mon, 15 Oct 2012 21:22:04 -0400, Phil Hobbs >>>>>>> <pcdhSpamMeSensel...@electrooptical.net> wrote: >>>>>>>> On 10/15/2012 9:16 PM, Nico Coesel wrote: >>>>>>>>> Jim Thompson<To-Email-Use-The-Envelope-I...@On-My-Web-Site.com> >>>>>>>>> wrote: > > <snip> > >>>>>>> It occurs to me that the variable current input quits at about 1*VTH. >>>>>>> So you were trying to get to zero frequency ?:-) >> >>>>>>> Add some offset current and it won't quit oscillating. >> >>>>>> The metal gate version works over about 1000:1 range, and is very >>>>>> respectably linear--a few percent IIRC, which is much better than good >>>>>> enough for inside a PLL. It's really quite pretty in a small way. >> >>>>>> The HC parts' nonlinearity is all over the map depending on the vendor, >>>>>> and that messes up the loop dynamics really badly. Spicing the HC4046 >>>>>> oscillator will definitely be "a trap for young players", as Dave Jones >>>>>> says. >> >>>>>> With the loop gain varying 3:1 with control voltage, and the centre >>>>>> frequency being a very poorly controlled function of the RC, you have >>>>>> to make HC4046 loops ridiculously overdamped in the normal case to avoid >>>>>> loop instability. If you're using lead-lag compensation, you have to >>>>>> put the zero a factor of at least 5 below the nominal unity gain cross, >>>>>> whereas with a well-behaved VCO, you can put it right at the unity gain >>>>>> cross and have 45 degrees' phase margin. >> >>>>>> I'd far rather use an OTA integrator/Schmitt trigger oscillator or >>>>>> something like that, with the 4046 PDII. >> >>>>>> The HC4046 has its uses, but not nearly as many as if it were really a >>>>>> faster CD4046. >> >>>>> Oh, I should know -- OTA Integrator? >> >>>>> I wish someone would take the 3-state phase detector from the 4046 and >>>>> put it into a 6-pin SOT and call it TinyLogic or whatever. It would save >>>>> ever so much board space. >> >>>> We build something like the charge-pump detector into FPGAs. We use an >>>> external dual schottky diode for the pump-up and pump-down blips, to >>>> avoid the deadband that tri-state charge pumps tend to create. We can >>>> also delta-sigma those outputs to control our VXCO open-loop. >> >>>> The little function generator chips make nice wide-range, low >>>> frequency VCOs. Exar, Maxim? >> >>> And there used to be a fairly wide range of chips available that were >>> designed to be very linear VCOs, intended for use as voltage-to- >>> frequency A/D converters. Analog Devices still seems to be in the >>> business >> >>> http://www.analog.com/en/analog-to-digital-converters/voltage-to-freq... >> >>> Phil Hobbs probably should be using the AD650 - though I can't >>> recommend it on the basis of personal expereience >> >> Fifteen bucks for a 1-MHz V-F converter? Not me, especially not inside >> a PLL where 1% linearity is way better than good enough. > > The point was that these are legacy parts, and correspondingly > expensive. The LM331 which offers even better linearity, but only goes > to 100kHz, turns out to be still available to, but at $6 each in small > quantities. I was rather hoping to provoke a response from somebody > who is still using that kind of part. > >> I'd happily use a metal-gate 4046 at frequencies where they work--all >> you need is a resistor to ground from the PD2 output to pull it off the >> dead zone. >> >> Above a megahertz or so, a current-programmed triangle wave oscillator >> is good, > > Sure. A 1GHz gbw op amp could take you quite a way above 1MHz. > >> or else a linearized LC VCO. You can get linearities of better >> than 10% in varactor-tuned VCOs by putting in a couple of off-stage >> resonances. > > Messy. I'd be thinking of a digitally controlled Direct Digital > Synthesis chip, which would be a lot tidier and would probably have a > lower jitter (if you low-pass filtered the synthesised sine wave > properly). For a seriously low jitter option, a DDS-like system > including an MC100E195 might be interesting - if complicated. Coping > with the temperature dependence of the delay through the MC100E195 > might require Peltier junction or a self-calibrating scheme if you > really wanted to exploit the full capacity of the MC100E195. > > -- > Bill Sloman, Sydney >Digital PLLs don't have the performance of analogue ones, and are far, far more complicated and power hungry. My usual use for PLLs is demodulation rather than frequency synthesis, so DDSes are pretty much beside the point. You can get inductors in 2% tolerances, and the varactors of course are variable (and also good to +-5% to 8%), so you don't need tweaks to get a very respectable linearity improvement. That means that you can be more aggressive on the loop compensation, and the improved performance is worth a lot. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Reply by ●October 18, 20122012-10-18
On 10/18/2012 07:06 AM, Allan Herriman wrote:> On Wed, 17 Oct 2012 15:57:57 -0700, Jim Thompson wrote: > >> On Tue, 16 Oct 2012 16:19:44 -0400, Phil Hobbs >> <pcdhSpamMeSenseless@electrooptical.net> wrote: >> >>> On 10/16/2012 02:30 PM, Jim Thompson wrote: >>>> On Tue, 16 Oct 2012 14:02:39 -0400, Phil Hobbs >>>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>>> >>>>> On 10/16/2012 11:56 AM, Jim Thompson wrote: >>>>>> On Tue, 16 Oct 2012 11:25:52 -0400, Phil Hobbs >>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote: >>>>>> >>>>>>> On 10/15/2012 07:59 PM, Jim Thompson wrote: >>>>>>>> Finally zeroing in on modeling the 74HC4046 after finding a >>>>>>>> unpublished AppNote that gave more details on the innards. This >>>>>>>> is what a fixed frequency looks like, simulation-wise... >>>>>>>> >>>>>>>> http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf >>>>>>>> >>>>>>>> Comments? Scalings? (This is based on AppNote and Datasheets >>>>>>>> claiming trip at VDD/2). >>>>>>>> >>>>>>>> First release will be VCO only and will be in LTspice format. >>>>>>>> Once you approve that, the PFD is virtually all logic. >>>>>>>> >>>>>>>> ...Jim Thompson >>>>>>> >>>>>>> Different manufacturers give you a wide variety of ridiculously >>>>>>> nonlinear tuning curves for the VCO--the tuning sensitivity varies >>>>>>> like 3:1, >>>>>> >>>>>> I don't think most users fret over the incremental slope. The >>>>>> "follower" variation is trivial to fix by adding an OpAmp. Sinking >>>>>> one end of the capacitor into the substrate diode every half cycle >>>>>> is something you have to live with if you like 4046's. I'm doing >>>>>> this for fun (and requests from this group)... I wouldn't use one >>>>>> myself. Get my MC4024 if you want better linearity. I think there's >>>>>> also a PECL copy, but I don't remember the part number off the top >>>>>> of my head. Or use a V-to-F chip. >>>>>> >>>>>>> and the oscillator quits below about 0.7-1.1V (@VDD=5) depending on >>>>>>> the device. >>>>>> >>>>>> That's noted on the data sheet. Why does that give you such >>>>>> heartburn? Do you really need zero frequency? >>>>>> >>>>>> >>>>>>> Which did you pick? ;) >>>>>> >>>>>> I have the most complete data on the TI 'HC4046, but I was aiming >>>>>> sort of average ;-) since I'm building it from behavioral blocks. >>>>>> >>>>>> I would guess that you're one of the few people in the world that >>>>>> would need a flat-ass accurate fit to one particular version. >>>>>> >>>>>> >>>>>>> (The metal gate 4046-style oscillators all stink on ice--HC4046, >>>>>>> HC7046, >>>>>>> HC9046, all makers, all horrible. PD2 is nice if you stay out of >>>>>>> the dead zone.) >>>>>>> >>>>>>> Cheers >>>>>>> >>>>>>> Phil Hobbs >>>>>> >>>>>> What do you really need? An accurate V-to-F? >>>>>> >>>>>> ...Jim Thompson >>>>> >>>>> The loop gain is proportional to K_VCO * K_phi, so if the tuning >>>>> sensitivity varies all over the map like that, so does the frequency >>>>> compensation of the loop. That's what makes the HC4046 and its >>>>> brethren so sucky. >>>>> >>>>> Cheers >>>>> >>>>> Phil Hobbs >>>> >>>> I've not even played with one, except to measure some DC. The data >>>> sheets would seem to indicate that the non-linearity occurs at the >>>> tuning extremes. Just bound your control voltage if you're getting >>>> lock-in issues<:-| >>> >>> Just what I need, another opportunity for a little turd-polishing. ;) >>> >>> The HC4046 isn't impossible to use, it's just sucky for no good reason. >>> Since the frequency vs RC spec is so loose, keeping away from the >>> edges is hard even in a narrowband application. You just have to use >>> really tame loop compensation (which is fine for some things). >>> >>> >>>> I don't know why the "designers" of the 4046 didn't do a better job of >>>> copying the PECL core of my MC4024 (~1965). All current mode, no >>>> diode clamping, etc. >>> >>> Or even the metal gate CD4046. >>> >>> Cheers >>> >>> Phil Hobbs >> >> Try this... >> >> http://www.analog-innovations.com/SED/Oscillator_AnotherArchitecture.pdf >> >> Note the frequency, ~46MHz, and the current consumption ;-) >> >> It is immaculately linear in frequency versus control current. >> >> Now I'm yanking your chain just a wee bit, this is on a 0.18um process, >> but I'll try it on a 5V process and see how it behaves. >> >> But would anyone buy it? > > I would have bought it up to about seven years ago. That was the last > time I used a '46 (actually a '9046 with its better phase detector). > I left the oscillator disabled. > > These days, for the sorts of things I design, I'm more likely to replace > the entire application with something like this: > http://www.silabs.com/products/clocksoscillators/clocks/Pages/Any-RateJitterAttenuatingClockMultipliers.aspx > > Regards, > AllanWow, $35? I can buy a lot of good analogue stuff for that! Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Reply by ●October 18, 20122012-10-18
On 10/18/2012 11:21 AM, Tom Del Rosso wrote:> Phil Hobbs wrote: >> On 10/15/2012 07:59 PM, Jim Thompson wrote: >>> Finally zeroing in on modeling the 74HC4046 after finding a >>> unpublished AppNote that gave more details on the innards. This is >>> what a fixed frequency looks like, simulation-wise... >>> >>> http://www.analog-innovations.com/SED/HC4046_VCO_2_SIM.pdf >>> >>> Comments? Scalings? (This is based on AppNote and Datasheets >>> claiming trip at VDD/2). >>> >>> First release will be VCO only and will be in LTspice format. Once >>> you approve that, the PFD is virtually all logic. >>> >>> ...Jim Thompson >> >> Different manufacturers give you a wide variety of ridiculously >> nonlinear tuning curves for the VCO--the tuning sensitivity varies >> like 3:1, and the oscillator quits below about 0.7-1.1V (@VDD=5) >> depending on the device. >> >> Which did you pick? ;) >> >> (The metal gate 4046-style oscillators all stink on ice--HC4046, >> HC7046, HC9046, all makers, all horrible. PD2 is nice if you stay >> out of the dead zone.) > > I always wondered what the "phase pulses" were good for. If you don't need > them, my 8-gate wonder* would do, and I don't think it has a dead zone. > > > * > SET -----+------------------------| > | |NAND>--+ > +-------| +--| | > |NAND>--+-----+ | > +--| | | > | | | > +----------|--+ | > | | | > +----------+ | | > | | | > +--| | | > |NAND>-----+ | > +-------| +--| Q > | |NAND>--+------- > +--------------------------------+--| | > | | > +----------|--+ > | | > +----------+ | > | | _ > +--------------------------------+--| | Q > | |NAND>-----+---- > +-------| +--| > |NAND>--+ | > +--| | | > | | | > +----------|--+ | > | | | > +----------+ | | > | | | > +--| | | > |NAND>-----+--+ | > +-------| +--| | > | |NAND>--+ > RESET -----+------------------------| > >The phase pulse output is for lock detection. PD2's output is valid in any condition, and when using PD2, PD1 will have a 50% duty cycle when the loop is locked and also when one of the input signals is missing. I normally just put a window comparator on the PD2 output and use that, since the filtered output pulls to the rail when it's out of lock. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Reply by ●October 18, 20122012-10-18
On Thu, 18 Oct 2012 13:00:19 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>On 10/17/2012 10:19 PM, Bill Sloman wrote: >> On Oct 18, 2:56 am, Phil Hobbs >> <pcdhSpamMeSensel...@electrooptical.net> wrote: >>> On 10/16/2012 11:33 PM, Bill Sloman wrote: >>>> On Oct 17, 1:12 pm, John Larkin >>>> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>>>> On Tue, 16 Oct 2012 10:54:01 -0500, Tim Wescot >>>>> <t...@seemywebsite.please> wrote: >>>>>> On Tue, 16 Oct 2012 11:45:09 -0400, Phil Hobbs wrote: >>>>>>> On 10/15/2012 09:40 PM, Jim Thompson wrote: >>>>>>>> On Mon, 15 Oct 2012 21:22:04 -0400, Phil Hobbs >>>>>>>> <pcdhSpamMeSensel...@electrooptical.net> wrote: >>>>>>>>> On 10/15/2012 9:16 PM, Nico Coesel wrote: >>>>>>>>>> Jim Thompson<To-Email-Use-The-Envelope-I...@On-My-Web-Site.com> >>>>>>>>>> wrote: >> >> <snip> >> >>>>>>>> It occurs to me that the variable current input quits at about 1*VTH. >>>>>>>> So you were trying to get to zero frequency ?:-) >>> >>>>>>>> Add some offset current and it won't quit oscillating. >>> >>>>>>> The metal gate version works over about 1000:1 range, and is very >>>>>>> respectably linear--a few percent IIRC, which is much better than good >>>>>>> enough for inside a PLL. It's really quite pretty in a small way. >>> >>>>>>> The HC parts' nonlinearity is all over the map depending on the vendor, >>>>>>> and that messes up the loop dynamics really badly. Spicing the HC4046 >>>>>>> oscillator will definitely be "a trap for young players", as Dave Jones >>>>>>> says. >>> >>>>>>> With the loop gain varying 3:1 with control voltage, and the centre >>>>>>> frequency being a very poorly controlled function of the RC, you have >>>>>>> to make HC4046 loops ridiculously overdamped in the normal case to avoid >>>>>>> loop instability. If you're using lead-lag compensation, you have to >>>>>>> put the zero a factor of at least 5 below the nominal unity gain cross, >>>>>>> whereas with a well-behaved VCO, you can put it right at the unity gain >>>>>>> cross and have 45 degrees' phase margin. >>> >>>>>>> I'd far rather use an OTA integrator/Schmitt trigger oscillator or >>>>>>> something like that, with the 4046 PDII. >>> >>>>>>> The HC4046 has its uses, but not nearly as many as if it were really a >>>>>>> faster CD4046. >>> >>>>>> Oh, I should know -- OTA Integrator? >>> >>>>>> I wish someone would take the 3-state phase detector from the 4046 and >>>>>> put it into a 6-pin SOT and call it TinyLogic or whatever. It would save >>>>>> ever so much board space. >>> >>>>> We build something like the charge-pump detector into FPGAs. We use an >>>>> external dual schottky diode for the pump-up and pump-down blips, to >>>>> avoid the deadband that tri-state charge pumps tend to create. We can >>>>> also delta-sigma those outputs to control our VXCO open-loop. >>> >>>>> The little function generator chips make nice wide-range, low >>>>> frequency VCOs. Exar, Maxim? >>> >>>> And there used to be a fairly wide range of chips available that were >>>> designed to be very linear VCOs, intended for use as voltage-to- >>>> frequency A/D converters. Analog Devices still seems to be in the >>>> business >>> >>>> http://www.analog.com/en/analog-to-digital-converters/voltage-to-freq... >>> >>>> Phil Hobbs probably should be using the AD650 - though I can't >>>> recommend it on the basis of personal expereience >>> >>> Fifteen bucks for a 1-MHz V-F converter? Not me, especially not inside >>> a PLL where 1% linearity is way better than good enough. >> >> The point was that these are legacy parts, and correspondingly >> expensive. The LM331 which offers even better linearity, but only goes >> to 100kHz, turns out to be still available to, but at $6 each in small >> quantities. I was rather hoping to provoke a response from somebody >> who is still using that kind of part. >> >>> I'd happily use a metal-gate 4046 at frequencies where they work--all >>> you need is a resistor to ground from the PD2 output to pull it off the >>> dead zone. >>> >>> Above a megahertz or so, a current-programmed triangle wave oscillator >>> is good, >> >> Sure. A 1GHz gbw op amp could take you quite a way above 1MHz. >> >>> or else a linearized LC VCO. You can get linearities of better >>> than 10% in varactor-tuned VCOs by putting in a couple of off-stage >>> resonances. >> >> Messy. I'd be thinking of a digitally controlled Direct Digital >> Synthesis chip, which would be a lot tidier and would probably have a >> lower jitter (if you low-pass filtered the synthesised sine wave >> properly). For a seriously low jitter option, a DDS-like system >> including an MC100E195 might be interesting - if complicated. Coping >> with the temperature dependence of the delay through the MC100E195 >> might require Peltier junction or a self-calibrating scheme if you >> really wanted to exploit the full capacity of the MC100E195. >> >> -- >> Bill Sloman, Sydney >> > >Digital PLLs don't have the performance of analogue ones, and are far, >far more complicated and power hungry. My usual use for PLLs is >demodulation rather than frequency synthesis, so DDSes are pretty much >beside the point. > >You can get inductors in 2% tolerances, and the varactors of course are >variable (and also good to +-5% to 8%), so you don't need tweaks to get >a very respectable linearity improvement. That means that you can be >more aggressive on the loop compensation, and the improved performance >is worth a lot. > >Cheers > >Phil HobbsWe have considered using a phase detector and a DDS, 100% digital PLL, inside an FPGA to be able to do i/q demodulation of digitized sinewave signals. It sounded like fun, but we never had a firm application (ie, paying customer) to justify doing it. In one case, it would have been AC line stuff, 50 or 60 or 400 Hz, fairly narrowband (except aircraft 400 Hz is all over the place.) In another, it would be synchro/LVDT, pretty much audio kind of range. The digital PLL takes no parts... it's just a heap of VHDL. -- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
Reply by ●October 18, 20122012-10-18
On 10/18/2012 02:59 PM, John Larkin wrote:> On Thu, 18 Oct 2012 13:00:19 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> On 10/17/2012 10:19 PM, Bill Sloman wrote: >>> On Oct 18, 2:56 am, Phil Hobbs >>> <pcdhSpamMeSensel...@electrooptical.net> wrote: >>>> On 10/16/2012 11:33 PM, Bill Sloman wrote: >>>>> On Oct 17, 1:12 pm, John Larkin >>>>> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>>>>> On Tue, 16 Oct 2012 10:54:01 -0500, Tim Wescot >>>>>> <t...@seemywebsite.please> wrote: >>>>>>> On Tue, 16 Oct 2012 11:45:09 -0400, Phil Hobbs wrote: >>>>>>>> On 10/15/2012 09:40 PM, Jim Thompson wrote: >>>>>>>>> On Mon, 15 Oct 2012 21:22:04 -0400, Phil Hobbs >>>>>>>>> <pcdhSpamMeSensel...@electrooptical.net> wrote: >>>>>>>>>> On 10/15/2012 9:16 PM, Nico Coesel wrote: >>>>>>>>>>> Jim Thompson<To-Email-Use-The-Envelope-I...@On-My-Web-Site.com> >>>>>>>>>>> wrote: >>> >>> <snip> >>> >>>>>>>>> It occurs to me that the variable current input quits at about 1*VTH. >>>>>>>>> So you were trying to get to zero frequency ?:-) >>>> >>>>>>>>> Add some offset current and it won't quit oscillating. >>>> >>>>>>>> The metal gate version works over about 1000:1 range, and is very >>>>>>>> respectably linear--a few percent IIRC, which is much better than good >>>>>>>> enough for inside a PLL. It's really quite pretty in a small way. >>>> >>>>>>>> The HC parts' nonlinearity is all over the map depending on the vendor, >>>>>>>> and that messes up the loop dynamics really badly. Spicing the HC4046 >>>>>>>> oscillator will definitely be "a trap for young players", as Dave Jones >>>>>>>> says. >>>> >>>>>>>> With the loop gain varying 3:1 with control voltage, and the centre >>>>>>>> frequency being a very poorly controlled function of the RC, you have >>>>>>>> to make HC4046 loops ridiculously overdamped in the normal case to avoid >>>>>>>> loop instability. If you're using lead-lag compensation, you have to >>>>>>>> put the zero a factor of at least 5 below the nominal unity gain cross, >>>>>>>> whereas with a well-behaved VCO, you can put it right at the unity gain >>>>>>>> cross and have 45 degrees' phase margin. >>>> >>>>>>>> I'd far rather use an OTA integrator/Schmitt trigger oscillator or >>>>>>>> something like that, with the 4046 PDII. >>>> >>>>>>>> The HC4046 has its uses, but not nearly as many as if it were really a >>>>>>>> faster CD4046. >>>> >>>>>>> Oh, I should know -- OTA Integrator? >>>> >>>>>>> I wish someone would take the 3-state phase detector from the 4046 and >>>>>>> put it into a 6-pin SOT and call it TinyLogic or whatever. It would save >>>>>>> ever so much board space. >>>> >>>>>> We build something like the charge-pump detector into FPGAs. We use an >>>>>> external dual schottky diode for the pump-up and pump-down blips, to >>>>>> avoid the deadband that tri-state charge pumps tend to create. We can >>>>>> also delta-sigma those outputs to control our VXCO open-loop. >>>> >>>>>> The little function generator chips make nice wide-range, low >>>>>> frequency VCOs. Exar, Maxim? >>>> >>>>> And there used to be a fairly wide range of chips available that were >>>>> designed to be very linear VCOs, intended for use as voltage-to- >>>>> frequency A/D converters. Analog Devices still seems to be in the >>>>> business >>>> >>>>> http://www.analog.com/en/analog-to-digital-converters/voltage-to-freq... >>>> >>>>> Phil Hobbs probably should be using the AD650 - though I can't >>>>> recommend it on the basis of personal expereience >>>> >>>> Fifteen bucks for a 1-MHz V-F converter? Not me, especially not inside >>>> a PLL where 1% linearity is way better than good enough. >>> >>> The point was that these are legacy parts, and correspondingly >>> expensive. The LM331 which offers even better linearity, but only goes >>> to 100kHz, turns out to be still available to, but at $6 each in small >>> quantities. I was rather hoping to provoke a response from somebody >>> who is still using that kind of part. >>> >>>> I'd happily use a metal-gate 4046 at frequencies where they work--all >>>> you need is a resistor to ground from the PD2 output to pull it off the >>>> dead zone. >>>> >>>> Above a megahertz or so, a current-programmed triangle wave oscillator >>>> is good, >>> >>> Sure. A 1GHz gbw op amp could take you quite a way above 1MHz. >>> >>>> or else a linearized LC VCO. You can get linearities of better >>>> than 10% in varactor-tuned VCOs by putting in a couple of off-stage >>>> resonances. >>> >>> Messy. I'd be thinking of a digitally controlled Direct Digital >>> Synthesis chip, which would be a lot tidier and would probably have a >>> lower jitter (if you low-pass filtered the synthesised sine wave >>> properly). For a seriously low jitter option, a DDS-like system >>> including an MC100E195 might be interesting - if complicated. Coping >>> with the temperature dependence of the delay through the MC100E195 >>> might require Peltier junction or a self-calibrating scheme if you >>> really wanted to exploit the full capacity of the MC100E195. >>> >>> -- >>> Bill Sloman, Sydney >>> >> >> Digital PLLs don't have the performance of analogue ones, and are far, >> far more complicated and power hungry. My usual use for PLLs is >> demodulation rather than frequency synthesis, so DDSes are pretty much >> beside the point. >> >> You can get inductors in 2% tolerances, and the varactors of course are >> variable (and also good to +-5% to 8%), so you don't need tweaks to get >> a very respectable linearity improvement. That means that you can be >> more aggressive on the loop compensation, and the improved performance >> is worth a lot. >> >> Cheers >> >> Phil Hobbs > > We have considered using a phase detector and a DDS, 100% digital PLL, > inside an FPGA to be able to do i/q demodulation of digitized sinewave > signals. It sounded like fun, but we never had a firm application (ie, > paying customer) to justify doing it. > > In one case, it would have been AC line stuff, 50 or 60 or 400 Hz, > fairly narrowband (except aircraft 400 Hz is all over the place.) In > another, it would be synchro/LVDT, pretty much audio kind of range. > > The digital PLL takes no parts... it's just a heap of VHDL.If you already have an FPGA, sure, dump it in with all the other crap. ;) A good diode phase detector such as an MPD-1 makes it a pleasure to build first-class PLLs. Lots of output, zilch noise, low and stable offset voltage, easy to drive from logic if you need to. Good medicine. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Reply by ●October 18, 20122012-10-18
Am 18.10.2012 21:17, schrieb Phil Hobbs:> On 10/18/2012 02:59 PM, John Larkin wrote:>> The digital PLL takes no parts... it's just a heap of VHDL. > > If you already have an FPGA, sure, dump it in with all the other crap. ;) > > A good diode phase detector such as an MPD-1 makes it a pleasure to > build first-class PLLs. Lots of output, zilch noise, low and stable > offset voltage, easy to drive from logic if you need to. Good medicine.As far as I remember that's the very first time I disagree with you, but for this subject I do. A customer of mine builds world class analog DLLs & PLLs for special navigation and timing systems, but when every ps counts, analog is really running out of steam. Just try to buy a state-of-the-art S&H. You get it if you buy a 16 bit /200 MHz ADC, too. There is no such thing as "low and stable offset voltage". There is offset voltage, and that dictates unpleasant architecture decisions because the appearant channel delay varies depending on what state of a QPDM signal you happen to lock to. Or so. We are about to digitize in L-Band, the downconverter / polyphase filter will perhaps be 8-way. That means 8 DDS-es, 8 sin/cos tables, 8 complex mixers etc, dissipating lots of power, but that power will not shift the phase/delay of some analog low pass. ;-) have a good night, Gerhard
Reply by ●October 18, 20122012-10-18
On 2012-10-18 20:59, John Larkin wrote:> On Thu, 18 Oct 2012 13:00:19 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: >> You can get inductors in 2% tolerances, and the varactors of course are >> variable (and also good to +-5% to 8%), so you don't need tweaks to get >> a very respectable linearity improvement. That means that you can be >> more aggressive on the loop compensation, and the improved performance >> is worth a lot. >> >> Cheers >> >> Phil Hobbs > > We have considered using a phase detector and a DDS, 100% digital PLL, > inside an FPGA to be able to do i/q demodulation of digitized sinewave > signals. It sounded like fun, but we never had a firm application (ie, > paying customer) to justify doing it.I have this particle beam trajectory measurement system where lots of fully digital PLLs are used to follow bunches of protons around a particle accelerator. It spits out the bunch trajectories at an aggregate rate of up to 280M bunch positions per second. All FPGAs. A British firm built it for me. Operators love it. I'm in the process of making a second system for another accelerator. Jeroen Belleman
