In comp.arch.fpga John Larkin <jjlarkin@highnotlandthistechnologypart.com> wrote: (snip, someone wrote)>>>What do mean by "30mV voltage drop across the BGA itself" ? Does that >>>mean PCB plane drop, or rather BGA balls to chip internal voltage?(snip)> I can sense an I/O bank supply voltage by just pulling an output up, > but core voltage is harder to get at. I could swipe one ball out of, > say, ten paralleled ones, I guess, if I were sure they were really > paralleled.As far as I know, you aren't supposed to do that. Even if they are paralleled internally, there might be enough voltage drop across the internal connection to cause problems.> Are core voltages segmented on most FPGAs, or are all the Vcc_core > balls connected to one power net?My choice would be to run a wire out from one of the power balls and measure the voltage on that wire. You could even use a power supply with a remote sense, such that it would adjust its output to get the right voltage on the sense line. Maybe even sense lines for both Vcc and ground. If you don't have remote sense on the power supply, just use them as a remote voltage measurment. -- glen
voltage drop on STRATIX FPGA supply planes
Started by ●January 6, 2012
Reply by ●January 8, 20122012-01-08
Reply by ●January 8, 20122012-01-08
On Sun, 08 Jan 2012 10:48:37 -0800, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:>On Sun, 08 Jan 2012 10:53:56 -0500, legg <legg@nospam.magma.ca> wrote: > >>On Fri, 06 Jan 2012 08:51:24 -0800, John Larkin >><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Fri, 6 Jan 2012 01:55:03 -0800 (PST), "colin_toogood@yahoo.com" >>><colin_toogood@yahoo.com> wrote: >>> >>>>Guys >>>> >>>>I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power >>>>plane. It is showing a 30mV voltage drop across the BGA itself, let >>>>alone getting the power to the BGA which is dropping another 50mV. >>>> >>>>Surely the 30mV cannot be true as there is a power plane in the BGA >>>>package itself. >>>> >>>>Historically I would look at the size of the plane and assume that >>>>everything is fine and I can't help wondering whether this worst case >>>>analysis is a bit pointless. >>>> >>>>Any opinions? >>>> >>>>BTW I'm already just beyond the PCB thickness I'm allowed so I can't >>>>just use thicker copper. >>>> >>>>Colin >>>> >>>>PS. sorry about using Google, I'm sitting in the UK behind a firewall >>>>controlled by an Indian call centre. >>> >>>How much current are you expecting in the core? >>> >>>What do mean by "30mV voltage drop across the BGA itself" ? Does that >>>mean PCB plane drop, or rather BGA balls to chip internal voltage? >>> >>>The chip vendors should give us one remote-sense feedback/measurement >>>ball. >>> >>>John >>> >>You can probably already take your pick.....if you sacrifice the >>immediate local signal functions. >> >>RL > >I can sense an I/O bank supply voltage by just pulling an output up, >but core voltage is harder to get at. I could swipe one ball out of, >say, ten paralleled ones, I guess, if I were sure they were really >paralleled.Probably not a good idea. You'll be leaving one corner of the power mesh sagging. A sense to the pad might not be a bad idea, though. ...if you can control the regulator.>Are core voltages segmented on most FPGAs, or are all the Vcc_core >balls connected to one power net?Paralleled.
Reply by ●January 9, 20122012-01-09
I should have probably have clarified the POL approach for a single FPGA. Some of the regulators we use are capable of being used in tandem so you might use 2 or 4 of them together. They do need to be tied together to avoid issues caused by large differences. This does avoid all of the current being delivered in a small contact area which can reduce losses and is sort of similar to the approach taken by most FPGAs themselves. It's also worth pointing out that there are always differences between individual FPGA power balls but they are small and FPGAs do cope with that. Sometimes part of the effect is more current gets dragged through an individual "good" ball causing more volts drop and crudely self regulating. If we are looking at losses don't forget the vias. We recently did a 50A circuit on our Broaddown3 board and to keep losses reasonable we put something like 30 vias between the regulators arms and the internal plane. This is more extreme than most people will need to think about and you can argue about which size of via to use as there are some trades here in numbner of vias versus size. In some boards like our Merrick1 where we used a brick dc/dc, instead of an on-board regulator approach, we can have 50A going though a single hole / leg. It does help a lot having the leg to carry current but still means a lot of current in a local board area to handle. Something to consider are copper filled vias when dc loss is important. They are a specalist technique also used to reduce via losses but do come at a cost and tend to limit the number of PCB manufacturers you can use. John Adair Enterpoint Ltd. On Jan 8, 10:14=A0pm, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> wrote:> On Sun, 08 Jan 2012 10:48:37 -0800, John Larkin > > > > > > > > > > <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > >On Sun, 08 Jan 2012 10:53:56 -0500, legg <l...@nospam.magma.ca> wrote: > > >>On Fri, 06 Jan 2012 08:51:24 -0800, John Larkin > >><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > > >>>On Fri, 6 Jan 2012 01:55:03 -0800 (PST), "colin_toog...@yahoo.com" > >>><colin_toog...@yahoo.com> wrote: > > >>>>Guys > > >>>>I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power > >>>>plane. It is showing a 30mV voltage drop across the BGA itself, let > >>>>alone getting the power to the BGA which is dropping another 50mV. > > >>>>Surely the 30mV cannot be true as there is a power plane in the BGA > >>>>package itself. > > >>>>Historically I would look at the size of the plane and assume that > >>>>everything is fine and I can't help wondering whether this worst case > >>>>analysis is a bit pointless. > > >>>>Any opinions? > > >>>>BTW I'm already just beyond the PCB thickness I'm allowed so I can't > >>>>just use thicker copper. > > >>>>Colin > > >>>>PS. sorry about using Google, I'm sitting in the UK behind a firewall > >>>>controlled by an Indian call centre. > > >>>How much current are you expecting in the core? > > >>>What do mean by "30mV voltage drop across the BGA itself" ? Does that > >>>mean PCB plane drop, or rather BGA balls to chip internal voltage? > > >>>The chip vendors should give us one remote-sense feedback/measurement > >>>ball. > > >>>John > > >>You can probably already take your pick.....if you sacrifice the > >>immediate local signal functions. > > >>RL > > >I can sense an I/O bank supply voltage by just pulling an output up, > >but core voltage is harder to get at. I could swipe one ball out of, > >say, ten paralleled ones, I guess, if I were sure they were really > >paralleled. > > Probably not a good idea. =A0You'll be leaving one corner of the power me=sh> sagging. =A0A sense to the pad might not be a bad idea, though. =A0...if =you can> control the regulator. > > >Are core voltages segmented on most FPGAs, or are all the Vcc_core > >balls connected to one power net? > > Paralleled.
