I should have probably have clarified the POL approach for a single
FPGA. Some of the regulators we use are capable of being used in
tandem so you might use 2 or 4 of them together. They do need to be
tied together to avoid issues caused by large differences. This does
avoid all of the current being delivered in a small contact area which
can reduce losses and is sort of similar to the approach taken by most
FPGAs themselves. It's also worth pointing out that there are always
differences between individual FPGA power balls but they are small and
FPGAs do cope with that. Sometimes part of the effect is more current
gets dragged through an individual "good" ball causing more volts drop
and crudely self regulating.

If we are looking at losses don't forget the vias. We recently did a
50A circuit on our Broaddown3 board and to keep losses reasonable we
put something like 30 vias between the regulators arms and the
internal plane. This is more extreme than most people will need to
think about and you can argue about which size of via to use as there
are some trades here in numbner of vias versus size. In some boards
like our Merrick1 where we used a brick dc/dc, instead of an on-board
regulator approach, we can have 50A going though a single hole / leg.
It does help a lot having the leg to carry current but still means a
lot of current in a local board area to handle.

Something to consider are copper filled vias when dc loss is
important. They are a specalist technique also used to reduce via
losses but do come at a cost and tend to limit the number of PCB
manufacturers you can use.

John Adair
Enterpoint Ltd.

On Jan 8, 10:14=A0pm, "k...@att.bizzzzzzzzzzzz"
<k...@att.bizzzzzzzzzzzz> wrote:
> On Sun, 08 Jan 2012 10:48:37 -0800, John Larkin
>
>
>
>
>
>
>
>
>
> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> >On Sun, 08 Jan 2012 10:53:56 -0500, legg <l...@nospam.magma.ca> wrote:
>
> >>On Fri, 06 Jan 2012 08:51:24 -0800, John Larkin
> >><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>
> >>>On Fri, 6 Jan 2012 01:55:03 -0800 (PST), "colin_toog...@yahoo.com"
> >>><colin_toog...@yahoo.com> wrote:
>
> >>>>Guys
>
> >>>>I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power
> >>>>plane. It is showing a 30mV voltage drop across the BGA itself, let
> >>>>alone getting the power to the BGA which is dropping another 50mV.
>
> >>>>Surely the 30mV cannot be true as there is a power plane in the BGA
> >>>>package itself.
>
> >>>>Historically I would look at the size of the plane and assume that
> >>>>everything is fine and I can't help wondering whether this worst case
> >>>>analysis is a bit pointless.
>
> >>>>Any opinions?
>
> >>>>BTW I'm already just beyond the PCB thickness I'm allowed so I can't
> >>>>just use thicker copper.
>
> >>>>Colin
>
> >>>>PS. sorry about using Google, I'm sitting in the UK behind a firewall
> >>>>controlled by an Indian call centre.
>
> >>>How much current are you expecting in the core?
>
> >>>What do mean by "30mV voltage drop across the BGA itself" ? Does that
> >>>mean PCB plane drop, or rather BGA balls to chip internal voltage?
>
> >>>The chip vendors should give us one remote-sense feedback/measurement
> >>>ball.
>
> >>>John
>
> >>You can probably already take your pick.....if you sacrifice the
> >>immediate local signal functions.
>
> >>RL
>
> >I can sense an I/O bank supply voltage by just pulling an output up,
> >but core voltage is harder to get at. I could swipe one ball out of,
> >say, ten paralleled ones, I guess, if I were sure they were really
> >paralleled.
>
> Probably not a good idea. =A0You'll be leaving one corner of the power me=
sh
> sagging. =A0A sense to the pad might not be a bad idea, though. =A0...if =
you can
> control the regulator.
>
> >Are core voltages segmented on most FPGAs, or are all the Vcc_core
> >balls connected to one power net?
>
> Paralleled.

On Sun, 08 Jan 2012 10:48:37 -0800, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

>On Sun, 08 Jan 2012 10:53:56 -0500, legg <legg@nospam.magma.ca> wrote:
>
>>On Fri, 06 Jan 2012 08:51:24 -0800, John Larkin
>><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>>On Fri, 6 Jan 2012 01:55:03 -0800 (PST), "colin_toogood@yahoo.com"
>>><colin_toogood@yahoo.com> wrote:
>>>
>>>>Guys
>>>>
>>>>I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power
>>>>plane. It is showing a 30mV voltage drop across the BGA itself, let
>>>>alone getting the power to the BGA which is dropping another 50mV.
>>>>
>>>>Surely the 30mV cannot be true as there is a power plane in the BGA
>>>>package itself.
>>>>
>>>>Historically I would look at the size of the plane and assume that
>>>>everything is fine and I can't help wondering whether this worst case
>>>>analysis is a bit pointless.
>>>>
>>>>Any opinions?
>>>>
>>>>BTW I'm already just beyond the PCB thickness I'm allowed so I can't
>>>>just use thicker copper.
>>>>
>>>>Colin
>>>>
>>>>PS. sorry about using Google, I'm sitting in the UK behind a firewall
>>>>controlled by an Indian call centre.
>>>
>>>How much current are you expecting in the core?
>>>
>>>What do mean by "30mV voltage drop across the BGA itself" ? Does that
>>>mean PCB plane drop, or rather BGA balls to chip internal voltage?
>>>
>>>The chip vendors should give us one remote-sense feedback/measurement
>>>ball.
>>>
>>>John
>>>
>>You can probably already take your pick.....if you sacrifice the
>>immediate local signal functions.
>>
>>RL
>
>I can sense an I/O bank supply voltage by just pulling an output up,
>but core voltage is harder to get at. I could swipe one ball out of,
>say, ten paralleled ones, I guess, if I were sure they were really
>paralleled.

Probably not a good idea.  You'll be leaving one corner of the power mesh
sagging.  A sense to the pad might not be a bad idea, though.  ...if you can
control the regulator.

>Are core voltages segmented on most FPGAs, or are all the Vcc_core
>balls connected to one power net? 

Paralleled.  

In comp.arch.fpga John Larkin <jjlarkin@highnotlandthistechnologypart.com> wrote:

(snip, someone wrote)
>>>What do mean by "30mV voltage drop across the BGA itself" ? Does that
>>>mean PCB plane drop, or rather BGA balls to chip internal voltage?

(snip)
> I can sense an I/O bank supply voltage by just pulling an output up,
> but core voltage is harder to get at. I could swipe one ball out of,
> say, ten paralleled ones, I guess, if I were sure they were really
> paralleled.

As far as I know, you aren't supposed to do that. Even if they are
paralleled internally, there might be enough voltage drop across the
internal connection to cause problems.

> Are core voltages segmented on most FPGAs, or are all the Vcc_core
> balls connected to one power net? 

My choice would be to run a wire out from one of the power balls and
measure the voltage on that wire. You could even use a power supply with
a remote sense, such that it would adjust its output to get the right
voltage on the sense line. Maybe even sense lines for both Vcc and
ground.

If you don't have remote sense on the power supply, just use them as
a remote voltage measurment.

-- glen

On Sun, 08 Jan 2012 10:53:56 -0500, legg <legg@nospam.magma.ca> wrote:

>On Fri, 06 Jan 2012 08:51:24 -0800, John Larkin
><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:
>
>>On Fri, 6 Jan 2012 01:55:03 -0800 (PST), "colin_toogood@yahoo.com"
>><colin_toogood@yahoo.com> wrote:
>>
>>>Guys
>>>
>>>I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power
>>>plane. It is showing a 30mV voltage drop across the BGA itself, let
>>>alone getting the power to the BGA which is dropping another 50mV.
>>>
>>>Surely the 30mV cannot be true as there is a power plane in the BGA
>>>package itself.
>>>
>>>Historically I would look at the size of the plane and assume that
>>>everything is fine and I can't help wondering whether this worst case
>>>analysis is a bit pointless.
>>>
>>>Any opinions?
>>>
>>>BTW I'm already just beyond the PCB thickness I'm allowed so I can't
>>>just use thicker copper.
>>>
>>>Colin
>>>
>>>PS. sorry about using Google, I'm sitting in the UK behind a firewall
>>>controlled by an Indian call centre.
>>
>>How much current are you expecting in the core?
>>
>>What do mean by "30mV voltage drop across the BGA itself" ? Does that
>>mean PCB plane drop, or rather BGA balls to chip internal voltage?
>>
>>The chip vendors should give us one remote-sense feedback/measurement
>>ball.
>>
>>John
>>
>You can probably already take your pick.....if you sacrifice the
>immediate local signal functions.
>
>RL

I can sense an I/O bank supply voltage by just pulling an output up,
but core voltage is harder to get at. I could swipe one ball out of,
say, ten paralleled ones, I guess, if I were sure they were really
paralleled.

Are core voltages segmented on most FPGAs, or are all the Vcc_core
balls connected to one power net? 

John

On Fri, 06 Jan 2012 08:51:24 -0800, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

>On Fri, 6 Jan 2012 01:55:03 -0800 (PST), "colin_toogood@yahoo.com"
><colin_toogood@yahoo.com> wrote:
>
>>Guys
>>
>>I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power
>>plane. It is showing a 30mV voltage drop across the BGA itself, let
>>alone getting the power to the BGA which is dropping another 50mV.
>>
>>Surely the 30mV cannot be true as there is a power plane in the BGA
>>package itself.
>>
>>Historically I would look at the size of the plane and assume that
>>everything is fine and I can't help wondering whether this worst case
>>analysis is a bit pointless.
>>
>>Any opinions?
>>
>>BTW I'm already just beyond the PCB thickness I'm allowed so I can't
>>just use thicker copper.
>>
>>Colin
>>
>>PS. sorry about using Google, I'm sitting in the UK behind a firewall
>>controlled by an Indian call centre.
>
>How much current are you expecting in the core?
>
>What do mean by "30mV voltage drop across the BGA itself" ? Does that
>mean PCB plane drop, or rather BGA balls to chip internal voltage?
>
>The chip vendors should give us one remote-sense feedback/measurement
>ball.
>
>John
>
You can probably already take your pick.....if you sacrifice the
immediate local signal functions.

RL

Colin

I'm not surprised at the numbers you are quoting. Personnally I would
be more worried by the dynamic current variation and the effects that
that the resistance and the parasitic inductance can have. If your
decoupling isn't good enough ,and your power plane forms part of that,
the effect of getting it wrong is far harder to debug than a static
voltage issue.

Going back to the static losses using parallel planes is a good option
as mentioned elsewhere. You can also go for heavier weights of
copperin your power planes but that tends to restrict you track and
gap you can use. This also related to the abilities of the
manufacturer of your PCB and sometimes the price you pay for a PCB.
There are also speciality PCB techniques like bonding busbars to the
PCB to reduce the resistive loss but usually it's better to use a
point of load technique and localise the high current areas. You can
see examples of that technique in our extrene Merrick family of boards
which are aimed at the HPC marketplace. Our recently annouced Merrick3
http://enterpoint.co.uk/products/asic-development-high-performance-computin=
g/merrick-3/
uses 6 12A circuits just in PCIe card format for the core voltage.
Internal distribution is by 12V rail in this case. Our new revision of
our Merrick1 board will take this further and there are 20 POL
regulators just for the core voltage.

One easy thing to do is to set you power supply on the higher end of
the input specification at light load. Tolerance of your power supply
is important if you use this method. Then even after losses hopefully
your FPGA die is still receiving voltage within spec.

Many FPGAs will still operate out of spec although may not meet timing
spec. Sometimes this can be used to solve a particular power issue but
use with care.

John Adair
Enterpoint Ltd. - Home of FPGA HPC solutions.

On Jan 6, 9:55=A0am, "colin_toog...@yahoo.com" <colin_toog...@yahoo.com>
wrote:
> Guys
>
> I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power
> plane. It is showing a 30mV voltage drop across the BGA itself, let
> alone getting the power to the BGA which is dropping another 50mV.
>
> Surely the 30mV cannot be true as there is a power plane in the BGA
> package itself.
>
> Historically I would look at the size of the plane and assume that
> everything is fine and I can't help wondering whether this worst case
> analysis is a bit pointless.
>
> Any opinions?
>
> BTW I'm already just beyond the PCB thickness I'm allowed so I can't
> just use thicker copper.
>
> Colin
>
> PS. sorry about using Google, I'm sitting in the UK behind a firewall
> controlled by an Indian call centre.

On Jan 6, 6:53=A0am, Allan Herriman <allanherri...@hotmail.com> wrote:
> On Fri, 06 Jan 2012 01:55:03 -0800, colin_toog...@yahoo.com wrote:
> > Guys
>
> > I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power
> > plane. It is showing a 30mV voltage drop across the BGA itself, let
> > alone getting the power to the BGA which is dropping another 50mV.
>
> > Surely the 30mV cannot be true as there is a power plane in the BGA
> > package itself.
>
> > Historically I would look at the size of the plane and assume that
> > everything is fine and I can't help wondering whether this worst case
> > analysis is a bit pointless.
>
> > Any opinions?
>
> > BTW I'm already just beyond the PCB thickness I'm allowed so I can't
> > just use thicker copper.
>
> I've had this issue in recent designs too. =A0Currents are higher, voltag=
es
> are lower (1.0, 0.9V, etc), supply tolerances are tighter (3% instead of
> 5% now for some parts) but copper doesn't seem conduct any better :(
>
> About the only thing that's improving is the DC/DC converter; some parts
> have a reference precision better than 1% now. =A0Transient response is
> also better due to faster switching frequencies and cheap, large, low ESR
> caps.
>
> The Cu in the BGA is thin. =A0I don't know its sheet resistance, but it's
> probably greater than the (roughly) 1mohm / square of the inner layers of
> your PCB. =A0At 20 or 30 amperes, you don't need many squares to get a
> voltage drop that puts you outside the supply voltage tolerance of the
> FPGA.
>
> In my last "high power" FPGA design, we ended up with a plane on an inner
> (1/2 oz) layer in parallel with a fill on an outer (1oz) layer for the
> core supply. =A0The layout guy hated doing it, but it gave adequate resul=
ts.
>
> It might also be possible to use smaller vias in your BGA fanout to
> reduce the "swiss cheese" effect on your planes, but I haven't tried that
> in an actual design.
>
> I've noticed that some PC motherboard manufacturers are advertising 2oz
> copper as a feature, so it's not just FPGA folk that are feeling the pain=
.
>
> Regards,
> Allan

If you have an old version .dxf file [with scale] of your PCB plane
and identify current magnitudes and injection points, tell me the two
cutout diameters to test; I could compare the effect of the 'swiss
cheese' on the voltage drop across the plane. Actually do 3D voltage
plots showing NO HOLES, Small Holes, Large Holes, and Delta Voltage
comparisons.

I created a PCB Layout Tool that quantifies the Ground Plane Noise
distributed across a PCB caused by currents from digital logic.

Provide an email address that accepts .zip and I can send small
example images of results in .zip attachment. approx 72kB

[The purpose for creating the tool was to confirm parts placement and
efficacy of plane cuts to keep GND noise below 1/4 LSB of the 24 bit
ADC on the same PCB as the microcontroller. I simply got tired of
'shooting from the hip', worrying if the cut(s) is enough, and
answering questions with, "In my opinion,..." Plus, wanted this PCB
layout 'right' the first time.]

On 06 Jan 2012 15:07:31 GMT, Allan Herriman
<allanherriman@hotmail.com> wrote:

>On Fri, 06 Jan 2012 13:53:05 +0000, Allan Herriman wrote:
>
>> On Fri, 06 Jan 2012 01:55:03 -0800, colin_toogood@yahoo.com wrote:
>> 
>>> Guys
>>> 
>>> I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power
>>> plane. It is showing a 30mV voltage drop across the BGA itself, let
>>> alone getting the power to the BGA which is dropping another 50mV.
>>> 
>>> Surely the 30mV cannot be true as there is a power plane in the BGA
>>> package itself.
>>> 
>>> Historically I would look at the size of the plane and assume that
>>> everything is fine and I can't help wondering whether this worst case
>>> analysis is a bit pointless.
>>> 
>>> Any opinions?
>>> 
>>> BTW I'm already just beyond the PCB thickness I'm allowed so I can't
>>> just use thicker copper.
>> 
>> 
>> I've had this issue in recent designs too.  Currents are higher,
>> voltages are lower (1.0, 0.9V, etc), supply tolerances are tighter (3%
>> instead of 5% now for some parts) but copper doesn't seem conduct any
>> better :(
>> 
>> About the only thing that's improving is the DC/DC converter; some parts
>> have a reference precision better than 1% now.  Transient response is
>> also better due to faster switching frequencies and cheap, large, low
>> ESR caps.
>> 
>> 
>> The Cu in the BGA is thin.  I don't know its sheet resistance, but it's
>> probably greater than the (roughly) 1mohm / square of the inner layers
>> of your PCB.  At 20 or 30 amperes, you don't need many squares to get a
>> voltage drop that puts you outside the supply voltage tolerance of the
>> FPGA.
>> 
>> In my last "high power" FPGA design, we ended up with a plane on an
>> inner (1/2 oz) layer in parallel with a fill on an outer (1oz) layer for
>> the core supply.  The layout guy hated doing it, but it gave adequate
>> results.
>> 
>> It might also be possible to use smaller vias in your BGA fanout to
>> reduce the "swiss cheese" effect on your planes, but I haven't tried
>> that in an actual design.
>> 
>> I've noticed that some PC motherboard manufacturers are advertising 2oz
>> copper as a feature, so it's not just FPGA folk that are feeling the
>> pain.
>
>
>Another thing I've been doing is to boost the nominal voltage slightly.


I do that, namely go 50 mV or so high out of my switchers,
anticipating copper losses.

I think the tight voltage specs on these FPGAs is part of the overall
speed budget. If you're not pushing the clock rate/timing/temperature
margins, it's not as critical. I also like to power-supply margin test
working units, just to see how much wiggle room we have. Usually it's
a lot.

John

On Fri, 6 Jan 2012 01:55:03 -0800 (PST), "colin_toogood@yahoo.com"
<colin_toogood@yahoo.com> wrote:

>Guys
>
>I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power
>plane. It is showing a 30mV voltage drop across the BGA itself, let
>alone getting the power to the BGA which is dropping another 50mV.
>
>Surely the 30mV cannot be true as there is a power plane in the BGA
>package itself.
>
>Historically I would look at the size of the plane and assume that
>everything is fine and I can't help wondering whether this worst case
>analysis is a bit pointless.
>
>Any opinions?
>
>BTW I'm already just beyond the PCB thickness I'm allowed so I can't
>just use thicker copper.
>
>Colin
>
>PS. sorry about using Google, I'm sitting in the UK behind a firewall
>controlled by an Indian call centre.

How much current are you expecting in the core?

What do mean by "30mV voltage drop across the BGA itself" ? Does that
mean PCB plane drop, or rather BGA balls to chip internal voltage?

The chip vendors should give us one remote-sense feedback/measurement
ball.

John

On Fri, 06 Jan 2012 13:53:05 +0000, Allan Herriman wrote:

> On Fri, 06 Jan 2012 01:55:03 -0800, colin_toogood@yahoo.com wrote:
> 
>> Guys
>> 
>> I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power
>> plane. It is showing a 30mV voltage drop across the BGA itself, let
>> alone getting the power to the BGA which is dropping another 50mV.
>> 
>> Surely the 30mV cannot be true as there is a power plane in the BGA
>> package itself.
>> 
>> Historically I would look at the size of the plane and assume that
>> everything is fine and I can't help wondering whether this worst case
>> analysis is a bit pointless.
>> 
>> Any opinions?
>> 
>> BTW I'm already just beyond the PCB thickness I'm allowed so I can't
>> just use thicker copper.
> 
> 
> I've had this issue in recent designs too.  Currents are higher,
> voltages are lower (1.0, 0.9V, etc), supply tolerances are tighter (3%
> instead of 5% now for some parts) but copper doesn't seem conduct any
> better :(
> 
> About the only thing that's improving is the DC/DC converter; some parts
> have a reference precision better than 1% now.  Transient response is
> also better due to faster switching frequencies and cheap, large, low
> ESR caps.
> 
> 
> The Cu in the BGA is thin.  I don't know its sheet resistance, but it's
> probably greater than the (roughly) 1mohm / square of the inner layers
> of your PCB.  At 20 or 30 amperes, you don't need many squares to get a
> voltage drop that puts you outside the supply voltage tolerance of the
> FPGA.
> 
> In my last "high power" FPGA design, we ended up with a plane on an
> inner (1/2 oz) layer in parallel with a fill on an outer (1oz) layer for
> the core supply.  The layout guy hated doing it, but it gave adequate
> results.
> 
> It might also be possible to use smaller vias in your BGA fanout to
> reduce the "swiss cheese" effect on your planes, but I haven't tried
> that in an actual design.
> 
> I've noticed that some PC motherboard manufacturers are advertising 2oz
> copper as a feature, so it's not just FPGA folk that are feeling the
> pain.


Another thing I've been doing is to boost the nominal voltage slightly.

(Contrived) example:  Requirement is 0.9V +/- 3% (i.e. +/- 27mV) at the 
die.

I budget +/- 1% (+/- 9mV) for the transient response.
I budget +/- 1% (+/- 9mV) for the initial tolerance.

This leaves +/- 1% (+/- 9mV) for the voltage drop.  However, the voltage 
drop is only in the -ve direction.  If I change the feedback resistors to 
move the nominal voltage up by +1% (+ 9mV), I can allow for a voltage 
drop of 0 to -2% (0 to -18mV).

Of course, one can use remote sense on the DC/DC converter to get 
feedback to eliminate the voltage drop.  My experience has been that the 
degradation of the transient response (due to having a more phase shift 
in the feedback) isn't worth it.  YMMV.

Regards,
Allan