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Stepped sine wave

Started by George Herold October 13, 2011
On Sun, 16 Oct 2011 10:42:48 -0700 (PDT), dagmargoodboat@yahoo.com wrote:

>On Oct 16, 8:55&#4294967295;am, "k...@att.bizzzzzzzzzzzz" ><k...@att.bizzzzzzzzzzzz> wrote: >> On Sun, 16 Oct 2011 06:25:38 -0700 (PDT), dagmargoodb...@yahoo.com wrote: >> >On Oct 15, 2:43&#4294967295;pm, patricia herold <pmdher...@gmail.com> wrote: >> >> On Oct 15, 9:31&#4294967295;am, dagmargoodb...@yahoo.com wrote: >> >> >> > On Oct 14, 11:25&#4294967295;pm, George Herold <gher...@teachspin.com> wrote: >> >> >> > > On Oct 14, 4:59&#4294967295;pm, dagmargoodb...@yahoo.com wrote: >> >> > > > On Oct 14, 2:41&#4294967295;pm, George Herold <gher...@teachspin.com> wrote: >> >> > > > > Hi James, &#4294967295;Yeah I was loading down the output of the 4017. &#4294967295;I measured >> >> > > > > an output impedance of ~180 ohms. &#4294967295;I put this number in and >> >> > > > > recalcualted values, &#4294967295;and then selected them to ~0.1% with a DMM. &#4294967295;The >> >> > > > > result.... I've got all the harmonics below the 9th down by ~70dB! &#4294967295;I >> >> > > > > don't know how repeatable the the output imedance is? &#4294967295;I put in a few >> >> > > > > different 4017's and say no difference, but these were all from the >> >> > > > > same order, so... >> >> >> > > > > Here's a plot from the SRS770.http://imageshack.us/photo/my-images/7/vco2.png/ >> >> >> > > > Beautiful, and well worth the resistors, right? &#4294967295;Compared to the cost >> >> > > > and complexity of extra hardware, it's a bargain. >> >> >> > > > For each half-wave, I'd analyze this as the sum of three impulses, one >> >> > > > inside the other, added together. &#4294967295;The phasing and amplitude of those >> >> > > > impulses is critical to canceling harmonics. >> >> >> > > > &#4294967295; &#4294967295; &#4294967295; &#4294967295; .---. >> >> > > > &#4294967295; &#4294967295; &#4294967295;.--' &#4294967295; '--. >> >> > > > &#4294967295; &#4294967295; &#4294967295;| &#4294967295; &#4294967295; &#4294967295; &#4294967295; | >> >> > > > &#4294967295; &#4294967295;.-' &#4294967295; &#4294967295; &#4294967295; &#4294967295; '-. >> >> > > > ___| &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; |___ >> >> > > > &#4294967295; &#4294967295;| &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; | >> >> > > > &#4294967295; -' &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; '- >> >> >> > > > My gut wants to say--but I'm too lazy to prove right now--that having >> >> > > > the same voltages repeated symmetrically on either side of each peak >> >> > > > is critical to harmonic rejection. >> >> >> > > Hmm you're suggesting that matching between equal value resistors it >> >> > > more important than hitting exact values? >> >> >> > I'm suggesting the possibility, but that's only a suspicion--I showed >> >> > one example below. &#4294967295;OTOH, I also just installed a virtual caterpillar >> >> > grommet backwards in another thread. :-) >> >> >> > As a practical matter, Phil's 'HC4017 with precision resistors seems >> >> > best. >> >> >> > > > Where the voltage is unequal on either side, you introduce a new >> >> > > > impulse with a magnitude equal to the difference in voltages. It's >> >> > > > easy to *introduce* a 2nd harmonic component that way. &#4294967295;For example, >> >> > > > taking the middle impulse: >> >> >> > > > &#4294967295; &#4294967295;.-----. >> >> > > > &#4294967295; &#4294967295;| &#4294967295; &#4294967295; '----. >> >> > > > &#4294967295; &#4294967295;| &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;| >> >> > > > &#4294967295; &#4294967295;| &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;| &#4294967295; &#4294967295; &#4294967295; &#4294967295; | >> >> > > > ___|__________|_________|__ >> >> > > > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; | &#4294967295; &#4294967295; &#4294967295; &#4294967295; | >> >> > > > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; | &#4294967295; &#4294967295; &#4294967295; &#4294967295; | >> >> > > > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; |____ &#4294967295; &#4294967295; | >> >> > > > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;'----' >> >> >> > > > My original thinking was to have an up/down counter, a single homemade >> >> > > > DAC, cycle up and down through the same (sine-weighted) values, then >> >> > > > invert (externally) for the negative swing. &#4294967295;That gets you 4x as many >> >> > > > steps and automatic symmetry, but it's not nearly as cute as Phil's >> >> > > > 4017. >> >> >> > FWIW, here's what I'd imagined, where v0-v7 encode a half-wave: >> >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;'HC4051 >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;.-----. >> >> > &#4294967295; v7-----|0 &#4294967295; &#4294967295;| >> >> > &#4294967295; v6-----|1 &#4294967295; &#4294967295;| >> >> > &#4294967295; v5-----|2 &#4294967295; &#4294967295;| >> >> > &#4294967295; v4-----|3 &#4294967295; Y|---- >> >> > &#4294967295; v3-----|4 &#4294967295; &#4294967295;| >> >> > &#4294967295; v2-----|5 &#4294967295; &#4294967295;| >> >> > &#4294967295; v1-----|6 &#4294967295; &#4294967295;| >> >> > &#4294967295; v0-----|7 &#4294967295; &#4294967295;| >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;| ABC | >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;'-----' >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;||| >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; .---. >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; |XOR|<-. >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; '---' &#4294967295;| >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;||| .-' >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;||| | >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;.------. >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;| ABC D| >> >> > 16x clk -|> &#4294967295; &#4294967295; | 4-bit Counter >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;| &#4294967295; &#4294967295; &#4294967295;| >> >> > &#4294967295; &#4294967295; &#4294967295; &#4294967295; &#4294967295;'------' >> >> >> > This logic walks up and down through 8 voltages, which, since they are >> >> > reused from the same source, are duplicated exactly on each side of >> >> > the peak. &#4294967295;That does not guarantee symmetry about zero, though. >> >> >> > Another possibility is to make v0-v7 encode a quarter-wave, then >> >> > multiply by +/-1 afterwards in analog, ensuring full symmetry. >> >> >> Ha, &#4294967295;following your bipolar idea, I was wondering if I could program >> >> the 4017 for 1/2 a sine wave and use the carry output to flip a +/-1 >> >> opamp down stream. &#4294967295;I guess that means another chip. >> >> >That's the "another possibility" I meant, above. &#4294967295;The DAC only has to >> >cover 1/4 of a sinewave, and you get the remaining wave portions by >> >manipulating that. >> >> >To wit, the external logic walks the DAC up, then down, then kicks on >> >the analog invert (x -1) function and cycles up, then down again. >> >Then, back to the beginning. >> >> >That, here, would take about 5 chips & get you 32 samples per >> >sinewave. >> >> >So, we've got several versions: 10 steps with one chip, 16 steps with >> >three chips, or 32 steps for five chips. Or, as always, you could use >> >a PIC :-) >> >> Or an 8-bit counter (e.g. '579), ROM, and DAC. &#4294967295;256 steps, three chips. ;-) >> >> The synchronous counter is the limitation, here. > >Hey, how about two 'HC4017's, driven out-of-phase. Clock one rising, >one falling. That's 20 steps, two chips, dirt-simple.
An FPGA. Hundreds of steps, one chip. Pick your poison. ;-)
On Fri, 14 Oct 2011 20:58:26 -0700 (PDT), George Herold
<gherold@teachspin.com> wrote:

>On Oct 14, 4:59=A0pm, dagmargoodb...@yahoo.com wrote: >> On Oct 14, 2:41=A0pm, George Herold <gher...@teachspin.com> wrote: >> >> >> >> >> >> > On Oct 13, 10:13=A0pm, dagmargoodb...@yahoo.com wrote: >> > > On Oct 13, 6:30=A0pm, George Herold <gher...@teachspin.com> wrote: >> > > > On Oct 13, 5:13=A0pm, Phil Hobbs wrote: >> > > > > On 10/13/2011 12:39 PM, George Herold wrote: >> >> > > > > > This is a continuation of the 50kHz VCO thread I started =
last week. =A0I
>> > > > > > tried the stepped sine wave idea as suggested by James A, =
and Phil
>> > > > > > H. >> > > > > > The circuit clocks a MC14017 at 10x(F) to make a stepped =
sine wave at
>> > > > > > frequency (F). =A0The ten outputs from the 4017 are sent =
through
>> > > > > > appropriate resistors and into the summing junction of an =
opamp.
>> > > > > > Here=92s a =91scope shot of the stepped output overlaid with=
a sine
>> > > > > > wave. >> >> > > > > >http://imageshack.us/photo/my-images/560/tek0024.png/ >> >> > > > > > The resistor values were chosen to intersect the sine wave =
at each new
>> > > > > > phase. =A0(R(n) =3D 1/sin^2(n*18degrees)) >> >> > > > > > Approximate values, R0=3Dopen, R1=3DR9=3D105k, =
R2=3DR8=3D28.9k, R3=3DR7=3D15.3k,
>> > > > > > R4=3DR6=3D11k, R5=3D10k. =A0all 1% resistors. >> >> > > > > > Here=92s the spectrum as recorded by an SRS770 spectrum =
analyzer.
>> >> > > > > >http://imageshack.us/photo/my-images/839/stepsin.png/ >> >> > > > > > The 2nd harmonic is only down by 50dB. =A0I don=92t =
understand why it=92s so
>> > > > > > big. =A0Is there some way to do better than this? =A0The 9th=
and 11th
>> > > > > > harmonics are big and then the 19th and 21st. >> >> > > > > 50 dB is only 0.3%, which isn't too bad. =A0 That might easily=
be due to
>> > > > > the output impedances of the 4017 drivers, or to the resistor >> > > > > tolerances. =A0Does it get better or worse when you change =
VDD? =A0If so,
>> > > > > it's probably the output impedance. >> >> > > > Yeah, I was thinking about the output impedance. (I didn't =
looked at
>> > > > the outputs from the 4017). =A0When I decreased the supply =
voltage the
>> > > > 2nd harmonic was roughly constant while everything else went =
down. =A0I
>> > > > added a tweaker on the lowest resistance output and got =
everything
>> > > > below the 9th close to 60 dB down. =A0 Which is almost beer =
time, except
>> > > > it's only at 1kHz. >> >> > > I posted (and Google lost) a long post, the gist of which was: >> >> > > (view in fixed font) >> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0desired, >> > > G.H. =A0 =A0desired, =A0 scaled to =A0George's >> > > values theoretical 'scope =A0 =A0 actual >> > > (volts) (volts) =A0 =A0(div) =A0 =A0 =A0(div) >> > > 0.000 =A0 0.000 =A0 =A0 =A0 0.2 =A0 =A0 =A0 =A00.2 >> > > 0.093 =A0 0.079 =A0 =A0 =A0 0.93 =A0 =A0 =A0 1.0 >> > > 0.323 =A0 0.287 =A0 =A0 =A0 2.82 =A0 =A0 =A0 2.8 >> > > 0.577 =A0 0.545 =A0 =A0 =A0 5.17 =A0 =A0 =A0 5.2 >> > > 0.768 =A0 0.753 =A0 =A0 =A0 7.07 =A0 =A0 =A0 7.05 >> > > 0.832 =A0 0.832 =A0 =A0 =A0 7.8 =A0 =A0 =A0 =A07.8 >> >> > > (1rst column is the expected outputs based on your resistor =
values)
>> >> > > So, the outputs are loaded, but you've tweaked the resistors from =
the
>> > > reported values to compensate. =A0That's device-dependent. =
=A0Might wanna
>> > > up the resistances or switch to 'HC. >> >> > > The actual waveform looks pretty good. =A0Some of the steps look a >> > > little mis-matched, e.g. 2-8 and 3-7 >> >> > Hi James, =A0Yeah I was loading down the output of the 4017. =A0I =
measured
>> > an output impedance of ~180 ohms. =A0I put this number in and >> > recalcualted values, =A0and then selected them to ~0.1% with a DMM. =
=A0The
>> > result.... I've got all the harmonics below the 9th down by ~70dB! =
=A0I
>> > don't know how repeatable the the output imedance is? =A0I put in a =
few
>> > different 4017's and say no difference, but these were all from the >> > same order, so... >> >> > Here's a plot from the =
SRS770.http://imageshack.us/photo/my-images/7/vco2.png/
>> >> Beautiful, and well worth the resistors, right? =A0Compared to the =
cost
>> and complexity of extra hardware, it's a bargain. > >Yeah, I was hoping for 60dB. When I crank up the frequency >capacitance is going to start to byte me, but now I've got dB's to >spare. >> >> For each half-wave, I'd analyze this as the sum of three impulses, one >> inside the other, added together. =A0The phasing and amplitude of =
those
>> impulses is critical to canceling harmonics. >> >> =A0 =A0 =A0 =A0 .---. >> =A0 =A0 =A0.--' =A0 '--. >> =A0 =A0 =A0| =A0 =A0 =A0 =A0 | >> =A0 =A0.-' =A0 =A0 =A0 =A0 '-. >> ___| =A0 =A0 =A0 =A0 =A0 =A0 |___ >> =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0 | >> =A0 -' =A0 =A0 =A0 =A0 =A0 =A0 '- >> >> My gut wants to say--but I'm too lazy to prove right now--that having >> the same voltages repeated symmetrically on either side of each peak >> is critical to harmonic rejection. > >Hmm you're suggesting that matching between equal value resistors is >more important than hitting some exact number. I think, that might be >true.... or does matching effect the odd harmonics and absolute value >the even?
The way i see it matching will impact even more than odd and absolute value will impact odd more than even. But each will impact both. It is = a small enough dft that it is worth cranking it up in a spreadsheet.
> >George H. >> >> Where the voltage is unequal on either side, you introduce a new >> impulse with a magnitude equal to the difference in voltages. It's >> easy to *introduce* a 2nd harmonic component that way. =A0For example, >> taking the middle impulse: >> >> =A0 =A0.-----. >> =A0 =A0| =A0 =A0 '----. >> =A0 =A0| =A0 =A0 =A0 =A0 =A0| >> =A0 =A0| =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 | >> ___|__________|_________|__ >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 =A0 | >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 =A0 | >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 |____ =A0 =A0 | >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0'----' >> >> My original thinking was to have an up/down counter, a single homemade >> DAC, cycle up and down through the same (sine-weighted) values, then >> invert (externally) for the negative swing. =A0That gets you 4x as =
many
>> steps and automatic symmetry, but it's not nearly as cute as Phil's >> 4017. >> >> > Now I've got to get it off the white proto-board and crank up the >> > frequency. >> >> > George H. >> >> -- >> Cheers, >> James Arthur- Hide quoted text - >> >> - Show quoted text -
On Oct 16, 6:09=A0pm, "k...@att.bizzzzzzzzzzzz" wrote:
> On Sun, 16 Oct 2011 10:42:48 -0700 (PDT), dagmargoodb...@yahoo.com wrote: > >On Oct 16, 8:55=A0am, "k...@att.bizzzzzzzzzzzz" wrote: > >> On Sun, 16 Oct 2011 06:25:38 -0700 (PDT), dagmargoodb...@yahoo.com wro=
te:
> >> >So, we've got several versions: 10 steps with one chip, 16 steps with > >> >three chips, or 32 steps for five chips. Or, as always, you could use > >> >a PIC :-) > > >> Or an 8-bit counter (e.g. '579), ROM, and DAC. =A0256 steps, three chi=
ps. ;-)
> > >> The synchronous counter is the limitation, here. > > >Hey, how about two 'HC4017's, driven out-of-phase. =A0Clock one rising, > >one falling. =A0That's 20 steps, two chips, dirt-simple. > > An FPGA. =A0Hundreds of steps, one chip. =A0Pick your poison. =A0;-)
Come to think of it, I suspect staggered 'HC4017's doesn't work. Each output of "B" would straddle (be active during) two output states of "A", and the simultaneous equations fail. You'd need to buffer 'em so you could enable just one 'HC4017 at a time, which is messy & takes more chips. So, it's either one 'HC4017, or a PIC. (Or a 555, details left as an exercise for the student.) -- Cheers, James Arthur
On 10/16/2011 11:43 PM, dagmargoodboat@yahoo.com wrote:
> On Oct 16, 6:09 pm, "k...@att.bizzzzzzzzzzzz" wrote: >> On Sun, 16 Oct 2011 10:42:48 -0700 (PDT), dagmargoodb...@yahoo.com wrote: >>> On Oct 16, 8:55 am, "k...@att.bizzzzzzzzzzzz" wrote: >>>> On Sun, 16 Oct 2011 06:25:38 -0700 (PDT), dagmargoodb...@yahoo.com wrote: > >>>>> So, we've got several versions: 10 steps with one chip, 16 steps with >>>>> three chips, or 32 steps for five chips. Or, as always, you could use >>>>> a PIC :-) >> >>>> Or an 8-bit counter (e.g. '579), ROM, and DAC. 256 steps, three chips. ;-) >> >>>> The synchronous counter is the limitation, here. >> >>> Hey, how about two 'HC4017's, driven out-of-phase. Clock one rising, >>> one falling. That's 20 steps, two chips, dirt-simple. >> >> An FPGA. Hundreds of steps, one chip. Pick your poison. ;-) > > Come to think of it, I suspect staggered 'HC4017's doesn't work. Each > output of "B" would straddle (be active during) two output states of > "A", and the simultaneous equations fail. You'd need to buffer 'em so > you could enable just one 'HC4017 at a time, which is messy& takes > more chips. > > So, it's either one 'HC4017, or a PIC. (Or a 555, details left as an > exercise for the student.) > > -- > Cheers, > James Arthur
We really need a 4017 with tri-state outputs. ;) You could take advantage of the particular phase choice that George used, i.e. one phase is disconnected, and use a bunch of SIPO shift registers. Do a synchronous reset of all of them when the last stage goes high, and use an R-S flipflop to inject a 1 into the first stage when that happens, reset from the output of the first stage. It would also need a missing pulse detector or something like that to make sure that it doesn't just sit there producing all zeros forever. You could get 8N+1 phases for about N+2 packages and 8N resistors. Alternatively, adapting your folding trick, it might be possible to use a bunch of universal shift registers and just shuttle the 1-state back and forth from end to end, by changing the shift direction when it hits the end. That way you'd get 16N or maybe 16N-1 codes for N + 3ish packages and 8N resistors. Fun. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
On Oct 16, 4:19=A0pm, whit3rd <whit...@gmail.com> wrote:
> On Thursday, October 13, 2011 7:14:04 PM UTC-7, George Herold wrote: > > [about making a sine with steps set by resistor values] > > > resistors have to take care of the lower harmonics. =A0(which is why th=
e
> > 2nd is so disturbing) 9 or 10, 0.1% resistors are not 'out of the > > question' only ~$2 + the cost of placing them. =A0Though 1% would be > > nicer. > > Manufacturers, take note! =A0If one can build/sell a RAMDAC ( old video p=
art,
> intended to encode colors), how about a sine-table ROMDAC? > Can you beat the price of ten $2 resistors, with 8-bit output converter?
Hi Whit3rd, Are you making fun of me? You can get 0.1% resostors from Sussumu for ~$0.20 each. George H.
On Oct 16, 11:43=A0pm, dagmargoodb...@yahoo.com wrote:
> On Oct 16, 6:09=A0pm, "k...@att.bizzzzzzzzzzzz" wrote: > > > On Sun, 16 Oct 2011 10:42:48 -0700 (PDT), dagmargoodb...@yahoo.com wrot=
e:
> > >On Oct 16, 8:55=A0am, "k...@att.bizzzzzzzzzzzz" wrote: > > >> On Sun, 16 Oct 2011 06:25:38 -0700 (PDT), dagmargoodb...@yahoo.com w=
rote:
> > >> >So, we've got several versions: 10 steps with one chip, 16 steps wi=
th
> > >> >three chips, or 32 steps for five chips. Or, as always, you could u=
se
> > >> >a PIC :-) > > > >> Or an 8-bit counter (e.g. '579), ROM, and DAC. =A0256 steps, three c=
hips. ;-)
> > > >> The synchronous counter is the limitation, here. > > > >Hey, how about two 'HC4017's, driven out-of-phase. =A0Clock one rising=
,
> > >one falling. =A0That's 20 steps, two chips, dirt-simple. > > > An FPGA. =A0Hundreds of steps, one chip. =A0Pick your poison. =A0;-) > > Come to think of it, I suspect staggered 'HC4017's doesn't work. =A0Each > output of "B" would straddle (be active during) two output states of > "A", and the simultaneous equations fail. =A0You'd need to buffer 'em so > you could enable just one 'HC4017 at a time, which is messy & takes > more chips. > > So, it's either one 'HC4017, or a PIC. =A0(Or a 555, details left as an > exercise for the student.) > > -- > Cheers, > James Arthur
Dat's OK James, I'm still pondering your idea of multiple switching... using each resistor four times during a cycle. (I'm a bit slow so it takes me a while to digest what you are suggesting.) I must admit that the symmetry is appealing. George H.
On Oct 17, 9:50=A0am, George Herold <gher...@teachspin.com> wrote:
> On Oct 16, 4:19=A0pm, whit3rd <whit...@gmail.com> wrote: > > > On Thursday, October 13, 2011 7:14:04 PM UTC-7, George Herold wrote: > > > [about making a sine with steps set by resistor values] > > > > resistors have to take care of the lower harmonics. =A0(which is why =
the
> > > 2nd is so disturbing) 9 or 10, 0.1% resistors are not 'out of the > > > question' only ~$2 + the cost of placing them. =A0Though 1% would be > > > nicer. > > > Manufacturers, take note! =A0If one can build/sell a RAMDAC ( old video=
part,
> > intended to encode colors), how about a sine-table ROMDAC? > > Can you beat the price of ten $2 resistors, with 8-bit output converter=
?
> > Hi Whit3rd, Are you making fun of me? > > You can get 0.1% resostors from Sussumu for ~$0.20 each.
resistors Susumu
> George H.
Geesh, be nice if I could spell say every other word correctly.
On Mon, 17 Oct 2011 00:10:09 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 10/16/2011 11:43 PM, dagmargoodboat@yahoo.com wrote: >> On Oct 16, 6:09 pm, "k...@att.bizzzzzzzzzzzz" wrote: >>> On Sun, 16 Oct 2011 10:42:48 -0700 (PDT), dagmargoodb...@yahoo.com =
wrote:
>>>> On Oct 16, 8:55 am, "k...@att.bizzzzzzzzzzzz" wrote: >>>>> On Sun, 16 Oct 2011 06:25:38 -0700 (PDT), dagmargoodb...@yahoo.com =
wrote:
>> >>>>>> So, we've got several versions: 10 steps with one chip, 16 steps =
with
>>>>>> three chips, or 32 steps for five chips. Or, as always, you could =
use
>>>>>> a PIC :-) >>> >>>>> Or an 8-bit counter (e.g. '579), ROM, and DAC. 256 steps, three =
chips. ;-)
>>> >>>>> The synchronous counter is the limitation, here. >>> >>>> Hey, how about two 'HC4017's, driven out-of-phase. Clock one =
rising,
>>>> one falling. That's 20 steps, two chips, dirt-simple. >>> >>> An FPGA. Hundreds of steps, one chip. Pick your poison. ;-) >> >> Come to think of it, I suspect staggered 'HC4017's doesn't work. Each >> output of "B" would straddle (be active during) two output states of >> "A", and the simultaneous equations fail. You'd need to buffer 'em so >> you could enable just one 'HC4017 at a time, which is messy& takes >> more chips. >> >> So, it's either one 'HC4017, or a PIC. (Or a 555, details left as an >> exercise for the student.) >> >> -- >> Cheers, >> James Arthur > >We really need a 4017 with tri-state outputs. ;) > >You could take advantage of the particular phase choice that George=20 >used, i.e. one phase is disconnected, and use a bunch of SIPO shift=20 >registers. Do a synchronous reset of all of them when the last stage=20 >goes high, and use an R-S flipflop to inject a 1 into the first stage=20 >when that happens, reset from the output of the first stage. > >It would also need a missing pulse detector or something like that to=20 >make sure that it doesn't just sit there producing all zeros forever.=20 >You could get 8N+1 phases for about N+2 packages and 8N resistors. > >Alternatively, adapting your folding trick, it might be possible to use=20 >a bunch of universal shift registers and just shuttle the 1-state back=20 >and forth from end to end, by changing the shift direction when it hits=20 >the end. That way you'd get 16N or maybe 16N-1 codes for N + 3ish=20 >packages and 8N resistors. > >Fun. > >Cheers > >Phil Hobbs
Got me to thimkin'. Two 74hc374 in a Johnson twisted ring counter with 16 resistors will get you 32 steps. Can get 16 steps with a single '374 and 8 resistors. Have to pay attention to initialization though. Calcs for the resistors will be a little different though, may be a problem if the High and Low drive strengths are different. Don't see one in 4000 style cmos. ?-)
On Oct 17, 10:03=A0am, George Herold <gher...@teachspin.com> wrote:
> On Oct 17, 9:50=A0am, George Herold <gher...@teachspin.com> wrote: > > > On Oct 16, 4:19=A0pm, whit3rd <whit...@gmail.com> wrote: > > > > On Thursday, October 13, 2011 7:14:04 PM UTC-7, George Herold wrote: > > > > [about making a sine with steps set by resistor values] > > > > > resistors have to take care of the lower harmonics. =A0(which is wh=
y the
> > > > 2nd is so disturbing) 9 or 10, 0.1% resistors are not 'out of the > > > > question' only ~$2 + the cost of placing them. =A0Though 1% would b=
e
> > > > nicer. > > > > Manufacturers, take note! =A0If one can build/sell a RAMDAC ( old vid=
eo part,
> > > intended to encode colors), how about a sine-table ROMDAC? > > > Can you beat the price of ten $2 resistors, with 8-bit output convert=
er?
> > > Hi Whit3rd, Are you making fun of me? > > > You can get 0.1% resostors from Sussumu for ~$0.20 each. > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0resistors =A0 =A0 =A0Susumu > > > George H. > > Geesh, be nice if I could spell say every other word correctly.
The Apple start-up sound is called Sosumi- a legacy of the legal troubles between Apple and the Beatles. It was thought by their legal beagles to be a better choice than "Let it beep". --sp
On 10/17/2011 11:08 PM, josephkk wrote:
> On Mon, 17 Oct 2011 00:10:09 -0400, Phil Hobbs > <pcdhSpamMeSenseless@electrooptical.net> wrote: > >> On 10/16/2011 11:43 PM, dagmargoodboat@yahoo.com wrote: >>> On Oct 16, 6:09 pm, "k...@att.bizzzzzzzzzzzz" wrote: >>>> On Sun, 16 Oct 2011 10:42:48 -0700 (PDT), dagmargoodb...@yahoo.com wrote: >>>>> On Oct 16, 8:55 am, "k...@att.bizzzzzzzzzzzz" wrote: >>>>>> On Sun, 16 Oct 2011 06:25:38 -0700 (PDT), dagmargoodb...@yahoo.com wrote: >>> >>>>>>> So, we've got several versions: 10 steps with one chip, 16 steps with >>>>>>> three chips, or 32 steps for five chips. Or, as always, you could use >>>>>>> a PIC :-) >>>> >>>>>> Or an 8-bit counter (e.g. '579), ROM, and DAC. 256 steps, three chips. ;-) >>>> >>>>>> The synchronous counter is the limitation, here. >>>> >>>>> Hey, how about two 'HC4017's, driven out-of-phase. Clock one rising, >>>>> one falling. That's 20 steps, two chips, dirt-simple. >>>> >>>> An FPGA. Hundreds of steps, one chip. Pick your poison. ;-) >>> >>> Come to think of it, I suspect staggered 'HC4017's doesn't work. Each >>> output of "B" would straddle (be active during) two output states of >>> "A", and the simultaneous equations fail. You'd need to buffer 'em so >>> you could enable just one 'HC4017 at a time, which is messy& takes >>> more chips. >>> >>> So, it's either one 'HC4017, or a PIC. (Or a 555, details left as an >>> exercise for the student.) >>> >>> -- >>> Cheers, >>> James Arthur >> >> We really need a 4017 with tri-state outputs. ;) >> >> You could take advantage of the particular phase choice that George >> used, i.e. one phase is disconnected, and use a bunch of SIPO shift >> registers. Do a synchronous reset of all of them when the last stage >> goes high, and use an R-S flipflop to inject a 1 into the first stage >> when that happens, reset from the output of the first stage. >> >> It would also need a missing pulse detector or something like that to >> make sure that it doesn't just sit there producing all zeros forever. >> You could get 8N+1 phases for about N+2 packages and 8N resistors. >> >> Alternatively, adapting your folding trick, it might be possible to use >> a bunch of universal shift registers and just shuttle the 1-state back >> and forth from end to end, by changing the shift direction when it hits >> the end. That way you'd get 16N or maybe 16N-1 codes for N + 3ish >> packages and 8N resistors. >> >> Fun. >> >> Cheers >> >> Phil Hobbs > > Got me to thimkin'. Two 74hc374 in a Johnson twisted ring counter with > 16 resistors will get you 32 steps. Can get 16 steps with a single '374 > and 8 resistors. Have to pay attention to initialization though. Calcs > for the resistors will be a little different though, may be a problem if > the High and Low drive strengths are different. Don't see one in 4000 > style cmos. > > ?-)
The problem is that there's no linear mapping from that to a sine wave--for 2**N states you need 2**N outputs in order to be able to solve the linear system. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net