On a sunny day (Wed, 29 Nov 2023 03:46:08 -0800) it happened John Larkin <jl@997PotHill.com> wrote in <sd8emit90cjntoeidgojoe2q1ggnm41anu@4ax.com>:>On Wed, 29 Nov 2023 05:49:47 GMT, Jan Panteltje <alien@comet.invalid> >wrote: > >>On a sunny day (Tue, 28 Nov 2023 09:09:44 -0800) it happened John Larkin >><jl@997PotHill.com> wrote in <bd7cmi1iaui01tmdti32c7bi71u41rtjmk@4ax.com>: >> >>>On Tue, 28 Nov 2023 16:08:32 GMT, Jan Panteltje <alien@comet.invalid> >>>wrote: >>> >>>>On a sunny day (Tue, 28 Nov 2023 14:13:25 +0100) it happened Miguel Gimenez >>>><me@privacy.net> wrote in <uk4p1p$9fur$1@dont-email.me>: >>>> >>>>>Hello. >>>>> >>>>>I have built a phase shifted converter based in the UCC28951 from TI, >>>>>but I have problems with stability. The load has built-in capacitors and >>>>>the converter oscillates wildly. I have changed the Type-II compensator >>>>>to a Type-III one, but oscillations do not stop. Calculation of the >>>>>Type-III compensator is based in application note SLVA662 from TI. >>>>> >>>>>The input voltage is 48 V, output is 311 V, nominal output power is 600 >>>>>W and the output capacitance is about 2000 uF. Fsw = 100 kHz. >>>>> >>>>>Is this kind of converter valid at all for this output capacitance? >>>> >>>>I maye be totally wrong here, but the guy who wrote that paper is maybe not >>>>aware you may need a differentiator in the feedback with high capacitance load >>>>All he does is basically low pass, >>>>? >>>> >>>>This is more clear perhaps: >>>> https://www.ni.com/en/shop/labview/pid-theory-explained.html >>>> scroll down to 'Iuning' >>>> >>>>I would experiment to get it right... >>> >>>Or Spice it. >>> >>>Usually just a pole-zero is all you need in the control loop. Output >>>cap ESR can help there. >>> >>>My latest trick is to take the AC feedback from the raw switch node >>>and DC from the final, filtered output. This is for a power supply >>>that might drive weird, unknown customer loads where we have no >>>control of the loop dynamics if we take our feedback from the output. >> >>Nice idea! > >Here's the idea. FB is a combination of a sorta fast (lowpass filtered >a bit) path from the switch node, blended with slow feedback from the >final output. Seems to work. > >https://www.dropbox.com/scl/fi/pgw70e2ls16i66pj0hl5b/P943_Loop_1.jpg?rlkey=hc1ske5u41ylhfnazuj4t27k5&raw=1 > >The transfer function of the switcher path into the FB network is >basically 48, which is easy to close a loop aound. > >In real life, the control loop will be in an FPGA. I'd keep the R4 etc >parts but FB will drive an ADC that makes the PWM signals into the fet >driver. I like to Spice a system mostly analog, and hand it over to >the FPGA kids to implement.Nice, way to go! Yes, much control is in software these days. The temperature control loop for the tritium decay experiment I did for example in PIC 18F14K22 asm: https://panteltje.nl/panteltje/tri_pic/ I expected that to be a big problem, but then after an hour or so coding it worked OK for many years to within a few ADC steps of the sensor.... Power on was fast and no overshoot either.
Stability of phase shifted converters
Started by ●November 28, 2023
Reply by ●November 29, 20232023-11-29
Reply by ●November 29, 20232023-11-29
On Wed, 29 Nov 2023 17:50:56 GMT, Jan Panteltje <alien@comet.invalid> wrote:>On a sunny day (Wed, 29 Nov 2023 03:46:08 -0800) it happened John Larkin ><jl@997PotHill.com> wrote in <sd8emit90cjntoeidgojoe2q1ggnm41anu@4ax.com>: > >>On Wed, 29 Nov 2023 05:49:47 GMT, Jan Panteltje <alien@comet.invalid> >>wrote: >> >>>On a sunny day (Tue, 28 Nov 2023 09:09:44 -0800) it happened John Larkin >>><jl@997PotHill.com> wrote in <bd7cmi1iaui01tmdti32c7bi71u41rtjmk@4ax.com>: >>> >>>>On Tue, 28 Nov 2023 16:08:32 GMT, Jan Panteltje <alien@comet.invalid> >>>>wrote: >>>> >>>>>On a sunny day (Tue, 28 Nov 2023 14:13:25 +0100) it happened Miguel Gimenez >>>>><me@privacy.net> wrote in <uk4p1p$9fur$1@dont-email.me>: >>>>> >>>>>>Hello. >>>>>> >>>>>>I have built a phase shifted converter based in the UCC28951 from TI, >>>>>>but I have problems with stability. The load has built-in capacitors and >>>>>>the converter oscillates wildly. I have changed the Type-II compensator >>>>>>to a Type-III one, but oscillations do not stop. Calculation of the >>>>>>Type-III compensator is based in application note SLVA662 from TI. >>>>>> >>>>>>The input voltage is 48 V, output is 311 V, nominal output power is 600 >>>>>>W and the output capacitance is about 2000 uF. Fsw = 100 kHz. >>>>>> >>>>>>Is this kind of converter valid at all for this output capacitance? >>>>> >>>>>I maye be totally wrong here, but the guy who wrote that paper is maybe not >>>>>aware you may need a differentiator in the feedback with high capacitance load >>>>>All he does is basically low pass, >>>>>? >>>>> >>>>>This is more clear perhaps: >>>>> https://www.ni.com/en/shop/labview/pid-theory-explained.html >>>>> scroll down to 'Iuning' >>>>> >>>>>I would experiment to get it right... >>>> >>>>Or Spice it. >>>> >>>>Usually just a pole-zero is all you need in the control loop. Output >>>>cap ESR can help there. >>>> >>>>My latest trick is to take the AC feedback from the raw switch node >>>>and DC from the final, filtered output. This is for a power supply >>>>that might drive weird, unknown customer loads where we have no >>>>control of the loop dynamics if we take our feedback from the output. >>> >>>Nice idea! >> >>Here's the idea. FB is a combination of a sorta fast (lowpass filtered >>a bit) path from the switch node, blended with slow feedback from the >>final output. Seems to work. >> >>https://www.dropbox.com/scl/fi/pgw70e2ls16i66pj0hl5b/P943_Loop_1.jpg?rlkey=hc1ske5u41ylhfnazuj4t27k5&raw=1 >> >>The transfer function of the switcher path into the FB network is >>basically 48, which is easy to close a loop aound. >> >>In real life, the control loop will be in an FPGA. I'd keep the R4 etc >>parts but FB will drive an ADC that makes the PWM signals into the fet >>driver. I like to Spice a system mostly analog, and hand it over to >>the FPGA kids to implement. > >Nice, way to go! >Yes, much control is in software these days. >The temperature control loop for the tritium decay experiment I did for example in PIC 18F14K22 asm: > https://panteltje.nl/panteltje/tri_pic/ >I expected that to be a big problem, but then after an hour or so coding it worked OK for many years to within a few ADC steps >of the sensor.... Power on was fast and no overshoot either.Real-life loops dither themselves, so you get better control than is obvious from what you see in the adc/dac/code. Sometimes we add noise to make that happen... an asynchronous triangle works nicely. The people who do pulse-height spectroscopy add noise to make their ADCs look better, and the clever ones subtract it back out.
Reply by ●November 30, 20232023-11-30
On a sunny day (Wed, 29 Nov 2023 10:07:23 -0800) it happened John Larkin <jl@997PotHill.com> wrote in <s6vemi5elfjpanc0n2rmc6e0kr2nkupeh6@4ax.com>:>On Wed, 29 Nov 2023 17:50:56 GMT, Jan Panteltje <alien@comet.invalid> >wrote: > >>On a sunny day (Wed, 29 Nov 2023 03:46:08 -0800) it happened John Larkin >><jl@997PotHill.com> wrote in <sd8emit90cjntoeidgojoe2q1ggnm41anu@4ax.com>: >> >>>On Wed, 29 Nov 2023 05:49:47 GMT, Jan Panteltje <alien@comet.invalid> >>>wrote: >>> >>>>On a sunny day (Tue, 28 Nov 2023 09:09:44 -0800) it happened John Larkin >>>><jl@997PotHill.com> wrote in <bd7cmi1iaui01tmdti32c7bi71u41rtjmk@4ax.com>: >>>> >>>>>On Tue, 28 Nov 2023 16:08:32 GMT, Jan Panteltje <alien@comet.invalid> >>>>>wrote: >>>>> >>>>>>On a sunny day (Tue, 28 Nov 2023 14:13:25 +0100) it happened Miguel Gimenez >>>>>><me@privacy.net> wrote in <uk4p1p$9fur$1@dont-email.me>: >>>>>> >>>>>>>Hello. >>>>>>> >>>>>>>I have built a phase shifted converter based in the UCC28951 from TI, >>>>>>>but I have problems with stability. The load has built-in capacitors and >>>>>>>the converter oscillates wildly. I have changed the Type-II compensator >>>>>>>to a Type-III one, but oscillations do not stop. Calculation of the >>>>>>>Type-III compensator is based in application note SLVA662 from TI. >>>>>>> >>>>>>>The input voltage is 48 V, output is 311 V, nominal output power is 600 >>>>>>>W and the output capacitance is about 2000 uF. Fsw = 100 kHz. >>>>>>> >>>>>>>Is this kind of converter valid at all for this output capacitance? >>>>>> >>>>>>I maye be totally wrong here, but the guy who wrote that paper is maybe not >>>>>>aware you may need a differentiator in the feedback with high capacitance load >>>>>>All he does is basically low pass, >>>>>>? >>>>>> >>>>>>This is more clear perhaps: >>>>>> https://www.ni.com/en/shop/labview/pid-theory-explained.html >>>>>> scroll down to 'Iuning' >>>>>> >>>>>>I would experiment to get it right... >>>>> >>>>>Or Spice it. >>>>> >>>>>Usually just a pole-zero is all you need in the control loop. Output >>>>>cap ESR can help there. >>>>> >>>>>My latest trick is to take the AC feedback from the raw switch node >>>>>and DC from the final, filtered output. This is for a power supply >>>>>that might drive weird, unknown customer loads where we have no >>>>>control of the loop dynamics if we take our feedback from the output. >>>> >>>>Nice idea! >>> >>>Here's the idea. FB is a combination of a sorta fast (lowpass filtered >>>a bit) path from the switch node, blended with slow feedback from the >>>final output. Seems to work. >>> >>>https://www.dropbox.com/scl/fi/pgw70e2ls16i66pj0hl5b/P943_Loop_1.jpg?rlkey=hc1ske5u41ylhfnazuj4t27k5&raw=1 >>> >>>The transfer function of the switcher path into the FB network is >>>basically 48, which is easy to close a loop aound. >>> >>>In real life, the control loop will be in an FPGA. I'd keep the R4 etc >>>parts but FB will drive an ADC that makes the PWM signals into the fet >>>driver. I like to Spice a system mostly analog, and hand it over to >>>the FPGA kids to implement. >> >>Nice, way to go! >>Yes, much control is in software these days. >>The temperature control loop for the tritium decay experiment I did for example in PIC 18F14K22 asm: >> https://panteltje.nl/panteltje/tri_pic/ >>I expected that to be a big problem, but then after an hour or so coding it worked OK for many years to within a few ADC steps >>of the sensor.... Power on was fast and no overshoot either. > >Real-life loops dither themselves, so you get better control than is >obvious from what you see in the adc/dac/code. Sometimes we add noise >to make that happen... an asynchronous triangle works nicely. The >people who do pulse-height spectroscopy add noise to make their ADCs >look better, and the clever ones subtract it back out.Control loops are interesting, in the analog TV days getting nanosecond precision from a rotating video head... Lots of tricks exist, never tried that noise thing though.> >
