Extraction of parasitic from trace

On Sunday, 8 January 2023 at 16:16:13 UTC, John Larkin wrote:
> On Sun, 08 Jan 2023 12:39:16 +0200, upsid...@downunder.com wrote: 
> 
> >On Sat, 7 Jan 2023 15:37:20 +0100, Klaus Vestergaard Kragelund 
> ><klau...@hotmail.com> wrote: 
> > 
> >>On 07-01-2023 13:56, John Larkin wrote: 
> >>> On Sat, 07 Jan 2023 02:29:48 +0100, Klaus Kragelund 
> >>> <klau...@hotmail.com> wrote: 
> >>> 
> >>>> Hi 
> >>>> 
> >>>> I am working on a high frequency design in which we in principle is using a very high frequency switch mode converter 
> >>>> 
> >>>> I need low loss, so need to minimize capacitive parasitics, and also minimize inductances. They conflict of course, smaller trace has lower capacitance but higher inductance. 
> >>>> 
> >>>> We use Altium for layout and have used ADS for parasitic extraction. But we cannot afford the license. 
> >>>> 
> >>>> Is there a low cost alternative that is ok in terms of amount of time to get it done? 
> >>>> 
> >>>> I was thinking maybe somebody has made a tool, maybe even excel, that could import the trace and image plane /traces to do a finite element analysis /model. 
> >>>> 
> >>>> Any hints? 
> >>> 
> >>> The Saturn software does the basics for standard trace geometries. 
> >>> 
> >>> Sonnet Lite does 2.5-D em analysis for free. 
> >>> 
> >>Thanks, that looks quite nice. 
> >> 
> >> 
> >>> A switcher should be small enough that the speed of light is 
> >>> inconsequential. How high a frequncy did you have in mind? 
> >>> 
> >> 
> >>It's not a standard switcher :-) 
> >> 
> >>Operating at 100MHz, and with 1ns switch node rise time. So even 
> >>laminate loss is important. 
> > 
> >Sounds like VHF transmitter design :-) 
> > 
> >At those frequencies you also need to consider the skin dept, i.e. the 
> >current flows only at the surface of the traces. Thus the resistive 
> >losses of the trace is larger than on DC and you may have to use wider 
> >traces if large currants are involved. 
> >
> More important, copper that's shiny on the bottom. Most of the current 
> is on the dielectric side. 
> 
> Regular PCB: 
> 
> https://www.dropbox.com/s/m65gd96vs8j5qp8/PCB_foil_peel.jpg?raw=1 
> 
> Isola, medium-range microwave laminate 
> 
> https://www.dropbox.com/s/7nwkho3kl1zx2bl/Isola_Peel.jpg?raw=1 
> 
> A serious microwave laminate is full shiny and peels with a toothpick.

There is one good thing about FR4 at high frequencies:  The high losses mean that
reflections are quickly damped, so impedance matching is not quite so critical.
This is quite useful on 10Gbit/s data tracks where attenuation is not necessarily
a problem but multiple reflections causing notches in the frequency response
would be.

John