On Thu, 21 Jul 2022 12:35:52 -0400, bitrex <user@example.net> wrote:>On 7/21/2022 12:09 PM, jlarkin@highlandsniptechnology.com wrote: >> On Thu, 21 Jul 2022 11:36:01 -0400, bitrex <user@example.net> wrote: >> >>> On 7/21/2022 10:55 AM, jlarkin@highlandsniptechnology.com wrote: >>>> On Thu, 21 Jul 2022 10:15:20 -0400, bitrex <user@example.net> wrote: >>>> >>>>> On 7/21/2022 10:12 AM, bitrex wrote: >>>>>> On 7/21/2022 4:33 AM, John Walliker wrote: >>>>>>> On Thursday, 21 July 2022 at 07:49:43 UTC+1, whit3rd wrote: >>>>>>>> On Wednesday, July 20, 2022 at 4:21:08 PM UTC-7, John Larkin wrote: >>>>>>>>> Suppose I have several rackmount boxes and each has a BNC connector on >>>>>>>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a >>>>>>>>> lowpass filtered schmitt gate back into our FPGA. >>>>>>>>> >>>>>>>>> I can daisy-chain several boxes with BNC cables and tees. >>>>>>>>> >>>>>>>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least >>>>>>>>> time-align them to always be the same within a few microseconds, >>>>>>>>> longterm. >>>>>>>> If you can tolerate 'a few microseconds' on a 40 MHz signal, that's >>>>>>>> not a phase-lock >>>>>>>> problem, it's a frequency-lock problem. Why not just run an up/down >>>>>>>> counter >>>>>>>> to generate a correction voltage for each non-leading VCO? >>>>>>> >>>>>>> If you have an ethernet interface to each unit then Precision Time >>>>>>> Protocol >>>>>>> should do exactly what you want. >>>>>>> https://en.wikipedia.org/wiki/Precision_Time_Protocol >>>>>>> John >>>>>> >>>>>> Yeah, that sounds like the ticket to me also. Trying to use each box's >>>>>> system clock for purposes of keeping "user-space" tasks in sync across >>>>>> boxes makes me uncomfortable, sounds like a srs hack. >>>>> >>>>> At minimum it likely won't scale very well. Why implicitly discourage >>>>> one's customers from buying only a limited number of units >>>> >>>> Time synchronization of programmable power supplies and loads is >>>> precisely one selling feature that my customers want but nobody else >>>> seems to make. It works fine in one box but I want to extend the >>>> function to multiple boxes in a rack. >>>> >>>> The controller in each box is a MicroZed and doesn't support the PTP >>>> thing, and my customers may not be able top provide it anyhow. The 1 >>>> PPS thing works with just a BNC cable. >>>> >>>> Besides, what I do is design things. >>>> >>> >>> >>> So if it works fine in one box why can't you just send some simple >>> packet data that says like OK box 4, run program 2 now for 1,084 ms. >>> >>> If they're all already locked individually to GPS or whatever other >>> standard they know how long a ms is. There will be some overhead latency >>> but syncing a bunch of boxes within a ms doesn't seem unreasonable. >>> >>> It's at least easier to ballpark how well a digital scheme like that >>> would scale on paper. The BNC scheme is analog, how do you know. >> >> The BNC would be 1 PPS pulses. They could come from GPS if it's >> available, or one of the boxes could output the 1 PPS and the others >> would sync to that. >> >> When we designed the box, we added two BNCs, open drain drivers with >> weak pullups and schmitt receivers, connected into our FPGA. We didn't >> know what they were for, but they turn out to be handy. > I see. > >> One is START RUNNING YOUR SEQUENCES NOW and the other is the 1 PPS >> lock. That should work. >> >> Each module has a sequencer table in its local fpga RAM, sort of a >> primitive program with 5 opcodes. A table entry can write any other >> register in the FPGA, ie do anything, and one command is WAIT UNTIL, >> against the 1 MHz start counter. >> >> Customers can write fairly simple SCPI script files to program events >> in each module, load them up, and fire off a shot and keep the whole >> experiment time synchronized forever. > >Gotcha > >> All we want to do is revolutionize the power supply business. > >Sounds good > >> It's actually useful to me to type and discuss this sort of thing. >> Ideas evolve at their own rates. >> > >I'm just sayin there's also a standard (uh oh!) dating back to the 50s >for synchronizing equipment using time-code: > ><https://en.wikipedia.org/wiki/IRIG_timecode> > >up to 10,000 pulses per second. I understand now that there's no >facility to program or sequence one box from the others they each run >their own "script" from memory. > >It would seem simpler to flip a switch to designate one box as the >master and have the others watch a timecode it sends out at a higher >resolution than the desired sync error. If the master then needs to >itself be synced to real-world time via a GPSDO then ah...well I guess >there should've been a 3rd BNC :-(There should be a third BNC, or a D9 or something. Synchronizing boxes has et up all my general-puropse i/o's.
really slow PLL
Started by ●July 20, 2022
Reply by ●July 22, 20222022-07-22
Reply by ●July 22, 20222022-07-22
On Thu, 21 Jul 2022 10:30:44 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:>torsdag den 21. juli 2022 kl. 01.21.08 UTC+2 skrev John Larkin: >> Suppose I have several rackmount boxes and each has a BNC connector on >> the back. Each of them has an open-drain mosfet, a weak pullup, and a >> lowpass filtered schmitt gate back into our FPGA. >> >> I can daisy-chain several boxes with BNC cables and tees. >> >> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least >> time-align them to always be the same within a few microseconds, >> longterm. >> >> I could call one the leader (not "master") and make the others >> followers (not "slaves") and have the leader make an active low pulse >> maybe once a second. > >why so slow?The design intended the outputs to be relay drivers with debounced schmitt-trigger inputs. So they are fairly slow. And lots of people have a 1 PPS GPS thing.> >> A follower would use her (not "his") clock to >> measure the incoming period and tweak its local VCXO in the right >> direction. That should work. > >it'll only make the run at at the same speed, not time aligned >No, I can really time align long-term, after the first accepted 1 PPS pulse. I've presented that in another post. One BNC locks the timebases and the other starts sequences, all together. It's only a power supply, so we don't need absolute timing to nanoseconds. Switchers alone add microsecond or even millisecond-scale uncertainty to the analog outputs.
Reply by ●July 22, 20222022-07-22
Don Y wrote:> bitrex wrote:<snip>>> Yeah I don't quite get it, either. My rack of synthesizers can each play one >> voice of the Maple Leaf Rag via MIDI and they all stay synced together really > > How is "really well" defined? In the domain of human auditory perception?In this case, isn't "really well" defined as an absence of sour note(s)? Danke, -- Don, KB7RPU, https://www.qsl.net/kb7rpu There was a young lady named Bright Whose speed was far faster than light; She set out one day In a relative way And returned on the previous night.
Reply by ●July 22, 20222022-07-22
On 7/21/2022 8:58 PM, Don wrote:> Don Y wrote: >> bitrex wrote: > > <snip> > >>> Yeah I don't quite get it, either. My rack of synthesizers can each play one >>> voice of the Maple Leaf Rag via MIDI and they all stay synced together really >> >> How is "really well" defined? In the domain of human auditory perception? > > In this case, isn't "really well" defined as an absence of sour note(s)?That assumes the synthesis uses the same clock as timing. I think the discussion here has been wrt durations/intervals. How sensitive are *your* ears to noticing small differences in pitch, absence a comparative reference? Can you discern a difference of a few cents ("perfect pitch")?
Reply by ●July 22, 20222022-07-22
jlarkin@highlandsniptechnology.com wrote:> On Fri, 22 Jul 2022 00:08:56 -0000 (UTC), Cydrome Leader > <presence@MUNGEpanix.com> wrote: > >>jlarkin@highlandsniptechnology.com wrote: >>> On Thu, 21 Jul 2022 07:43:18 +0200, Gerhard Hoffmann <dk4xp@arcor.de> >>> wrote: >>> >>>>Am 21.07.22 um 01:20 schrieb John Larkin: >>>>> >>>>> >>>>> Suppose I have several rackmount boxes and each has a BNC connector on >>>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a >>>>> lowpass filtered schmitt gate back into our FPGA. >>>>> >>>>> I can daisy-chain several boxes with BNC cables and tees. >>>>> >>>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least >>>>> time-align them to always be the same within a few microseconds, >>>>> longterm. >>>> >>>>I have a backburner project of locking 16 MTI-260 oscillators >>>>slooowy to another one, and when they are in sync, combine >>>>them with an array of Wilkinsons. That should have a nice >>>>effect on phase noise by averaging over 16. >>>>The CPLD has enough resources to implement that as a delay >>>>locked loop with 1 pps, but low hanging fruit first. >>>> >>>>> >>>>> I could call one the leader (not "master") and make the others >>>>> followers (not "slaves") and have the leader make an active low pulse >>>>> maybe once a second. A follower would use her (not "his") clock to >>>>> measure the incoming period and tweak its local VCXO in the right >>>>> direction. That should work. >>>>> >>>>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse >>>>> from the satellites? >>>> >>>>No. There is no 1PPS pulse from the sat nor the need for exactly 10 MHz. >>>>The sats transmit a pseudo noise sequence that is >>>>aligned to the second of their local clock source. >>>>The GPS receiver knows the polynomial and runs a local copy of >>>>the polynomial. It knows by cross correlation if the local >>>>pseudo noise is the same as that of the sat and therefore knows >>>>the start of the second. Usually that won't be the case. >>>>Then the receiver delays its own polynomial by omitting a >>>>clock to the shift register that generates it and tries again. >>>>Sooner or later it will fit. >>> >>> Where does the 10 MHz come from? >> >>https://en.wikipedia.org/wiki/GPS_disciplined_oscillator > > "GPSDOs typically phase-align the internal flywheel oscillator to the > GPS signal by using dividers to generate a 1PPS signal from the > reference oscillator, then phase comparing this 1PPS signal to the > GPS-generated 1PPS signal and using the phase differences to control > the local oscillator frequency in small adjustments via the tracking > loop." > > That's what I meant: the 10M xo is locked to the 1 PPS GPS output. > > The GPS 1 PPS is perfect (by definition) long-term but terrible > short-term, so the XO or rubidium has to be very good itself, and the > loop has to be very slow. Big flywheel.GPS timing isn't completely perfect in reality. Antennas blow off roofs, contractors cut cables etc. Even losing sync for a minute is sort of a big deal. As you mentioned, jitter is the real problem. There are tradeoffs to making a flywheel thats too heavy so to speak. For really fussy stuff, one might have multiple GPS receivers and a quorum of local 10Mhz oscillators. In fact, 10Mhz is a dinosaur relic for modern stuff too. We've got racks of 10Mhz oscillators and equipment to monitor any phase shift between local oscillators and GPS sources. It's all going to the dumpster when somebody finally notices it's been powered down and forgotten about. Fairly accurate nS resolution timing is possible in computers these days, with the right tricks.> I'll be doing something similar, locking my 40 MHz clock to some 1 PPS > input, the difference being that I don't mind a few us of jitter, so I > can lock quick and crude.Do you have to worry about fun issues like an the timestamp of a signal being received before it was even transmitted between pieces of equipment? I like the toggle switches on the USNO hydrogen masers: https://www.cnmoc.usff.navy.mil/Organization/United-States-Naval-Observatory/Precise-Time-Department/The-USNO-Master-Clock/The-USNO-Master-Clock/ They were originally made by some weird company called Sigma Tau. Somehow, Microchip owns them now. New models have a new paint job, but still look like they might be a transit case for a Dalek.
Reply by ●July 22, 20222022-07-22
On 22/07/2022 03:44, Clifford Heath wrote:> On 22/7/22 03:10, Phil Hobbs wrote: >> Gerhard Hoffmann wrote: >>> Am 21.07.22 um 16:15 schrieb Phil Hobbs: >>> >>>> I wonder if there's an advantage to using the closure phase for an >>>> array that large. With 17 oscillators you've got 136 independent >>>> phase differences, so maybe there's a way to get 22 dB instead of 12 >>>> dB improvement. >>> >>> -v ? >>> >>> what do you mean with closure phase? Where do the 22 dB come >>> from? >>> >>> The idea was simply to have all 16 regulated to the be >>> synchronous and then feed them into a 16-to--1 Wilkinson >>> combiner. The phase noise should average out among the >>> 16 units. Just as proof of concept. The MTI-260 are quite ok, >>> but with bleeding edge oscillators that could be interesting. >>> In the region where you just cannot improve an oscillator. >>> >>>> Cheers >>> Gerhard >> >> Sure. Thing is, that wastes a lot of information that you could maybe >> use to get 10*log(136) = 21.3 dB improvement instead of 10*log(17) = >> 12.3 dB. [136 = N(N-1)/2 when N = 17.] >> >> Closure is a really cute idea, which I first came across in the >> context of very long baseline interferometry (VLBI) radio telescopes. >> See the discussion from BEOS 3e here: >> >> <https://electrooptical.net/www/sed/closure.png>. > > Interesting, thanks. > > Some frequency synthesiser chips employ proprietary majick to reduce the > phase noise associated with integer divide/multiply ratios. Polyphase > oscillator and slipping by partial cycles I think. Perhaps they're doing > something like closure against the different clock phases?Quite probably - it has been known for a long time in radio astronomy first derived by Jennison in 1958 at Jodrell Bank for 3 antennae. This is the original ground breaking paper for anyone interested https://articles.adsabs.harvard.edu//full/1958MNRAS.118..276J/0000276.000.html (easier to understand versions exist today). WIki isn't bad: https://en.wikipedia.org/wiki/Closure_phase It allows you to get a good phase observable uncontaminated by the phase error at each node for every distinct subset of 3 nodes. There is a corresponding closure amplitude for distinct subsets of 4 nodes. Obviously the bigger N is the more useful observables you can get which is why the big dish telescopes sometimes stay on target and in the loop for perhaps longer than they really ought to in deteriorating weather. This book reviews most of the classical tricks used in VLBI and interferometry from the period when they had just become routine: Indirect Imaging: Measurement and Processing for Indirect Imaging Editor-J. A. Roberts 0 ratings by Goodreads ISBN 10: 0521262828 / ISBN 13: 9780521262828 Published by Cambridge University Press, 1984 -- Regards, Martin Brown
Reply by ●July 22, 20222022-07-22
Am 22.07.22 um 04:47 schrieb jlarkin@highlandsniptechnology.com:>>> Where does the 10 MHz come from? >> >> https://en.wikipedia.org/wiki/GPS_disciplined_oscillator > > "GPSDOs typically phase-align the internal flywheel oscillator to the > GPS signal by using dividers to generate a 1PPS signal from the > reference oscillator, then phase comparing this 1PPS signal to the > GPS-generated 1PPS signal and using the phase differences to control > the local oscillator frequency in small adjustments via the tracking > loop." > > That's what I meant: the 10M xo is locked to the 1 PPS GPS output.No. The 1pps is asserted when the CPU thinks it's closest to the "right" clockcycle. It could be off by half a cycle. There is no need for 10 MHz, one could have chosen a nice multiple of the desired baud rate. The 1pps does not control the clock, its the huge state vector in the CPU that does. 1pps is only an approximation, that's why it's so bad in the short term. Locking an oscillator via 1pps is only done when there is nothing better available, outside the GPS box. < http://www.leapsecond.com/pages/m12/sawtooth.htm > Cheers, Gerhard
Reply by ●July 22, 20222022-07-22
On 21/07/2022 12:42, jlarkin@highlandsniptechnology.com wrote:> On Thu, 21 Jul 2022 12:06:26 +0100, Martin Brown > <'''newspam'''@nonad.co.uk> wrote: > >> On 21/07/2022 01:22, John Larkin wrote:>>> If a follower is told to start locking, it could timestamp the first >>> incoming 1 PPS with a giant counter clocked by its local 40 MHz VCO. >>> If a later 1 PPS edge appears to arrive too soon, we could speed up >>> our VCXO by, say, 1 PPM, and vice versa. So longterm it walks into >>> alignment with the 1 PPS and eventually dithers a microsecond per >>> second. Noise on the coax gets fixed over time too. >> >> Have a free running counter on each of the followers and use the value >> of that after 1s, 10s, 100s to determine the correct tweak to apply >> locally. Tweaks of 1ppm at a time is rather crude you should be able to >> determine the right amount to tweak it by better than that. >> (especially over longer timebases) > > I wouldn't expect my VCXO to be more than 10 PPM off at the start of > the lock request. So I can walk it to within 1 PPM, namely 1 > microsecond error, in at most 10 seconds using 1 PPM jogs. If the osc > were 50 PPM off, it would take 50 seconds to catch up to the external > pulse.You would have lower systematic error after lockin if you made the adjustments by reading the full width counter as a two's compliment number when the synch pulse arrives (and using a 2^N counter).>>> That's better than just measuring the 1 Hz period once a second, >>> tweaking the clock, and then throwing away that measurement. I want a >>> time lock, not a frequency lock. >> >> Then you probably want to measure the cumulative error over many >> seconds. Each unit can work out how long it can free run without >> exceeding tolerance once it has the rough and ready count from the first >> second. After that you have a good idea of how many seconds you can free >> run for without having any ambiguities from residual drift. > > Yes, I don't want to measure period once a second. I want to compare > time alignment forever after receiving the first 1 pps pulse. > > It's actually simple: first received pulse, start a mod 40 million > counter. Every time it rolls over, do an early/late compare to the 1 > PPS input, and jog the 40 MHz VCXO 1 PPM in the right direction. > > The compare is a dflop, d is the msb of the counter, clock is the 1 > PPS input. Occasional metastability is fine; it indicates success. > > It doesn't even need to be a 40 million counter. Something a fraction > of that will do. 10,000 maybe.Unless you are very wedded to base 10 it might well work better to use a hardware 16 or 24 bit counter and allow it to free run. The master clock time pulses could be at some suitable power of 2^N x 0.1us. Under software control you could even do quick corrections in the first second to get the basic frequency of all clocks approximately right. The master could produce a set of pulses that were 1/16s, 1/8s, 1/4s, 1/2, 1s long at the outset. That would speed up the lock in time.> Maybe the counter can just free-run, never get initialized. Gotta do > the math on that after I wake up.If you want to get the clocks on the various boxes as close to in synch as possible then it makes sense to correct any errors quickly. Power of 2 steps decreasing to some floor level being most favourable. -- Regards, Martin Brown
Reply by ●July 22, 20222022-07-22
On 21/07/2022 18:41, bitrex wrote:> On 7/21/2022 1:21 PM, Martin Brown wrote:>> IEEE488 was good in its day but a bit long in the tooth now. Still on >> some test equipment in service today and was provided as standard on >> NEC 9801 PC's in Japan although hardly ever used by their customers. >> >> The cables and connectors could only be described as a bit clunky! >> They really didn't get on with metal swarf being around but were OK in >> clean dry electronics/physics labs - much less so in chemistry ones... > > I feel like there wasn't really a good relatively inexpensive standard > for interfacing PC peripherals until USB. Serial and parallel were slow > (occasionally some devices supported ECP, I remember having to enable it > in the BIOS sometimes), and external SCSI wasn't really well-suited to > anything but external disk drives.There were bidirectional parallel ports that could run fairly quick. A parallel port interface for a CD drive was just about doable on a bog standard PC parallel port. SCSI was quite good for external bulk data devices like scanners too. It's disadvantage was cost. I recall early versions of USB 1.x very unfondly. ISTR the acronym was originally take to be Unusable Serial Bus (cf Firewire implementations). It slowly improved with successive Doze versions to become merely Unstable Serial Bus. Firewire easily left it standing. https://en.wikipedia.org/wiki/IEEE_1394#Comparison_with_USB USB eventually won out by being cheaper. Much like VHS vs Betamax - the superior technology was effectively sidelined by popularity of the rival. Even today there are USB peripherals that never come back when a PC goes into sleep mode without being unplugged and plugged in again.> I don't think you could hot-swap IEE-488 either but it seems like it was > pretty fast and more amenable to a wide class of devices than SCSI, but > just didn't seem to catch on outside the test equipment realm.GPIB and HPIB was fairly common on desktop computers in the early 80's. HP and Commodore used it for their external disk drives. We hacked an interface for the Commodore hard disk drive but the HP harddrive blinded the bus analysers of the day and by the time we had hacked it cheaper options were already available. It survived as a niche instrumentation bus until the turn of the century and is possibly still used by some. The instruments using it still being pretty good kit. Token ring WAN over cheap twisted pairs took over for a while in my neck of the woods before truly fast Ethernet really got going. (it was an academic predecessor of IBM's token ring offering) Early fast ethernet distribution was on expensive thick heavy coax cable marked up with where to tap into them. The cost difference for wiring up was enormous. Physically manhandling the cable was a PITA. -- Regards, Martin Brown
Reply by ●July 22, 20222022-07-22
On 7/22/2022 2:36 AM, Martin Brown wrote:> On 21/07/2022 18:41, bitrex wrote: >> On 7/21/2022 1:21 PM, Martin Brown wrote: > >>> IEEE488 was good in its day but a bit long in the tooth now. Still on some >>> test equipment in service today and was provided as standard on NEC 9801 >>> PC's in Japan although hardly ever used by their customers. >>> >>> The cables and connectors could only be described as a bit clunky! >>> They really didn't get on with metal swarf being around but were OK in clean >>> dry electronics/physics labs - much less so in chemistry ones... >> >> I feel like there wasn't really a good relatively inexpensive standard for >> interfacing PC peripherals until USB. Serial and parallel were slow >> (occasionally some devices supported ECP, I remember having to enable it in >> the BIOS sometimes), and external SCSI wasn't really well-suited to anything >> but external disk drives. > > There were bidirectional parallel ports that could run fairly quick. > A parallel port interface for a CD drive was just about doable on a bog > standard PC parallel port.But old ports (without queues) were a bitch for the processor to service.> SCSI was quite good for external bulk data devices like scanners too. It's > disadvantage was cost.And cable length. Aside from differential (even costlier), you were stuck to "arm's reach". At least serial and USB can be pushed to longer lengths (despite limitations of their respective standards).> Token ring WAN over cheap twisted pairs took over for a while in my neck of the > woods before truly fast Ethernet really got going. > (it was an academic predecessor of IBM's token ring offering)IBM's suffered from the same sort of costs as SCSI with their big, klunky connectors.> Early fast ethernet distribution was on expensive thick heavy coax cable marked > up with where to tap into them. The cost difference for wiring up was enormous. > Physically manhandling the cable was a PITA.Ah, yes. "Orange hose" and vampire taps. I suspect one could make a pretty little structure (think: Lincoln Logs) out of lengths of that! A likely factor in its lack of ubiquity. I rely on network connectivity for an increasing number of appliances, now. Scanners (direct network connections or USB to SBC host), disks (iSCSI), printers (direct network connections or dedicated print server appliance), other computers, etc. But, all of the T/TX technologies make cabling a PITA. Every cable has to travel all the way to a switch, even if some other networked device is nearby (e.g., 10Base2 would tolerate device insertion with just a short length of coax -- though the entire network was disrupted in the process!) I have thick bundles of CAT5e affixed to the undersides of my workbenches as the cables from each device (on or under the bench) join the bundle as it travels to the east or west switch. Add a new device? Ugh! IMO, most interfaces fall down (in practical terms) when it comes to the choice of connector. Either too cheap (flimsy) or too costly. The RJ45/8P8C wins in terms of cost... but is a nuisance when the locking tab inevitably breaks off (even if "guarded"): "Great! Now I either repair the cable or replace it!" And, inevitably, connectors require a bit of "fiddling" to ensure oriented correctly and mated well. How many times do you discover a bent pin on a HD SCSI cable only because the interface refuses to run properly? (and trying to repair said pin is essentially impossible). And, of course, the wide choice of "standards" (SCSI cables being among the worst for lack of uniformity: Old Sun, Apple, SCSI, SCSI2, SCSI3, VHDCI, etc.) The ideal connector wouldn't have a top or bottom (etc.) Something like a phone plug where all you have to do is line up plug to hole and jam it home. Considering most connectors reside on the backs of equipment, expecting the user to be able to VIEW the mate while attempting to connect is wishful thinking!
