Version 4 SHEET 1 880 680 WIRE 480 -32 384 -32 WIRE 608 -32 560 -32 WIRE 608 80 608 -32 WIRE 608 80 544 80 WIRE 656 80 608 80 WIRE 688 80 656 80 WIRE -112 96 -160 96 WIRE -64 96 -112 96 WIRE 48 96 16 96 WIRE 80 96 48 96 WIRE 240 96 192 96 WIRE 272 96 240 96 WIRE 384 96 384 -32 WIRE 384 96 336 96 WIRE 432 96 384 96 WIRE 480 96 432 96 WIRE -160 144 -160 96 WIRE 80 144 80 96 WIRE 192 144 192 96 WIRE -160 256 -160 224 WIRE 80 256 80 224 WIRE 192 256 192 224 FLAG 80 256 0 FLAG 192 256 0 FLAG -160 256 0 FLAG 656 80 OUT FLAG 432 96 G FLAG 240 96 S FLAG 48 96 P FLAG -112 96 IN SYMBOL ind2 64 128 R0 WINDOW 0 -53 39 Left 2 WINDOW 3 -60 70 Left 2 SYMATTR InstName L1 SYMATTR Value 10� SYMATTR Type ind SYMBOL ind2 176 128 R0 WINDOW 0 56 34 Left 2 WINDOW 3 51 66 Left 2 SYMATTR InstName L2 SYMATTR Value 10� SYMATTR Type ind SYMBOL res 32 80 R90 WINDOW 0 -40 54 VBottom 2 WINDOW 3 -34 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 50 SYMBOL res 464 -16 R270 WINDOW 0 -38 20 VTop 2 WINDOW 3 -10 94 VBottom 2 SYMATTR InstName R2 SYMATTR Value 200 SYMBOL voltage -160 128 R0 WINDOW 0 39 113 Left 2 WINDOW 3 -61 184 Left 2 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 5 10n 5n 5n 10u 20u 10) SYMBOL Digital\\schmitt 480 32 R0 WINDOW 0 15 116 Left 2 SYMATTR InstName A1 SYMATTR SpiceLine Vhigh=3.3 VT=1.65 VH=0.4 Td=5n SYMBOL cap 336 80 R90 WINDOW 0 -48 30 VBottom 2 WINDOW 3 -39 29 VTop 2 SYMATTR InstName C1 SYMATTR Value 250p TEXT 64 40 Left 2 !K1 L1 L2 0.98 TEXT 352 304 Left 2 !.tran 0 250u 0 1n TEXT 360 208 Left 2 ;Logic Coupler TEXT 352 256 Left 2 ;JL Dec 29 2021 -- I yam what I yam - Popeye
transformer coupled logic isolator
Started by ●December 30, 2021
Reply by ●December 30, 20212021-12-30
On Thursday, December 30, 2021 at 4:11:21 PM UTC+11, jla...@highlandsniptechnology.com wrote:> Version 4 > SHEET 1 880 680 > WIRE 480 -32 384 -32 > WIRE 608 -32 560 -32 > WIRE 608 80 608 -32 > WIRE 608 80 544 80 > WIRE 656 80 608 80 > WIRE 688 80 656 80 > WIRE -112 96 -160 96 > WIRE -64 96 -112 96 > WIRE 48 96 16 96 > WIRE 80 96 48 96 > WIRE 240 96 192 96 > WIRE 272 96 240 96 > WIRE 384 96 384 -32 > WIRE 384 96 336 96 > WIRE 432 96 384 96 > WIRE 480 96 432 96 > WIRE -160 144 -160 96 > WIRE 80 144 80 96 > WIRE 192 144 192 96 > WIRE -160 256 -160 224 > WIRE 80 256 80 224 > WIRE 192 256 192 224 > FLAG 80 256 0 > FLAG 192 256 0 > FLAG -160 256 0 > FLAG 656 80 OUT > FLAG 432 96 G > FLAG 240 96 S > FLAG 48 96 P > FLAG -112 96 IN > SYMBOL ind2 64 128 R0 > WINDOW 0 -53 39 Left 2 > WINDOW 3 -60 70 Left 2 > SYMATTR InstName L1 > SYMATTR Value 10µ > SYMATTR Type ind > SYMBOL ind2 176 128 R0 > WINDOW 0 56 34 Left 2 > WINDOW 3 51 66 Left 2 > SYMATTR InstName L2 > SYMATTR Value 10µ > SYMATTR Type ind > SYMBOL res 32 80 R90 > WINDOW 0 -40 54 VBottom 2 > WINDOW 3 -34 56 VTop 2 > SYMATTR InstName R1 > SYMATTR Value 50 > SYMBOL res 464 -16 R270 > WINDOW 0 -38 20 VTop 2 > WINDOW 3 -10 94 VBottom 2 > SYMATTR InstName R2 > SYMATTR Value 200 > SYMBOL voltage -160 128 R0 > WINDOW 0 39 113 Left 2 > WINDOW 3 -61 184 Left 2 > WINDOW 123 0 0 Left 0 > WINDOW 39 0 0 Left 0 > SYMATTR InstName V1 > SYMATTR Value PULSE(0 5 10n 5n 5n 10u 20u 10) > SYMBOL Digital\\schmitt 480 32 R0 > WINDOW 0 15 116 Left 2 > SYMATTR InstName A1 > SYMATTR SpiceLine Vhigh=3.3 VT=1.65 VH=0.4 Td=5n > SYMBOL cap 336 80 R90 > WINDOW 0 -48 30 VBottom 2 > WINDOW 3 -39 29 VTop 2 > SYMATTR InstName C1 > SYMATTR Value 250p > TEXT 64 40 Left 2 !K1 L1 L2 0.98 > TEXT 352 304 Left 2 !.tran 0 250u 0 1n > TEXT 360 208 Left 2 ;Logic Coupler > TEXT 352 256 Left 2 ;JL Dec 29 2021Adding 1pF of parallel capacitance across each of L1 and L2 made the output look a lot less neat. I haven't dug in to work out why, but capacitance-free 10uH doesn't look too realistic. It would be nice if John told us how he thought that he'd get that. Presumably he has something off-the shelf from Coilcraft in mind. If it were wound with twisted pair it would have capacitance between the windings and the coupling might be better than 0.98 . Two physically separated single layer windings on different parts of one core might do it. -- Bill Sloman, Sydney -- Bill Sloman, Sydney
Reply by ●December 30, 20212021-12-30
On Thursday, December 30, 2021 at 5:15:17 PM UTC+11, Anthony William Sloman wrote:> On Thursday, December 30, 2021 at 4:11:21 PM UTC+11, jla...@highlandsniptechnology.com wrote: > > Version 4 > > SHEET 1 880 680 > > WIRE 480 -32 384 -32 > > WIRE 608 -32 560 -32 > > WIRE 608 80 608 -32 > > WIRE 608 80 544 80 > > WIRE 656 80 608 80 > > WIRE 688 80 656 80 > > WIRE -112 96 -160 96 > > WIRE -64 96 -112 96 > > WIRE 48 96 16 96 > > WIRE 80 96 48 96 > > WIRE 240 96 192 96 > > WIRE 272 96 240 96 > > WIRE 384 96 384 -32 > > WIRE 384 96 336 96 > > WIRE 432 96 384 96 > > WIRE 480 96 432 96 > > WIRE -160 144 -160 96 > > WIRE 80 144 80 96 > > WIRE 192 144 192 96 > > WIRE -160 256 -160 224 > > WIRE 80 256 80 224 > > WIRE 192 256 192 224 > > FLAG 80 256 0 > > FLAG 192 256 0 > > FLAG -160 256 0 > > FLAG 656 80 OUT > > FLAG 432 96 G > > FLAG 240 96 S > > FLAG 48 96 P > > FLAG -112 96 IN > > SYMBOL ind2 64 128 R0 > > WINDOW 0 -53 39 Left 2 > > WINDOW 3 -60 70 Left 2 > > SYMATTR InstName L1 > > SYMATTR Value 10µ > > SYMATTR Type ind > > SYMBOL ind2 176 128 R0 > > WINDOW 0 56 34 Left 2 > > WINDOW 3 51 66 Left 2 > > SYMATTR InstName L2 > > SYMATTR Value 10µ > > SYMATTR Type ind > > SYMBOL res 32 80 R90 > > WINDOW 0 -40 54 VBottom 2 > > WINDOW 3 -34 56 VTop 2 > > SYMATTR InstName R1 > > SYMATTR Value 50 > > SYMBOL res 464 -16 R270 > > WINDOW 0 -38 20 VTop 2 > > WINDOW 3 -10 94 VBottom 2 > > SYMATTR InstName R2 > > SYMATTR Value 200 > > SYMBOL voltage -160 128 R0 > > WINDOW 0 39 113 Left 2 > > WINDOW 3 -61 184 Left 2 > > WINDOW 123 0 0 Left 0 > > WINDOW 39 0 0 Left 0 > > SYMATTR InstName V1 > > SYMATTR Value PULSE(0 5 10n 5n 5n 10u 20u 10) > > SYMBOL Digital\\schmitt 480 32 R0 > > WINDOW 0 15 116 Left 2 > > SYMATTR InstName A1 > > SYMATTR SpiceLine Vhigh=3.3 VT=1.65 VH=0.4 Td=5n > > SYMBOL cap 336 80 R90 > > WINDOW 0 -48 30 VBottom 2 > > WINDOW 3 -39 29 VTop 2 > > SYMATTR InstName C1 > > SYMATTR Value 250p > > TEXT 64 40 Left 2 !K1 L1 L2 0.98 > > TEXT 352 304 Left 2 !.tran 0 250u 0 1n > > TEXT 360 208 Left 2 ;Logic Coupler > > TEXT 352 256 Left 2 ;JL Dec 29 2021> Adding 1pF of parallel capacitance across each of L1 and L2 made the output look a lot less neat. I haven't dug in to work out why, but capacitance-free 10uH doesn't look too realistic.That's what I thought that I'd done. When I started digging in I found out that what I'd added was parallel resistance, and that did mess up circuit.> > It would be nice if John told us how he thought that he'd get that. Presumably he has something off-the shelf from Coilcraft in mind. If it were wound with twisted pair it would have capacitance between the windings and the coupling might be better than 0.98 .> Two physically separated single layer windings on different parts of one core might do it.Years ago - around 1979 - I staked a ferrite core to a board with some eight u-shaped wire links. Half of them were the primary winding and the other half the isolated secondary, and I relied on a receiver with hysteresis to hold the square wave output beyond the time constant of the inductance. It was much slower - for process control - but worked fine. --> Bill Sloman, Sydney
Reply by ●December 30, 20212021-12-30
On 30-Dec-21 4:11 pm, jlarkin@highlandsniptechnology.com wrote:> Version 4<snip> What is the use-case for this that a conventional digital isolator wouldn't be suitable for? Sylvia.
Reply by ●December 30, 20212021-12-30
On Thu, 30 Dec 2021 19:04:22 +1100, Sylvia Else <sylvia@email.invalid> wrote:>On 30-Dec-21 4:11 pm, jlarkin@highlandsniptechnology.com wrote: >> Version 4 > ><snip> > >What is the use-case for this that a conventional digital isolator >wouldn't be suitable for? > >Sylvia.Sometimes used in lower frequency isolated gate drive, when minimal magnetics cost is the aim. RL
Reply by ●December 30, 20212021-12-30
legg wrote:> On Thu, 30 Dec 2021 19:04:22 +1100, Sylvia Else <sylvia@email.invalid> > wrote: > >> On 30-Dec-21 4:11 pm, jlarkin@highlandsniptechnology.com wrote: >>> Version 4 >> >> <snip> >> >> What is the use-case for this that a conventional digital isolator >> wouldn't be suitable for? >> >> Sylvia. > > Sometimes used in lower frequency isolated gate drive, when minimal > magnetics cost is the aim. > > RL >Or very fast edges are needed, as in the examples JL and I posted in the "CML-CML level shifter" thread. Logic isolators don't go much faster than 40 ns AFAICT. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Reply by ●December 30, 20212021-12-30
On Thu, 30 Dec 2021 19:04:22 +1100, Sylvia Else <sylvia@email.invalid> wrote:>On 30-Dec-21 4:11 pm, jlarkin@highlandsniptechnology.com wrote: >> Version 4 > ><snip> > >What is the use-case for this that a conventional digital isolator >wouldn't be suitable for? > >Sylvia.It has no internal clocks, so it's fast and has no jitter or EMI sources. It's cheap. Its high-side static power requirement is zero. And it's cute. Fun circuits don't need use cases. -- I yam what I yam - Popeye
Reply by ●December 30, 20212021-12-30
On Thu, 30 Dec 2021 10:22:06 -0500, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>legg wrote: >> On Thu, 30 Dec 2021 19:04:22 +1100, Sylvia Else <sylvia@email.invalid> >> wrote: >> >>> On 30-Dec-21 4:11 pm, jlarkin@highlandsniptechnology.com wrote: >>>> Version 4 >>> >>> <snip> >>> >>> What is the use-case for this that a conventional digital isolator >>> wouldn't be suitable for? >>> >>> Sylvia. >> >> Sometimes used in lower frequency isolated gate drive, when minimal >> magnetics cost is the aim. >> >> RL >> > >Or very fast edges are needed, as in the examples JL and I posted in the >"CML-CML level shifter" thread. Logic isolators don't go much faster >than 40 ns AFAICT. > >Cheers > >Phil HobbsRight. And most modulate/demodulate so have a lot of jitter. One could make a very fast low-jitter optical isolator, but it would be a big expensive power hog. -- I yam what I yam - Popeye
Reply by ●December 30, 20212021-12-30
On Thu, 30 Dec 2021 10:22:06 -0500, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>legg wrote: >> On Thu, 30 Dec 2021 19:04:22 +1100, Sylvia Else <sylvia@email.invalid> >> wrote: >> >>> On 30-Dec-21 4:11 pm, jlarkin@highlandsniptechnology.com wrote: >>>> Version 4 >>> >>> <snip> >>> >>> What is the use-case for this that a conventional digital isolator >>> wouldn't be suitable for? >>> >>> Sylvia. >> >> Sometimes used in lower frequency isolated gate drive, when minimal >> magnetics cost is the aim. >> >> RL >> > >Or very fast edges are needed, as in the examples JL and I posted in the >"CML-CML level shifter" thread. Logic isolators don't go much faster >than 40 ns AFAICT. > >Cheers > >Phil HobbsThat circuit was just a doodle. It would need tweaking in real life. It's most elegant when the transformer time constant matches the Schmitt feedback time constant, and when the final RC also damps any leakage inductance ringing. That actually gets complex. It really doesn't need a Schmitt gate, but it's nice. -- I yam what I yam - Popeye
Reply by ●December 30, 20212021-12-30
On Thu, 30 Dec 2021 09:08:03 -0500, legg <legg@nospam.magma.ca> wrote:>On Thu, 30 Dec 2021 19:04:22 +1100, Sylvia Else <sylvia@email.invalid> >wrote: > >>On 30-Dec-21 4:11 pm, jlarkin@highlandsniptechnology.com wrote: >>> Version 4 >> >><snip> >> >>What is the use-case for this that a conventional digital isolator >>wouldn't be suitable for? >> >>Sylvia. > >Sometimes used in lower frequency isolated gate drive, when minimal >magnetics cost is the aim. > >RLIt's faster than most isolators, and is DC-coupled, after a powerup priming shot. -- If a man will begin with certainties, he shall end with doubts, but if he will be content to begin with doubts he shall end in certainties. Francis Bacon
