Fast simple microcontroller

mandag den 5. juli 2021 kl. 15.13.45 UTC+2 skrev gnuarm.del...@gmail.com:
> On Monday, July 5, 2021 at 1:13:28 AM UTC-4, Chris Jones wrote: 
> > On 04/07/2021 01:01, Clive Arthur wrote: 
> > > On 03/07/2021 14:30, Chris Jones wrote: 
> > > 
> > > <snip> 
> > > 
> > >> You could do it in an FPGA. Obviously you could put a CPU with UART in 
> > >> the FPGA design, with the CPU running whatever code to make a menu you 
> > >> would have put on a micro, (but with peripherals that do exactly 
> > >> whatever fast logic you need, unlike those on most microcontrollers), 
> > >> though there are much more efficient ways. 
> > >> 
> > >> There are for example logic analyzers that you can drop into your fpga 
> > >> design, that connect to an external PC for debugging. This is much 
> > >> better than some printf statements to a uart, as you can get timing 
> > >> information about when things happen, that is much more accurate than 
> > >> over a UART. I think most of the bugs are usually caught in simulation 
> > >> so the need for debugging on the hardware may be rare anyway. 
> > >> 
> > > There are lots of timers. Timing information is garnered from them and 
> > > printed (though not with printf). On occasion a spare I/O pin might 
> > > trigger a scope. 
> > I do that too in firmware, but it is not ideal. When you put in code to 
> > trigger/capture the timers, the timing changes, so then you have to 
> > leave all the debugging code in for production, or just hope that the 
> > timing will still be right when you take it out. And if the compiler 
> > gets upgraded, all bets are off. Perhaps you write in pure assembler so 
> > you don't care about that. I would be less productive without a compiler.
> People talk as if coding an MCU is a piece of cake, mostly because this is what they are familiar with. The comfort factor is high even if they know there can be difficult to solve problems mostly having to do with the timing issues that result from sharing a sequential process between multiple, separate functions. In the most simple cases there are no real problems. In more difficult cases the problems can become quite complex. There are methods for managing these issues, but they are often not well understood or implemented. 
> 

swap mcu and fpga and you do the same for the same reasons .... 

mandag den 5. juli 2021 kl. 18.16.25 UTC+2 skrev Ed Lee:
> On Monday, July 5, 2021 at 8:51:20 AM UTC-7, gnuarm.del...@gmail.com wrote: 
> > On Monday, July 5, 2021 at 11:24:12 AM UTC-4, Ed Lee wrote: 
> > > On Monday, July 5, 2021 at 6:23:38 AM UTC-7, gnuarm.del...@gmail.com wrote: 
> > > > On Monday, July 5, 2021 at 12:01:26 AM UTC-4, Ed Lee wrote: 
> > > > > OK, i am asking you a very simply question. How do you change the clock speed on the fly for the FPGA. It's a simple write to registers in micro. 
> > > > However you wish. The circuit is yours to design. How would you like it to work? 
> > > > 
> > > > I like the fact that you keep talking about a "simple write to registers" as if you were programming a sequential processor with a linear address space like an MCU no matter what the device is. (I would also point out that the clocking controls are some of the most complex in any given MCU, so not often a "simple" register write). How would you adjust the clock speed in a discrete circuit design? An FPGA is just discrete logic inside a chip with programmable interconnects. Do you write to registers in analog designs too? 
> > > > 
> > > > I will repeat the problem. You continue to be stuck in the MCU mindset and are not willing to learn enough about FPGAs to actually understand them. You won't understand them until you stop pretending FPGAs are just different MCUs. Open your mind. Learn something. 
> > > Not if you keep side-stepping the question. I ask a very simple and direct question: How do you reconfig the PLL from the chip within? 
> > No side stepping. That was not the question you asked before.
> I asked you how to change the clock speed, which is driven by the PLL. It's the same question. And we, those who know nothing about FPGA, want you to tell us how to do that with the ICE40 FPGA you recommended.
> > Clock control is done using the logic resources inside the FPGA. If you are asking about programming the PLL, every device family is different. You can read about it in the data sheet for the clock distribution or some brands have a separate document just for the PLL. They tend to be more complex than a UART, so just listing the bits in registers doesn't explain it. I don't have any of this info memorized, so you will need to look at the docs yourself.
> I know how to do that from the Actel designer, but not from within the chip. If you want us to replace our micro with this ICE40 CPLD/FPGA, you should at least give us the link to do it. Otherwise, it's beyond our knowledge to attempt to use this CPLD/FPGA.


why would you want to change the clock? if you want lowpower standby, run the housekeeping a the slow clock, 
keep the pll and the fast stuff in reset when you don''t need it

On Monday, July 5, 2021 at 9:49:43 AM UTC-7, lang...@fonz.dk wrote:
> mandag den 5. juli 2021 kl. 18.16.25 UTC+2 skrev Ed Lee: 
> > On Monday, July 5, 2021 at 8:51:20 AM UTC-7, gnuarm.del...@gmail.com wrote: 
> > > On Monday, July 5, 2021 at 11:24:12 AM UTC-4, Ed Lee wrote: 
> > > > On Monday, July 5, 2021 at 6:23:38 AM UTC-7, gnuarm.del...@gmail.com wrote: 
> > > > > On Monday, July 5, 2021 at 12:01:26 AM UTC-4, Ed Lee wrote: 
> > > > > > OK, i am asking you a very simply question. How do you change the clock speed on the fly for the FPGA. It's a simple write to registers in micro. 
> > > > > However you wish. The circuit is yours to design. How would you like it to work? 
> > > > > 
> > > > > I like the fact that you keep talking about a "simple write to registers" as if you were programming a sequential processor with a linear address space like an MCU no matter what the device is. (I would also point out that the clocking controls are some of the most complex in any given MCU, so not often a "simple" register write). How would you adjust the clock speed in a discrete circuit design? An FPGA is just discrete logic inside a chip with programmable interconnects. Do you write to registers in analog designs too? 
> > > > > 
> > > > > I will repeat the problem. You continue to be stuck in the MCU mindset and are not willing to learn enough about FPGAs to actually understand them. You won't understand them until you stop pretending FPGAs are just different MCUs. Open your mind. Learn something. 
> > > > Not if you keep side-stepping the question. I ask a very simple and direct question: How do you reconfig the PLL from the chip within? 
> > > No side stepping. That was not the question you asked before. 
> > I asked you how to change the clock speed, which is driven by the PLL. It's the same question. And we, those who know nothing about FPGA, want you to tell us how to do that with the ICE40 FPGA you recommended. 
> > > Clock control is done using the logic resources inside the FPGA. If you are asking about programming the PLL, every device family is different. You can read about it in the data sheet for the clock distribution or some brands have a separate document just for the PLL. They tend to be more complex than a UART, so just listing the bits in registers doesn't explain it. I don't have any of this info memorized, so you will need to look at the docs yourself. 
> > I know how to do that from the Actel designer, but not from within the chip. If you want us to replace our micro with this ICE40 CPLD/FPGA, you should at least give us the link to do it. Otherwise, it's beyond our knowledge to attempt to use this CPLD/FPGA.
> why would you want to change the clock? if you want lowpower standby, run the housekeeping a the slow clock, 
> keep the pll and the fast stuff in reset when you don''t need it

Some function needs special speed.  For example, usb needs 48MHz exactly.  Others need higher speed just for speed and lower speed for power savings.

mandag den 5. juli 2021 kl. 19.05.27 UTC+2 skrev Ed Lee:
> On Monday, July 5, 2021 at 9:49:43 AM UTC-7, lang...@fonz.dk wrote: 
> > mandag den 5. juli 2021 kl. 18.16.25 UTC+2 skrev Ed Lee: 
> > > On Monday, July 5, 2021 at 8:51:20 AM UTC-7, gnuarm.del...@gmail.com wrote: 
> > > > On Monday, July 5, 2021 at 11:24:12 AM UTC-4, Ed Lee wrote: 
> > > > > On Monday, July 5, 2021 at 6:23:38 AM UTC-7, gnuarm.del...@gmail.com wrote: 
> > > > > > On Monday, July 5, 2021 at 12:01:26 AM UTC-4, Ed Lee wrote: 
> > > > > > > OK, i am asking you a very simply question. How do you change the clock speed on the fly for the FPGA. It's a simple write to registers in micro. 
> > > > > > However you wish. The circuit is yours to design. How would you like it to work? 
> > > > > > 
> > > > > > I like the fact that you keep talking about a "simple write to registers" as if you were programming a sequential processor with a linear address space like an MCU no matter what the device is. (I would also point out that the clocking controls are some of the most complex in any given MCU, so not often a "simple" register write). How would you adjust the clock speed in a discrete circuit design? An FPGA is just discrete logic inside a chip with programmable interconnects. Do you write to registers in analog designs too? 
> > > > > > 
> > > > > > I will repeat the problem. You continue to be stuck in the MCU mindset and are not willing to learn enough about FPGAs to actually understand them. You won't understand them until you stop pretending FPGAs are just different MCUs. Open your mind. Learn something. 
> > > > > Not if you keep side-stepping the question. I ask a very simple and direct question: How do you reconfig the PLL from the chip within? 
> > > > No side stepping. That was not the question you asked before. 
> > > I asked you how to change the clock speed, which is driven by the PLL. It's the same question. And we, those who know nothing about FPGA, want you to tell us how to do that with the ICE40 FPGA you recommended. 
> > > > Clock control is done using the logic resources inside the FPGA. If you are asking about programming the PLL, every device family is different. You can read about it in the data sheet for the clock distribution or some brands have a separate document just for the PLL. They tend to be more complex than a UART, so just listing the bits in registers doesn't explain it. I don't have any of this info memorized, so you will need to look at the docs yourself. 
> > > I know how to do that from the Actel designer, but not from within the chip. If you want us to replace our micro with this ICE40 CPLD/FPGA, you should at least give us the link to do it. Otherwise, it's beyond our knowledge to attempt to use this CPLD/FPGA. 
> > why would you want to change the clock? if you want lowpower standby, run the housekeeping a the slow clock, 
> > keep the pll and the fast stuff in reset when you don''t need it
> Some function needs special speed. For example, usb needs 48MHz exactly. Others need higher speed just for speed and lower speed for power savings.

so what is the question?

On Monday, July 5, 2021 at 10:08:07 AM UTC-7, lang...@fonz.dk wrote:
> mandag den 5. juli 2021 kl. 19.05.27 UTC+2 skrev Ed Lee: 
> > On Monday, July 5, 2021 at 9:49:43 AM UTC-7, lang...@fonz.dk wrote: 
> > > mandag den 5. juli 2021 kl. 18.16.25 UTC+2 skrev Ed Lee: 
> > > > On Monday, July 5, 2021 at 8:51:20 AM UTC-7, gnuarm.del...@gmail.com wrote: 
> > > > > On Monday, July 5, 2021 at 11:24:12 AM UTC-4, Ed Lee wrote: 
> > > > > > On Monday, July 5, 2021 at 6:23:38 AM UTC-7, gnuarm.del...@gmail.com wrote: 
> > > > > > > On Monday, July 5, 2021 at 12:01:26 AM UTC-4, Ed Lee wrote: 
> > > > > > > > OK, i am asking you a very simply question. How do you change the clock speed on the fly for the FPGA. It's a simple write to registers in micro. 
> > > > > > > However you wish. The circuit is yours to design. How would you like it to work? 
> > > > > > > 
> > > > > > > I like the fact that you keep talking about a "simple write to registers" as if you were programming a sequential processor with a linear address space like an MCU no matter what the device is. (I would also point out that the clocking controls are some of the most complex in any given MCU, so not often a "simple" register write). How would you adjust the clock speed in a discrete circuit design? An FPGA is just discrete logic inside a chip with programmable interconnects. Do you write to registers in analog designs too? 
> > > > > > > 
> > > > > > > I will repeat the problem. You continue to be stuck in the MCU mindset and are not willing to learn enough about FPGAs to actually understand them. You won't understand them until you stop pretending FPGAs are just different MCUs. Open your mind. Learn something. 
> > > > > > Not if you keep side-stepping the question. I ask a very simple and direct question: How do you reconfig the PLL from the chip within? 
> > > > > No side stepping. That was not the question you asked before. 
> > > > I asked you how to change the clock speed, which is driven by the PLL. It's the same question. And we, those who know nothing about FPGA, want you to tell us how to do that with the ICE40 FPGA you recommended. 
> > > > > Clock control is done using the logic resources inside the FPGA. If you are asking about programming the PLL, every device family is different. You can read about it in the data sheet for the clock distribution or some brands have a separate document just for the PLL. They tend to be more complex than a UART, so just listing the bits in registers doesn't explain it. I don't have any of this info memorized, so you will need to look at the docs yourself. 
> > > > I know how to do that from the Actel designer, but not from within the chip. If you want us to replace our micro with this ICE40 CPLD/FPGA, you should at least give us the link to do it. Otherwise, it's beyond our knowledge to attempt to use this CPLD/FPGA. 
> > > why would you want to change the clock? if you want lowpower standby, run the housekeeping a the slow clock, 
> > > keep the pll and the fast stuff in reset when you don''t need it 
> > Some function needs special speed. For example, usb needs 48MHz exactly. Others need higher speed just for speed and lower speed for power savings.
> so what is the question?

How do you change the PLL setting of the ICE40 FPGA, from the chip itself, not from an external programmer?

On Sunday, July 4, 2021 at 9:01:26 PM UTC-7, Ed Lee wrote:

> OK, i am asking you a very simply question. How do you change the clock speed on the fly for the FPGA. It's a simple write to registers in micro.

The classic method is pulse swallowing; small-scale integrated circuits with divide-by-ten/eleven were
a good example, and a gate array should have no difficulty implementing this.  It's just
a latched bit driving a mux of the divider's two outputs. 

<https://intochips.com/DHL612.pdf>  is a slightly more complex example.

It's hard to know what 'the' clock speed is, since a fixed clock drives the logic, and a variable clock drives
the output signal, of the digital PLL under discussion.

On Monday, July 5, 2021 at 10:34:43 AM UTC-7, whit3rd wrote:
> On Sunday, July 4, 2021 at 9:01:26 PM UTC-7, Ed Lee wrote: 
> 
> > OK, i am asking you a very simply question. How do you change the clock speed on the fly for the FPGA. It's a simple write to registers in micro.
> The classic method is pulse swallowing; small-scale integrated circuits with divide-by-ten/eleven were 
> a good example, and a gate array should have no difficulty implementing this. It's just 
> a latched bit driving a mux of the divider's two outputs. 
> 
> <https://intochips.com/DHL612.pdf> is a slightly more complex example. 
> 
> It's hard to know what 'the' clock speed is, since a fixed clock drives the logic, and a variable clock drives 
> the output signal, of the digital PLL under discussion.

And we want to know exactly how to config the PLL.  Otherwise, we can't use FPGA to replace micro as suggested.

On Monday, July 5, 2021 at 12:16:25 PM UTC-4, Ed Lee wrote:
> On Monday, July 5, 2021 at 8:51:20 AM UTC-7, gnuarm.del...@gmail.com wrote: 
> > On Monday, July 5, 2021 at 11:24:12 AM UTC-4, Ed Lee wrote: 
> > > On Monday, July 5, 2021 at 6:23:38 AM UTC-7, gnuarm.del...@gmail.com wrote: 
> > > > On Monday, July 5, 2021 at 12:01:26 AM UTC-4, Ed Lee wrote: 
> > > > > OK, i am asking you a very simply question. How do you change the clock speed on the fly for the FPGA. It's a simple write to registers in micro. 
> > > > However you wish. The circuit is yours to design. How would you like it to work? 
> > > > 
> > > > I like the fact that you keep talking about a "simple write to registers" as if you were programming a sequential processor with a linear address space like an MCU no matter what the device is. (I would also point out that the clocking controls are some of the most complex in any given MCU, so not often a "simple" register write). How would you adjust the clock speed in a discrete circuit design? An FPGA is just discrete logic inside a chip with programmable interconnects. Do you write to registers in analog designs too? 
> > > > 
> > > > I will repeat the problem. You continue to be stuck in the MCU mindset and are not willing to learn enough about FPGAs to actually understand them. You won't understand them until you stop pretending FPGAs are just different MCUs. Open your mind. Learn something. 
> > > Not if you keep side-stepping the question. I ask a very simple and direct question: How do you reconfig the PLL from the chip within? 
> > No side stepping. That was not the question you asked before.
> I asked you how to change the clock speed, which is driven by the PLL. It's the same question. And we, those who know nothing about FPGA, want you to tell us how to do that with the ICE40 FPGA you recommended.

Now you are just playing games.   I mentioned the iCE40 devices as being low power.  I don't get commission for selling the devices.  If you want to learn things you need to crack a book.  You aren't in elementary school anymore.  I've never designed with an iCE40 PLL, so I would have to do the same work as you to dig out the answer.  

But now that you have clearly stated the question, I would respond with why do you need to know that?  I've never had need to change the clock speed in a design.  I just enable and disable a clock to enter the low power state and run the logic in bursts... same as most people do on MCUs to reduce power.  Bill has said he doesn't even need to do that, so are you just asking for general knowledge?  


> > Clock control is done using the logic resources inside the FPGA. If you are asking about programming the PLL, every device family is different. You can read about it in the data sheet for the clock distribution or some brands have a separate document just for the PLL. They tend to be more complex than a UART, so just listing the bits in registers doesn't explain it. I don't have any of this info memorized, so you will need to look at the docs yourself.
> I know how to do that from the Actel designer, but not from within the chip. If you want us to replace our micro with this ICE40 CPLD/FPGA, you should at least give us the link to do it. Otherwise, it's beyond our knowledge to attempt to use this CPLD/FPGA.

I don't care what you do in your designs.  I'm just pointing out the FPGA PLL is as capable as an MCU with the exception that low power MCUs don't typically have clocks that run at hundreds of MHz because there is no point as the processor can't run that fast. 

Until now the thing preventing you from learning about FPGAs seemed to be that you didn't understand they are different from MCUs.  Now it seems to be that you are just being argumentative and don't really want to learn how to use them.  I suspect you also don't really get that FPGAs are not like MCUs.  

I don't  see the point in continuing this conversation.  You expect me to do all the work of teaching you by spoon feeding you.  That's your mama''s job, not mine.  

You were happy enough to read the data sheet to find the max speed which you got wrong and I had to correct you.  But now you've drawn a line and aren't willing to read further to learn about the PLL.  That's on you.  Sorry. 

-- 

Rick C.

+-++ Get 1,000 miles of free Supercharging
+-++ Tesla referral code - https://ts.la/richard11209

On Monday, July 5, 2021 at 12:42:37 PM UTC-4, lang...@fonz.dk wrote:
> mandag den 5. juli 2021 kl. 15.13.45 UTC+2 skrev gnuarm.del...@gmail.com: 
> > On Monday, July 5, 2021 at 1:13:28 AM UTC-4, Chris Jones wrote: 
> > > On 04/07/2021 01:01, Clive Arthur wrote: 
> > > > On 03/07/2021 14:30, Chris Jones wrote: 
> > > > 
> > > > <snip> 
> > > > 
> > > >> You could do it in an FPGA. Obviously you could put a CPU with UART in 
> > > >> the FPGA design, with the CPU running whatever code to make a menu you 
> > > >> would have put on a micro, (but with peripherals that do exactly 
> > > >> whatever fast logic you need, unlike those on most microcontrollers), 
> > > >> though there are much more efficient ways. 
> > > >> 
> > > >> There are for example logic analyzers that you can drop into your fpga 
> > > >> design, that connect to an external PC for debugging. This is much 
> > > >> better than some printf statements to a uart, as you can get timing 
> > > >> information about when things happen, that is much more accurate than 
> > > >> over a UART. I think most of the bugs are usually caught in simulation 
> > > >> so the need for debugging on the hardware may be rare anyway. 
> > > >> 
> > > > There are lots of timers. Timing information is garnered from them and 
> > > > printed (though not with printf). On occasion a spare I/O pin might 
> > > > trigger a scope. 
> > > I do that too in firmware, but it is not ideal. When you put in code to 
> > > trigger/capture the timers, the timing changes, so then you have to 
> > > leave all the debugging code in for production, or just hope that the 
> > > timing will still be right when you take it out. And if the compiler 
> > > gets upgraded, all bets are off. Perhaps you write in pure assembler so 
> > > you don't care about that. I would be less productive without a compiler. 
> > People talk as if coding an MCU is a piece of cake, mostly because this is what they are familiar with. The comfort factor is high even if they know there can be difficult to solve problems mostly having to do with the timing issues that result from sharing a sequential process between multiple, separate functions. In the most simple cases there are no real problems. In more difficult cases the problems can become quite complex. There are methods for managing these issues, but they are often not well understood or implemented. 
> >
> swap mcu and fpga and you do the same for the same reasons ....

I don't agree.  I learned to use MCUs proficiently long before I used FPGAs.  Even then I would have said MCUs were easier to use than FPGAs.  But now the tools have gotten better and I have learned proper techniques for simulating and debugging designs making FPGA designs easier to implement than MCU designs... for the size and complexity I typically implement.  I don't have experience with MCUs or FPGAs at integrating large functional blocks to implement SoC devices.  So I can't offer an opinion on those size designs.  That is not what we have been discussing.  

-- 

Rick C.

++-- Get 1,000 miles of free Supercharging
++-- Tesla referral code - https://ts.la/richard11209

On Monday, July 5, 2021 at 1:05:27 PM UTC-4, Ed Lee wrote:
> On Monday, July 5, 2021 at 9:49:43 AM UTC-7, lang...@fonz.dk wrote: 
> > mandag den 5. juli 2021 kl. 18.16.25 UTC+2 skrev Ed Lee: 
> > > On Monday, July 5, 2021 at 8:51:20 AM UTC-7, gnuarm.del...@gmail.com wrote: 
> > > > On Monday, July 5, 2021 at 11:24:12 AM UTC-4, Ed Lee wrote: 
> > > > > On Monday, July 5, 2021 at 6:23:38 AM UTC-7, gnuarm.del...@gmail.com wrote: 
> > > > > > On Monday, July 5, 2021 at 12:01:26 AM UTC-4, Ed Lee wrote: 
> > > > > > > OK, i am asking you a very simply question. How do you change the clock speed on the fly for the FPGA. It's a simple write to registers in micro. 
> > > > > > However you wish. The circuit is yours to design. How would you like it to work? 
> > > > > > 
> > > > > > I like the fact that you keep talking about a "simple write to registers" as if you were programming a sequential processor with a linear address space like an MCU no matter what the device is. (I would also point out that the clocking controls are some of the most complex in any given MCU, so not often a "simple" register write). How would you adjust the clock speed in a discrete circuit design? An FPGA is just discrete logic inside a chip with programmable interconnects. Do you write to registers in analog designs too? 
> > > > > > 
> > > > > > I will repeat the problem. You continue to be stuck in the MCU mindset and are not willing to learn enough about FPGAs to actually understand them. You won't understand them until you stop pretending FPGAs are just different MCUs. Open your mind. Learn something. 
> > > > > Not if you keep side-stepping the question. I ask a very simple and direct question: How do you reconfig the PLL from the chip within? 
> > > > No side stepping. That was not the question you asked before. 
> > > I asked you how to change the clock speed, which is driven by the PLL. It's the same question. And we, those who know nothing about FPGA, want you to tell us how to do that with the ICE40 FPGA you recommended. 
> > > > Clock control is done using the logic resources inside the FPGA. If you are asking about programming the PLL, every device family is different. You can read about it in the data sheet for the clock distribution or some brands have a separate document just for the PLL. They tend to be more complex than a UART, so just listing the bits in registers doesn't explain it. I don't have any of this info memorized, so you will need to look at the docs yourself. 
> > > I know how to do that from the Actel designer, but not from within the chip. If you want us to replace our micro with this ICE40 CPLD/FPGA, you should at least give us the link to do it. Otherwise, it's beyond our knowledge to attempt to use this CPLD/FPGA. 
> > why would you want to change the clock? if you want lowpower standby, run the housekeeping a the slow clock, 
> > keep the pll and the fast stuff in reset when you don''t need it
> Some function needs special speed. For example, usb needs 48MHz exactly. Others need higher speed just for speed and lower speed for power savings.

There are many ways to skin a cat, but I prefer to run everything in the design from one clock to reduce clock domain crossing issues.  So if 48 MHz was required, I would have perhaps a 96 MHz clock for faster stuff and run the USB logic with an enable at 48 MHz.  Then everything is on one clock other than the low power circuits. 

If the other clock has to be say, 100 MHz, then you use two fast clocks and must design clock domain crossing circuits for anything that goes between them.  It's not hard if you are willing to ask questions and learn.  If you just want to argue, I'll let you talk to someone else. 

-- 

Rick C.

++-+ Get 1,000 miles of free Supercharging
++-+ Tesla referral code - https://ts.la/richard11209