On Friday, June 28, 2019 at 8:11:36 AM UTC-4, George Herold wrote:> On Thursday, June 27, 2019 at 4:16:06 AM UTC-4, piglet wrote: > > On 27/06/2019 2:06 am, George Herold wrote: > > > On Wednesday, June 26, 2019 at 5:22:34 PM UTC-4, piglet wrote: > > >> On 26/06/2019 5:48 pm, Winfield Hill wrote: > > >>> Here's a TIA circuit published in 2012, in RSI, > > >>> by Yale physicist, Stephen Eckel. “A high dynamic > > >>> range, linear response transimpedance amplifier.” > > >>> > > >>> It's easy to implement, and super useful. The TIA > > >>> has multiple ranges, each with its own output, but > > >>> multiple ranges are active at once; there's no loss > > >>> of data as would happen switching range resistors. > > >>> > > >>> Stephen and his co-authors found a simple, clever > > >>> trick to prevent input TIA opamp saturation, using > > >>> JFETs to successively short series-placed higher- > > >>> value range resistors for strong input currents. > > >>> > > >>> They suggest a three-stage implementation, with a > > >>> 300:1 ratio for each, but you can use many stages > > >>> (each one takes few extra parts), to obtain high > > >>> accuracy with a say 12-bit ADC. Also, a high > > >>> input-opamp Vos needn't degrade the dynamic range. > > >>> > > >>> DropBox has a draft of our x-Chapters write-up: > > >>> https://www.dropbox.com/s/fs4edz7dqgwswoj/4x.3.7_Eckel_TIA.pdf?dl=0 > > >>> > > >>> I think you can download Stephen's RSI article here: > > >>> https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=8&ved=2ahUKEwjk6KvVwYfjAhVlRN8KHaMfD48QFjAHegQICRAC&url=http%3A%2F%2Fwww.bmo.physik.uni-muenchen.de%2F~riedle%2FElektronik_I%2FKW103%2F2012_Eckel%2CSushkov_9-decade_RSI.pdf&usg=AOvVaw3g9i6-pWAwuuZlZLvlFArd > > >>> > > >>> > > >> > > >> > > >> Marvellous - thank you! > > >> > > >> Jfets are nice because when fully depleted off there is no parasitic s-d > > >> diode that curses gumdrop mosfets. But gumdrop mosfets are much cheaper > > >> than jfets these days. I wonder if one could use series connected > > >> source-source 2N7002 and s-s BSS84 to replace those jfets? Eight mosfets > > >> could work out cheaper than four jfets? While gate leakage should be a > > >> non-issue I don't know how s-d channel leakage compares? > > >> > > >> piglet > > > > > > I was going to ask what about source-source fets, and found this, > > > https://electronics.stackexchange.com/questions/79028/understanding-two-mosfet-with-sources-connected > > > > > > Is that right... just looking at pics not reading comments/ words. > > > > > > George H. > > > > > > > Yes, here is sketch showing how might be done using mosfets to replace > > jfets: > > > > <https://www.dropbox.com/s/bidm47zj29moq6k/SteppedTIA.jpg?dl=0> > > > > piglet > > Thanks piglet. I didn't know that Jfet's have no S-D body diode. > (Why the heck is that? so much I don't know!) > > George H.So I was searching for a model of a jfet. Figure 1 here, http://www.linearsystems.com/lsdata/others/LIS_White_Paper_Consider_Discrete_JFET.pdf Is the gate and 'back gate' connected together? George H.
9-decade transimpedance amplifier
Started by ●June 26, 2019
Reply by ●June 28, 20192019-06-28
Reply by ●June 28, 20192019-06-28
On 28 Jun 2019 08:02:08 -0700, Winfield Hill <winfieldhill@yahoo.com> wrote:>George Herold wrote... >> >> Winfield Hill wrote: >>> George Herold wrote... >>>> >>>> We sell a PD with a 10 position switch, 1,3.3,10... >>>> It's OK, when I tried to make it faster I found >>>> the switch added ~5 pF of C. Otherwise I'm not >>>> sure what's wrong with a gain switch. >>> >>> Well, as I said, the Eckel scheme, with outputs >>> running simultaneously, insures fast, accurate >>> digitizing, especially with noisy signals. But >>> John's scheme looks very practical for separating >>> a high Rf first stage from a lower Rf second stage. >>> The first stage would not suffer from any extra >>> capacitances to slow it down. You could safely >>> add switches to the lower-gain stage to get lots >>> of ranges. I might use 10x for 1st to 2nd stage, >>> to insure speed, and do the 3.3x bit later. >> >> Thanks Win, I like the trick. I'm wondering what >> the application is, where having to switch ranges >> (with a switch) is a problem. > > A switch, with wiring to the panel, will add 1 to > 5pF across the feedback resistor. We often make > fast TIAs, with high f_T opamps, that make use of > the intrinsic 0.1pF capacitance of many resistors. > We go further, and trick the resistor into having > even less capacitance, see Figure 8.80-C. These > applications could use John's scheme to separate > the highest-gain stage from the rest.You can sometimes switch things around with low-capacitance diodes or phemts or even multiplexers, so rotary switch capacitance and wiring aren't in the circuit. The switch is cold, just DC. These Fujitsu relays are dynamite. https://www.dropbox.com/s/14mt8y78cc5ng79/Relays.jpg?raw=1 https://www.dropbox.com/s/se162xpw86hpmzs/DSC06884.JPG?raw=1 DPDT, fraction of a pF, fraction of an ohm, good to a few GHz. But don't water wash them. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●June 28, 20192019-06-28
In article <b549465b-526d-4394-bf23-84157436d2cd@googlegroups.com>, George Herold <gherold@teachspin.com> wrote:>So I was searching for a model of a jfet. >Figure 1 here, >http://www.linearsystems.com/lsdata/others/LIS_White_Paper_Consider_Discrete_JFET.pdf > >Is the gate and 'back gate' connected together?From https://www.nxp.com/docs/en/application-note/AN211A.pdf I see "The substrate, which functions as Gate 2 of Figure 1, is of relatively low resistivity material to maximize gain. For the same purpose, Gate 1 is of very low resistivity material, allowing the depletion region to spread mostly into the n-type channel. In most cases the gates are internally connected together. A tetrode device can be realized by not making this internal connection." I have a few surplus JFETs from Linear Integrated Systems which do have an active fourth lead - I believe it's the substrate (gate 2). If I recall correctly one can either tie the substrate to the gate, or to the source, or to a constant voltage which is more negative than the source (in the case of an N-JFET).
Reply by ●June 28, 20192019-06-28
On 28/06/2019 18:51, Dave Platt wrote:> In article <b549465b-526d-4394-bf23-84157436d2cd@googlegroups.com>, > George Herold <gherold@teachspin.com> wrote: >> So I was searching for a model of a jfet. >> Figure 1 here, >> http://www.linearsystems.com/lsdata/others/LIS_White_Paper_Consider_Discrete_JFET.pdf >> >> Is the gate and 'back gate' connected together? > > From https://www.nxp.com/docs/en/application-note/AN211A.pdf I see > > "The substrate, which functions as Gate 2 of Figure 1, is > of relatively low resistivity material to maximize gain. For the > same purpose, Gate 1 is of very low resistivity material, > allowing the depletion region to spread mostly into the n-type > channel. In most cases the gates are internally connected > together. A tetrode device can be realized by not making > this internal connection." > > I have a few surplus JFETs from Linear Integrated Systems which do > have an active fourth lead - I believe it's the substrate (gate 2). > If I recall correctly one can either tie the substrate to the gate, or > to the source, or to a constant voltage which is more negative than > the source (in the case of an N-JFET). > > > > >Having substrate access sounds like it could be useful - shame the jfets I use (J177, J113, J107, BF256 etc) only have three pins :( piglet
