I have a couple of simple 555 monostables, the first to delay the triggering of the second. https://www.dropbox.com/s/6uboy3fgd0ixhxa/GenerateNegPulse-1.jpg?raw=1 But I'm struggling to extract the brief -ve pulse required for the Main mono. I thought it would prove simple. But bread-boarding various combinations of R, C, diode and NPN or PNP transistor has so far not yielded a winning combination. All suggestions would be appreciated please. Terry, East Grinstead, UK
Generating this negative pulse?
Started by ●April 26, 2019
Reply by ●April 26, 20192019-04-26
On 26/04/2019 09:49, Terry Pinnell wrote:> I have a couple of simple 555 monostables, the first to delay the > triggering of the second. > https://www.dropbox.com/s/6uboy3fgd0ixhxa/GenerateNegPulse-1.jpg?raw=1 > > But I'm struggling to extract the brief -ve pulse required for the Main > mono. I thought it would prove simple. But bread-boarding various > combinations of R, C, diode and NPN or PNP transistor has so far not > yielded a winning combination. > > All suggestions would be appreciated please. > > Terry, East Grinstead, UKC on output going to R pulled up to supply. Possibly upwards pointing diode across R, but doubt that's needed. CMOS 555s I guess? Cheers -- Clive
Reply by ●April 26, 20192019-04-26
On 4/26/2019 1:49 AM, Terry Pinnell wrote:> I have a couple of simple 555 monostables, the first to delay the > triggering of the second. > https://www.dropbox.com/s/6uboy3fgd0ixhxa/GenerateNegPulse-1.jpg?raw=1 > > But I'm struggling to extract the brief -ve pulse required for the Main > mono. I thought it would prove simple. But bread-boarding various > combinations of R, C, diode and NPN or PNP transistor has so far not > yielded a winning combination. > > All suggestions would be appreciated please. > > Terry, East Grinstead, UK >A time axis might be helpful to know how critical the relative timing might be...how fast do you have to reset the timing components? How accurate/repeatable do the delay and pulse outputs have to be. Are the delay and width fixed? Or vary over what range? Have you tried an XOR gate with an RC on one input? If you wanna have some fun, consider the emitter follower. If you put a resistor in the base and drive current into the emitter, the emitter impedance looks like the base resistor in parallel with an inductor. The time constant of that LR is the Tsub-t of the transistor. I'm too sleepy to remember, but it's something like 1/2pi*ft. Works great as a fast differentiator. The cool part is that the L was never really there, so when you turn off the current, all you have to wait for is the charge in the base junction to dissipate. The width of the pulse is relatively independent of the rep rate.
Reply by ●April 26, 20192019-04-26
Clive Arthur <cliveta@nowaytoday.co.uk> wrote:>On 26/04/2019 09:49, Terry Pinnell wrote: >> I have a couple of simple 555 monostables, the first to delay the >> triggering of the second. >> https://www.dropbox.com/s/6uboy3fgd0ixhxa/GenerateNegPulse-1.jpg?raw=1 >> >> But I'm struggling to extract the brief -ve pulse required for the Main >> mono. I thought it would prove simple. But bread-boarding various >> combinations of R, C, diode and NPN or PNP transistor has so far not >> yielded a winning combination. >> >> All suggestions would be appreciated please. >> >> Terry, East Grinstead, UK > >C on output going to R pulled up to supply. Possibly upwards pointing >diode across R, but doubt that's needed. CMOS 555s I guess? > >CheersThanks Clive, appreciate that fast reply. Haven't bread-boarded it yet but simulation looks good. https://www.dropbox.com/s/dsnxzxm6pe4uo10/CreateNegEdge-1.png?raw=1 I rather think the diode is needed as I suspect the +ve pulse might cause trouble? Terry, East Grinstead, UK
Reply by ●April 26, 20192019-04-26
Mike <ham789@netscape.net> wrote:>On 4/26/2019 1:49 AM, Terry Pinnell wrote: >> I have a couple of simple 555 monostables, the first to delay the >> triggering of the second. >> https://www.dropbox.com/s/6uboy3fgd0ixhxa/GenerateNegPulse-1.jpg?raw=1 >> >> But I'm struggling to extract the brief -ve pulse required for the Main >> mono. I thought it would prove simple. But bread-boarding various >> combinations of R, C, diode and NPN or PNP transistor has so far not >> yielded a winning combination. >> >> All suggestions would be appreciated please. >> >> Terry, East Grinstead, UK >> >A time axis might be helpful to know how critical the relative timing >might be...how fast do you have to reset the timing components? >How accurate/repeatable do the delay and pulse outputs have to be. >Are the delay and width fixed? Or vary over what range? > >Have you tried an XOR gate with an RC on one input? > >If you wanna have some fun, consider the emitter follower. >If you put a resistor in the base and drive current into the emitter, >the emitter impedance looks like the base resistor in parallel with an >inductor. >The time constant of that LR is the Tsub-t of the transistor. I'm too >sleepy >to remember, but it's something like 1/2pi*ft. >Works great as a fast differentiator. >The cool part is that the L was never really there, so when you >turn off the current, all you have to wait for is the charge in the >base junction to dissipate. The width of the pulse is relatively >independent >of the rep rate.Thanks Mike. I'll experiment with that later but Clive's ultra-simple suggestion looks good! Terry, East Grinstead, UK
Reply by ●April 26, 20192019-04-26
Mike <ham789@netscape.net> wrote:>On 4/26/2019 1:49 AM, Terry Pinnell wrote: >> I have a couple of simple 555 monostables, the first to delay the >> triggering of the second. >> https://www.dropbox.com/s/6uboy3fgd0ixhxa/GenerateNegPulse-1.jpg?raw=1 >> >> But I'm struggling to extract the brief -ve pulse required for the Main >> mono. I thought it would prove simple. But bread-boarding various >> combinations of R, C, diode and NPN or PNP transistor has so far not >> yielded a winning combination. >> >> All suggestions would be appreciated please. >> >> Terry, East Grinstead, UK >> >A time axis might be helpful to know how critical the relative timing >might be...how fast do you have to reset the timing components? >How accurate/repeatable do the delay and pulse outputs have to be. >Are the delay and width fixed? Or vary over what range? > >Have you tried an XOR gate with an RC on one input? > >If you wanna have some fun, consider the emitter follower. >If you put a resistor in the base and drive current into the emitter, >the emitter impedance looks like the base resistor in parallel with an >inductor. >The time constant of that LR is the Tsub-t of the transistor. I'm too >sleepy >to remember, but it's something like 1/2pi*ft. >Works great as a fast differentiator. >The cool part is that the L was never really there, so when you >turn off the current, all you have to wait for is the charge in the >base junction to dissipate. The width of the pulse is relatively >independent >of the rep rate.Also meant to also reply to your questions about the time scale. Initial delay mono trigger pulse not critical, but typically 100 ms. Delay mono output user-settable between 1 and 30 s. Main mono user-settable between 5s and 7 mins. I've amended my illustration accordingly. Nothing deserving much rigour, it's just hobby stuff. I'm using main mono to light an external lamp as part of my project to get video of an occasional overnight garden visit by a local fox and cub. Terry, East Grinstead, UK
Reply by ●April 26, 20192019-04-26
On 26/04/2019 11:39, Terry Pinnell wrote:> Clive Arthur <cliveta@nowaytoday.co.uk> wrote: > >> On 26/04/2019 09:49, Terry Pinnell wrote: >>> I have a couple of simple 555 monostables, the first to delay the >>> triggering of the second. >>> https://www.dropbox.com/s/6uboy3fgd0ixhxa/GenerateNegPulse-1.jpg?raw=1 >>> >>> But I'm struggling to extract the brief -ve pulse required for the Main >>> mono. I thought it would prove simple. But bread-boarding various >>> combinations of R, C, diode and NPN or PNP transistor has so far not >>> yielded a winning combination. >>> >>> All suggestions would be appreciated please. >>> >>> Terry, East Grinstead, UK >> >> C on output going to R pulled up to supply. Possibly upwards pointing >> diode across R, but doubt that's needed. CMOS 555s I guess? >> >> Cheers > > Thanks Clive, appreciate that fast reply. Haven't bread-boarded it yet > but simulation looks good. > https://www.dropbox.com/s/dsnxzxm6pe4uo10/CreateNegEdge-1.png?raw=1 > > I rather think the diode is needed as I suspect the +ve pulse might > cause trouble? > > Terry, East Grinstead, UKIt's likely that the 555 input will have a protection diode, but I haven't looked, that's just a guess, so yes, use one. A Schottky diode would keep the pulse down to maybe 300mV above rail. Cheers -- Clive
Reply by ●April 26, 20192019-04-26
On 4/26/19 4:49 AM, Terry Pinnell wrote:> I have a couple of simple 555 monostables, the first to delay the > triggering of the second. > https://www.dropbox.com/s/6uboy3fgd0ixhxa/GenerateNegPulse-1.jpg?raw=1 > > But I'm struggling to extract the brief -ve pulse required for the Main > mono. I thought it would prove simple. But bread-boarding various > combinations of R, C, diode and NPN or PNP transistor has so far not > yielded a winning combination. > > All suggestions would be appreciated please. > > Terry, East Grinstead, UK >One method would be a couple of NAND gates and an RC, forming a "half monostable". 0-*-------RRRR-------*-----------N * | A___________0 | CCC N | CCC *-----D | | | | GND | | | *------N | | A-----------------* | N *------D When the input is sitting high, the second NAND sees 10 so it stays high. When the input goes low, initially the the second NAND sees 11, so its output goes LOW. The RC charges up to the logic threshold, at which point the second NAND sees 01 and brings its output high. A Schmitt-trigger NAND such as a 74HC132 or 4093 would be best. An RC and an XOR will generate pulses on both edges of its input. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net https://hobbs-eo.com
Reply by ●April 26, 20192019-04-26
Clive Arthur <cliveta@nowaytoday.co.uk> wrote:>On 26/04/2019 11:39, Terry Pinnell wrote: >> Clive Arthur <cliveta@nowaytoday.co.uk> wrote: >> >>> On 26/04/2019 09:49, Terry Pinnell wrote: >>>> I have a couple of simple 555 monostables, the first to delay the >>>> triggering of the second. >>>> https://www.dropbox.com/s/6uboy3fgd0ixhxa/GenerateNegPulse-1.jpg?raw=1 >>>> >>>> But I'm struggling to extract the brief -ve pulse required for the Main >>>> mono. I thought it would prove simple. But bread-boarding various >>>> combinations of R, C, diode and NPN or PNP transistor has so far not >>>> yielded a winning combination. >>>> >>>> All suggestions would be appreciated please. >>>> >>>> Terry, East Grinstead, UK >>> >>> C on output going to R pulled up to supply. Possibly upwards pointing >>> diode across R, but doubt that's needed. CMOS 555s I guess? >>> >>> Cheers >> >> Thanks Clive, appreciate that fast reply. Haven't bread-boarded it yet >> but simulation looks good. >> https://www.dropbox.com/s/dsnxzxm6pe4uo10/CreateNegEdge-1.png?raw=1 >> >> I rather think the diode is needed as I suspect the +ve pulse might >> cause trouble? >> >> Terry, East Grinstead, UK > >It's likely that the 555 input will have a protection diode, but I >haven't looked, that's just a guess, so yes, use one. A Schottky diode >would keep the pulse down to maybe 300mV above rail. > >CheersOn similarly minimalist lines, I'll test if this also works in practice.: https://www.dropbox.com/s/xbzl8mp8w66yb9r/CreateNegEdge-3.jpg?raw=1 (BTW, this old batch of 555s are not CMOS.) Terry, East Grinstead, UK
Reply by ●April 26, 20192019-04-26
Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:>On 4/26/19 4:49 AM, Terry Pinnell wrote: >> I have a couple of simple 555 monostables, the first to delay the >> triggering of the second. >> https://www.dropbox.com/s/6uboy3fgd0ixhxa/GenerateNegPulse-1.jpg?raw=1 >> >> But I'm struggling to extract the brief -ve pulse required for the Main >> mono. I thought it would prove simple. But bread-boarding various >> combinations of R, C, diode and NPN or PNP transistor has so far not >> yielded a winning combination. >> >> All suggestions would be appreciated please. >> >> Terry, East Grinstead, UK >> > >One method would be a couple of NAND gates and an RC, forming a "half >monostable". > > > > >0-*-------RRRR-------*-----------N > * | A___________0 > | CCC N > | CCC *-----D > | | | > | GND | > | | > *------N | > | A-----------------* > | N > *------D > >When the input is sitting high, the second NAND sees 10 so it stays high. > >When the input goes low, initially the the second NAND sees 11, so its >output goes LOW. The RC charges up to the logic threshold, at which >point the second NAND sees 01 and brings its output high. > >A Schmitt-trigger NAND such as a 74HC132 or 4093 would be best. > >An RC and an XOR will generate pulses on both edges of its input. > >Cheers >Thanks Phil, neat, I'll get around to trying it, but see my earlier reply to Mike. Terry, East Grinstead, UK
