On Wed, 13 Mar 2019 07:22:58 -0700, John Larkin wrote:> On Wed, 13 Mar 2019 10:05:12 -0000 (UTC), Jasen Betts <jasen@xnet.co.nz> > wrote: > >>On 2019-03-12, John Larkin <jjlarkin@highland_snip_technology.com> >>wrote: >>> On Tue, 12 Mar 2019 21:34:53 -0000 (UTC), Jasen Betts >>><jasen@xnet.co.nz> wrote: >>> >>>>On 2019-03-12, John Larkin <jjlarkin@highlandtechnology.com> wrote: >>>>> On Tue, 12 Mar 2019 06:44:15 -0000 (UTC), Jasen Betts >>>>><jasen@xnet.co.nz> wrote: >>>>> >>>>>>On 2019-03-11, John Larkin <jjlarkin@highlandtechnology.com> wrote: >>>>>>> On Mon, 11 Mar 2019 07:06:59 -0000 (UTC), Jasen Betts >>>>>>><jasen@xnet.co.nz> wrote: >>>>>>> >>>>>>>>On 2019-03-10, John Larkin <jjlarkin@highland_snip_technology.com> >>>>>>>>wrote: >>>>>>>>> On Sun, 10 Mar 2019 14:33:41 -0700, John Larkin >>>>>>>>><jjlarkin@highland_snip_technology.com> wrote: >>>>>>>>> >>>>>>>>>>On Sat, 9 Mar 2019 02:41:08 -0000 (UTC), Jasen Betts >>>>>>>>>><jasen@xnet.co.nz> wrote: >>>>>>>>>> >>>>>>>>>>>On 2019-03-08, John Larkin >>>>>>>>>>><jjlarkin@highland_snip_technology.com> wrote: >>>>>>>>>>>> On Fri, 8 Mar 2019 19:25:28 -0000, "Kevin Aylward" >>>>>>>>>>>><kevinRemovAT@kevinaylward.co.uk> wrote: >>>>>>>>>>>> >>>>>>>>>>>>>"John Larkin" wrote in message >>>>>>>>>>>>>news:an658epspab4p9b433lbtca3uno7a2ku8h@4ax.com... >>>>>>>>>>>>> >>>>>>>>>>>>>On Fri, 8 Mar 2019 16:13:29 -0000, "Kevin Aylward" >>>>>>>>>>>>><kevinRemovAT@kevinaylward.co.uk> wrote: >>>>>>>>>>>>> >>>>>>>>>>>>>>"John Larkin" wrote in message >>>>>>>>>>>>>>news:jkvt7e1mu51gueopgk7lodptq5imp5vjru@4ax.com... >>>>>>>>>>>>>> >>>>>>>>>>>>>> >>>>>>>>>>>>>>>>I have attached a simple sim showing the frequency error >>>>>>>>>>>>>>>>is unmeasurable when you set the tank ESR to zero. Let it >>>>>>>>>>>>>>>>run for 1,000 cycles. After 1,000 cycles, the tank voltage >>>>>>>>>>>>>>>>and sine wave overlap exactly. The frequency difference is >>>>>>>>>>>>>>>>too small to measure. >>>>>>>>>>>>>> >>>>>>>>>>>>>>>>Maybe so, but I often have to force the time step down to >>>>>>>>>>>>>>>>get a useful simulation. And that sometimes makes >>>>>>>>>>>>>>>>simulation times silly. There is a reason that the max >>>>>>>>>>>>>>>>time step can be set. When precision matters, I reduce it >>>>>>>>>>>>>>>>until the sim doesn't change. >>>>>>>>>>>>>> >>>>>>>>>>>>>>>>Make a pure, 1 volt, 1 Hz sine wave V source. Run that for >>>>>>>>>>>>>>>>5 seconds and zoom the top of the sine. It's chunky line >>>>>>>>>>>>>>>>segments. Change the time step to 1 us and it looks a lot >>>>>>>>>>>>>>>>better. >>>>>>>>>>>>>> >>>>>>>>>>>>>>>I am going to guess that you must be using LTSpice with >>>>>>>>>>>>>>>compression on. >>>>>>>>>>>>> >>>>>>>>>>>>>>Right, that is the default. >>>>>>>>>>>>> >>>>>>>>>>>>>My advice is to never use compression. Its a solution looking >>>>>>>>>>>>>for a problem. >>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>>-- Kevin Aylward http://www.anasoft.co.uk - SuperSpice >>>>>>>>>>>>>http://www.kevinaylward.co.uk/ee/index.html >>>>>>>>>>>> >>>>>>>>>>>> The point I was making, somewhere far above, is that the LT >>>>>>>>>>>> Spice defaults seem to go for speed. That usually works fine >>>>>>>>>>>> for things like opamp circuits, but sometimes doesn't. >>>>>>>>>>>> >>>>>>>>>>>> Things with a huge range of time constants are nasty. >>>>>>>>>>>> >>>>>>>>>>>> I wonder how it handles time steps when I specify a pulse >>>>>>>>>>>> generator with fast rise and fall times, maybe driving a slow >>>>>>>>>>>> RC or something. >>>>>>>>>>>> >>>>>>>>>>>> Or transmission lines? How many time buckets inside a >>>>>>>>>>>> transmission line? One txline can theoretically store an >>>>>>>>>>>> unlimited amount of information. >>>>>>>>>>> >>>>>>>>>>>Ltspice probably just looks at the simulated signal at the >>>>>>>>>>>other end of the lines at the apropriate time in the past. it >>>>>>>>>>>doesn't need separate storage for the line. >>>>>>>>>> >>>>>>>>>>That works for the lossless line, but data is only saved at >>>>>>>>>>time-step times of the overall circuit. >>>>>>>>>> >>>>>>>>>>The lossy line model has stuff happening all along the line, so >>>>>>>>>>can't just look back in time at the input. I wonder how many >>>>>>>>>>effective segments Spice chops up a line into, and whether the >>>>>>>>>>time step matters there. >>>>>>>>>> >>>>>>>>>>I might do some experiments. >>>>>>>>> >>>>>>>>> More fun: seriously mis-terminate a line and poke a pulse into >>>>>>>>> one end. After a while there will be a mess of reflections, >>>>>>>>> maybe of various polarities, things sloshing back and forth. >>>>>>>>> There's no "black box" way to simulate that; you'd need a lot of >>>>>>>>> internal nodes. >>>>>>>> >>>>>>>>Sure there is, the current pulse that was not conducted out of the >>>>>>>>line at the unterminated end is the history of that end node as an >>>>>>>>input at that end of the line, that gets replayed back to the >>>>>>>>source end. >>>>>>> >>>>>>> You could do that; Spice can't. Spice simulates circuits; it >>>>>>> doesn't understand them. >>>>>> >>>>>>It doesn't need to understand it. >>>>>> >>>>>>The current (and voltage) into the first end appears at the second >>>>>>end after the line's delay any of that current that doesn't flow >>>>>>into the attached circuit will be as current input to the second end >>>>>>and eventualy appear at the first end. >>>>> >>>>> Multiple reflections complicate that endlessly. >>>> >>>>they only complicate the signal. not the algorithm >>>> >>>>>>> There's still the issue of the lossy line. It needs internal >>>>>>> nodes. >>>>>> >>>>>>why? is it dispersive? >>>>> >>>>> Lossy and dispersive. >>>> >>>>how do I do a lossy line in ltspice? >>> >>> ltline is a component. >>> >>> >>It wants some stuff that I don't know how to write before I can run a >>simulation. > > Look up "telegraphers equation" to get the general idea. You've got to > build the txline out of Rs and Ls and Cs. I used to do that myself; I > wrote a Basic program to make a netlist for a lossy line for ECA. The > number of sections explodes as the square of Td/Tr or something nasty > like that. Sim times were bad for 1000 sections running on an 8086.Sometime last century I made a physical one with 120 sections for testing HDSL modems I was working on. It modelled 3.7km of 0.4mm twisted pair, and was good to about 500kHz. I actually posted about it in s.e.d: https://groups.google.com/d/msg/sci.electronics.design/uvkEtEJgDwM/ 8LuNcWHCm6MJ Regards, Allan
SPICE tarnsient analysis of oscillators - sampling time
Started by ●March 5, 2019
Reply by ●March 14, 20192019-03-14
Reply by ●March 14, 20192019-03-14
On Thu, 14 Mar 2019 05:09:37 -0000 (UTC), Jasen Betts <jasen@xnet.co.nz> wrote:>On 2019-03-13, John Larkin <jjlarkin@highlandtechnology.com> wrote: >> On Wed, 13 Mar 2019 10:05:12 -0000 (UTC), Jasen Betts >><jasen@xnet.co.nz> wrote: >> >>>On 2019-03-12, John Larkin <jjlarkin@highland_snip_technology.com> wrote: >>>> On Tue, 12 Mar 2019 21:34:53 -0000 (UTC), Jasen Betts >>>><jasen@xnet.co.nz> wrote: >>>> >>>> ltline is a component. >>>> >>> >>>It wants some stuff that I don't know how to write before I can run a >>>simulation. >> >> Look up "telegraphers equation" to get the general idea. You've got to >> build the txline out of Rs and Ls and Cs. I used to do that myself; I >> wrote a Basic program to make a netlist for a lossy line for ECA. The >> number of sections explodes as the square of Td/Tr or something nasty >> like that. Sim times were bad for 1000 sections running on an 8086. > >Cool, that explains L,C,R, and G but where do I put the numbers?Go to the LT Spice HELP and look for O. Lossy line Try this: Version 4 SHEET 1 904 680 WIRE -80 96 -128 96 WIRE -48 96 -80 96 WIRE 80 96 32 96 WIRE 160 96 80 96 WIRE 368 96 256 96 WIRE 432 96 368 96 WIRE -128 128 -128 96 WIRE 160 128 112 128 WIRE 288 128 256 128 WIRE 432 128 432 96 WIRE 112 160 112 128 WIRE 288 160 288 128 WIRE -128 240 -128 208 WIRE 432 240 432 208 FLAG 112 160 0 FLAG 288 160 0 FLAG -128 240 0 FLAG 432 240 0 FLAG -80 96 GEN FLAG 80 96 TDR FLAG 368 96 END SYMBOL ltline 208 112 R0 WINDOW 0 -4 -75 Bottom 2 WINDOW 3 -5 -68 Top 2 SYMATTR InstName O1 SYMATTR Value LTR50 SYMBOL voltage -128 112 R0 WINDOW 0 48 73 Left 2 WINDOW 3 33 116 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value PULSE(0 1 1n) SYMBOL res 48 80 R90 WINDOW 0 -45 54 VBottom 2 WINDOW 3 -37 53 VTop 2 SYMATTR InstName R1 SYMATTR Value 50 SYMBOL res 416 112 R0 WINDOW 0 53 42 Left 2 WINDOW 3 52 75 Left 2 SYMATTR InstName R2 SYMATTR Value 100 TEXT -96 288 Left 2 !.model LTR50 LTRA(len=10 R=5 L=2.3u C=1n) TEXT 152 224 Left 2 !.tran 10u TEXT 576 128 Left 2 ;TDR of 50 ohm lossy line TEXT 624 168 Left 2 ;DCR = 50 ohms TEXT 640 216 Left 2 ;Td = 470 ns TEXT 616 264 Left 2 ;JL Mar 26, 2017 -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●March 16, 20192019-03-16
On 3/10/19 5:33 PM, John Larkin wrote:> On Sat, 9 Mar 2019 02:41:08 -0000 (UTC), Jasen Betts > <jasen@xnet.co.nz> wrote: > >> On 2019-03-08, John Larkin <jjlarkin@highland_snip_technology.com> wrote: >>> On Fri, 8 Mar 2019 19:25:28 -0000, "Kevin Aylward" >>> <kevinRemovAT@kevinaylward.co.uk> wrote: >>> >>>> "John Larkin" wrote in message >>>> news:an658epspab4p9b433lbtca3uno7a2ku8h@4ax.com... >>>> >>>> On Fri, 8 Mar 2019 16:13:29 -0000, "Kevin Aylward" >>>> <kevinRemovAT@kevinaylward.co.uk> wrote: >>>> >>>>> "John Larkin" wrote in message >>>>> news:jkvt7e1mu51gueopgk7lodptq5imp5vjru@4ax.com... >>>>> >>>>> >>>>>>> I have attached a simple sim showing the frequency error is unmeasurable >>>>>>> when you set the tank ESR to zero. Let it run for 1,000 cycles. After >>>>>>> 1,000 >>>>>>> cycles, the tank voltage and sine wave overlap exactly. The frequency >>>>>>> difference is too small to measure. >>>>> >>>>>>> Maybe so, but I often have to force the time step down to get a useful >>>>>>> simulation. And that sometimes makes simulation times silly. There is >>>>>>> a reason that the max time step can be set. When precision matters, I >>>>>>> reduce it until the sim doesn't change. >>>>> >>>>>>> Make a pure, 1 volt, 1 Hz sine wave V source. Run that for 5 seconds >>>>>>> and zoom the top of the sine. It's chunky line segments. Change the >>>>>>> time step to 1 us and it looks a lot better. >>>>> >>>>>> I am going to guess that you must be using LTSpice with compression on. >>>> >>>>> Right, that is the default. >>>> >>>> My advice is to never use compression. Its a solution looking for a problem. >>>> >>>> >>>> -- Kevin Aylward >>>> http://www.anasoft.co.uk - SuperSpice >>>> http://www.kevinaylward.co.uk/ee/index.html >>> >>> The point I was making, somewhere far above, is that the LT Spice >>> defaults seem to go for speed. That usually works fine for things like >>> opamp circuits, but sometimes doesn't. >>> >>> Things with a huge range of time constants are nasty. >>> >>> I wonder how it handles time steps when I specify a pulse generator >>> with fast rise and fall times, maybe driving a slow RC or something. >>> >>> Or transmission lines? How many time buckets inside a transmission >>> line? One txline can theoretically store an unlimited amount of >>> information. >> >> Ltspice probably just looks at the simulated signal at the other end of the >> lines at the apropriate time in the past. it doesn't need separate storage for >> the line. > > That works for the lossless line, but data is only saved at time-step > times of the overall circuit. > > The lossy line model has stuff happening all along the line, so can't > just look back in time at the input. I wonder how many effective > segments Spice chops up a line into, and whether the time step matters > there. > > I might do some experiments. > >It may use an integral equation for that bit. Chopping the TL up into short sections isn't an efficient solving method. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Reply by ●March 16, 20192019-03-16
On 3/10/19 5:40 PM, John Larkin wrote:> On Sun, 10 Mar 2019 14:33:41 -0700, John Larkin > <jjlarkin@highland_snip_technology.com> wrote: > >> On Sat, 9 Mar 2019 02:41:08 -0000 (UTC), Jasen Betts >> <jasen@xnet.co.nz> wrote: >> >>> On 2019-03-08, John Larkin <jjlarkin@highland_snip_technology.com> wrote: >>>> On Fri, 8 Mar 2019 19:25:28 -0000, "Kevin Aylward" >>>> <kevinRemovAT@kevinaylward.co.uk> wrote: >>>> >>>>> "John Larkin" wrote in message >>>>> news:an658epspab4p9b433lbtca3uno7a2ku8h@4ax.com... >>>>> >>>>> On Fri, 8 Mar 2019 16:13:29 -0000, "Kevin Aylward" >>>>> <kevinRemovAT@kevinaylward.co.uk> wrote: >>>>> >>>>>> "John Larkin" wrote in message >>>>>> news:jkvt7e1mu51gueopgk7lodptq5imp5vjru@4ax.com... >>>>>> >>>>>> >>>>>>>> I have attached a simple sim showing the frequency error is unmeasurable >>>>>>>> when you set the tank ESR to zero. Let it run for 1,000 cycles. After >>>>>>>> 1,000 >>>>>>>> cycles, the tank voltage and sine wave overlap exactly. The frequency >>>>>>>> difference is too small to measure. >>>>>> >>>>>>>> Maybe so, but I often have to force the time step down to get a useful >>>>>>>> simulation. And that sometimes makes simulation times silly. There is >>>>>>>> a reason that the max time step can be set. When precision matters, I >>>>>>>> reduce it until the sim doesn't change. >>>>>> >>>>>>>> Make a pure, 1 volt, 1 Hz sine wave V source. Run that for 5 seconds >>>>>>>> and zoom the top of the sine. It's chunky line segments. Change the >>>>>>>> time step to 1 us and it looks a lot better. >>>>>> >>>>>>> I am going to guess that you must be using LTSpice with compression on. >>>>> >>>>>> Right, that is the default. >>>>> >>>>> My advice is to never use compression. Its a solution looking for a problem. >>>>> >>>>> >>>>> -- Kevin Aylward >>>>> http://www.anasoft.co.uk - SuperSpice >>>>> http://www.kevinaylward.co.uk/ee/index.html >>>> >>>> The point I was making, somewhere far above, is that the LT Spice >>>> defaults seem to go for speed. That usually works fine for things like >>>> opamp circuits, but sometimes doesn't. >>>> >>>> Things with a huge range of time constants are nasty. >>>> >>>> I wonder how it handles time steps when I specify a pulse generator >>>> with fast rise and fall times, maybe driving a slow RC or something. >>>> >>>> Or transmission lines? How many time buckets inside a transmission >>>> line? One txline can theoretically store an unlimited amount of >>>> information. >>> >>> Ltspice probably just looks at the simulated signal at the other end of the >>> lines at the apropriate time in the past. it doesn't need separate storage for >>> the line. >> >> That works for the lossless line, but data is only saved at time-step >> times of the overall circuit. >> >> The lossy line model has stuff happening all along the line, so can't >> just look back in time at the input. I wonder how many effective >> segments Spice chops up a line into, and whether the time step matters >> there. >> >> I might do some experiments. > > > More fun: seriously mis-terminate a line and poke a pulse into one > end. After a while there will be a mess of reflections, maybe of > various polarities, things sloshing back and forth. There's no "black > box" way to simulate that; you'd need a lot of internal nodes.I do that with real coax a fair amount. It's good for generating odd pulse trains and so on. with quite decent timing. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
