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Does the noise density function increase if an OpAmp goes into slew rate limit?

Started by RobertMacy May 28, 2014
On Fri, 06 Jun 2014 16:49:47 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

>On Fri, 06 Jun 2014 18:59:00 -0400, krw@attt.bizz wrote: > >>On Fri, 06 Jun 2014 12:31:28 -0700, Jim Thompson >><To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote: >[snip] >>> >>>Lot of nay-sayers here, but I've not had a chip come out of foundry in >>>many years that didn't perfectly match the simulations. >> >>Oh, good grief! You're talking apples and orangutans. Foundry models >>are very good. They have to be or the foundry has no customers. OTOH, >>board-level models invariably suck. Some are good enough to show you >>that something you know works, works. I've seen none that work even >>in corner (or basket) case situations. It's rare to see one that even >>models the power supply. >> >[snip] > >You're late to the discussion... as usual >:-}
I work for a living. You should try it sometime.
On Fri, 06 Jun 2014 09:37:00 -0700, Jim Thompson  
<To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote:

>> ...snip.... > The question is... How do you _see_ this noise in a transient > analysis? > > ...Jim Thompson
I enhance things a bit to make the circuit capable of producing the results. Plus, what I do in no way changes the .ac or .noise analysis, and I can switch it off to allow a 'normal' .tran analysis. Thus completely backward compatible. With it 'ON', I can then perform the .tran analysis, upon completion you simply probe the circuit just like normal, click on any node, or differential voltage, and the waveform has the realistic noise in it. The resulting time traces really 'look' like a scope trace. The OpAmp's output has that 'meander' caused by 1/f contribution. Turns the process into a 'real' circuit simulation, like working with a 'real' breadboard. Especially useful to see what nonlinear circuitry does with the noise. Has been educational in many ways. Especially, when you get into the nonlinear mixer/multiplier circuitry. While investigating closed loop gain, you also get 'birdies on a wire' those little bursts that look like oscillation, depending on the OpAmp's operating point at some extreme as the loop gain goes weird and stability goes nuts. In other words, the 'noise' appears as 'fuzz' on the time waveform and the signal looks just like a scope trace, and in spectrum analyzer mode, FFT, the noise yields a legitmate noise floor. As mnemonic that this is transient AND noise analyses combined, I started calling it .tranoise analysis and has much the same syntax as .tran. Right now it is not a super fast analysis. Takes quite a few data points. Do you have a use for this as you produce models for your clients? It would be great to be so forward thinking that your models are capable of accurately representing the component's "real" performance. All we need do is correctly make the model *and* slightly modify LTspice and PSpice to be compatible and we're off and running at taking circuit simulation to a new level. I'll send you some plots to show the comparison. I don't have anyway to post for people here though. Perhaps, you can post on your website and provide links for people here.
>wrote in message news:glh4p9taibv0arc22mour08k42rhp718oj@4ax.com...
>Lot of nay-sayers here, but I've not had a chip come out of foundry in >many years that didn't perfectly match the simulations.
>Oh, good grief! You're talking apples and orangutans. Foundry models >are very good. They have to be or the foundry has no customers. OTOH, >board-level models invariably suck. Some are good enough to show you >that something you know works, works. I've seen none that work even >in corner (or basket) case situations. It's rare to see one that even >models the power supply.
Sure, most vendor macro models are only functional behavioural models. You could try making your own from the data sheet though. Kevin Aylward B.Sc. www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
"Jim Thompson"  wrote in message 
news:id54p9592rafpno41qgr5ktbh97t86did5@4ax.com...


>>for sure. Unless I'm very much mistaken, it would be a lot faster and >>cheaper to make a couple of boards and have a look. > >>Spice and Spice model based simulations at the device level, are pretty >>much, engineering perfect, even for non-linear noise effects. It cost >>money >>though. > >>Just this last week I have yet another asic come back where the >>simulations >of phase noise for a complicated oscillator system come nuts on. Its >Spectre >>R.F PSS Noise, but it still uses the same spice BSim3 and VBIC models used >>in Spice. This Software deals with all the complicated interaction of >>mixing >>up 1/f noise, non-linear buffer stages and VCF modulation and gets within >>a >>db or so over the range of -60 dBc to -170 dBc phase noise, due to device >>noise. Its actually stunning that the right mathematics means that chips >>can >>be designed first time correctly purely in the virtual world. Its just a >>fact. Simulations work, and its faster and cheaper than spinning test >>chips >:-)
>Lot of nay-sayers here, but I've not had a chip come out of foundry in >many years that didn't perfectly match the simulations.
Of course, sometimes one misses doing a simulation or two... Sometimes you have to modify the kit setup though. Fabs are clueless as to what an analog design requires. I have had fabs tie the pnp and npn models together for weak, nominal and strong so had to have them split to independently be able to do 4 strong/weak corners of npn/pnp X4 corners of nmos/pmos X vps corners X temp corners etc. The current Cadence corner-parameter sweep setups are really good. Unlimited combinations, with multiple setups. Kevin Aylward B.Sc. www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
On Sat, 7 Jun 2014 07:25:20 +0100, "Kevin Aylward"
<ExtractkevinRemove@kevinaylward.co.uk> wrote:

>"Jim Thompson" wrote in message >news:id54p9592rafpno41qgr5ktbh97t86did5@4ax.com... > > >>>for sure. Unless I'm very much mistaken, it would be a lot faster and >>>cheaper to make a couple of boards and have a look. >> >>>Spice and Spice model based simulations at the device level, are pretty >>>much, engineering perfect, even for non-linear noise effects. It cost >>>money >>>though. >> >>>Just this last week I have yet another asic come back where the >>>simulations >>of phase noise for a complicated oscillator system come nuts on. Its >>Spectre >>>R.F PSS Noise, but it still uses the same spice BSim3 and VBIC models used >>>in Spice. This Software deals with all the complicated interaction of >>>mixing >>>up 1/f noise, non-linear buffer stages and VCF modulation and gets within >>>a >>>db or so over the range of -60 dBc to -170 dBc phase noise, due to device >>>noise. Its actually stunning that the right mathematics means that chips >>>can >>>be designed first time correctly purely in the virtual world. Its just a >>>fact. Simulations work, and its faster and cheaper than spinning test >>>chips >>:-) > > >>Lot of nay-sayers here, but I've not had a chip come out of foundry in >>many years that didn't perfectly match the simulations. > >Of course, sometimes one misses doing a simulation or two...
Once per fault type >:-} I've mentioned before... some years ago a design simulated perfectly but, in real life, as it powered up, it sucked enough current to stop the power supply ramp-up. Now that is a standard test I do. (Fortunately it didn't kill the chip, and a quick ion-milling showed a viable solution, so we sampled ion-milled parts while we patched the mask set... only one layer, fortunately.)
> >Sometimes you have to modify the kit setup though. Fabs are clueless as to >what an analog design requires. I have had fabs tie the pnp and npn models >together for weak, nominal and strong so had to have them split to >independently be able to do 4 strong/weak corners of npn/pnp X4 corners of >nmos/pmos X vps corners X temp corners etc. The current Cadence >corner-parameter sweep setups are really good. Unlimited combinations, with >multiple setups. > >Kevin Aylward B.Sc. >www.kevinaylward.co.uk >www.anasoft.co.uk - SuperSpice
Yep. I roll my own corners, particularly now that Cadence has convinced X-Fab to drop PSpice support. Sometimes I have as many as 81 corners in a run ;-) ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
"Jim Thompson"  wrote in message 
news:9m86p91rdao6m7dlm5ho1escdirvhpepa0@4ax.com...

On Sat, 7 Jun 2014 07:25:20 +0100, "Kevin Aylward"
<ExtractkevinRemove@kevinaylward.co.uk> wrote:

>"Jim Thompson" wrote in message >news:id54p9592rafpno41qgr5ktbh97t86did5@4ax.com... > > >>>for sure. Unless I'm very much mistaken, it would be a lot faster and >>>cheaper to make a couple of boards and have a look. >> >>>Spice and Spice model based simulations at the device level, are pretty >>>much, engineering perfect, even for non-linear noise effects. It cost >>>money >>>though. >> >>>Just this last week I have yet another asic come back where the >>>simulations >>of phase noise for a complicated oscillator system come nuts on. Its >>Spectre >>>R.F PSS Noise, but it still uses the same spice BSim3 and VBIC models >>>used >>>in Spice. This Software deals with all the complicated interaction of >>>mixing >>>up 1/f noise, non-linear buffer stages and VCF modulation and gets within >>>a >>>db or so over the range of -60 dBc to -170 dBc phase noise, due to device >>>>noise. Its actually stunning that the right mathematics means that chips >>>can >>>>be designed first time correctly purely in the virtual world. Its just a >>>>fact. Simulations work, and its faster and cheaper than spinning test >>>chips >>:-) > > >>>Lot of nay-sayers here, but I've not had a chip come out of foundry in >>many years that didn't perfectly match the simulations. > >>Of course, sometimes one misses doing a simulation or two...
Once per fault type >:-}
>I've mentioned before... some years ago a design simulated perfectly >but, in real life, as it powered up, it sucked enough current to stop >the power supply ramp-up.
>Now that is a standard test I do.
>(Fortunately it didn't kill the chip, and a quick ion-milling showed a >viable solution, so we sampled ion-milled parts while we patched the >mask set... only one layer, fortunately.)
Often its the real trivial oversights.
> >>Sometimes you have to modify the kit setup though. Fabs are clueless as to >>what an analog design requires. I have had fabs tie the pnp and npn models >>together for weak, nominal and strong so had to have them split to >>independently be able to do 4 strong/weak corners of npn/pnp X4 corners of >>nmos/pmos X vps corners X temp corners etc. The current Cadence >>corner-parameter sweep setups are really good. Unlimited combinations, >>with >>multiple setups. >
>Yep. I roll my own corners, particularly now that Cadence has >convinced X-Fab to drop PSpice support. Sometimes I have as many as >81 corners in a run ;-)
Luxury...sheer luxury...you are lucky son...I used to dream when I could only do so few simulations. Including parameter sweep combinations, I run 347,874, and still have time to make the tea for the whole team...and breakfast. Kevin Aylward B.Sc. www.kevinaylward.co.uk www.anasoft.co.uk - SuperSpice
On Sat, 7 Jun 2014 15:53:19 +0100, "Kevin Aylward"
<ExtractkevinRemove@kevinaylward.co.uk> wrote:

>"Jim Thompson" wrote in message >news:9m86p91rdao6m7dlm5ho1escdirvhpepa0@4ax.com... > >On Sat, 7 Jun 2014 07:25:20 +0100, "Kevin Aylward" ><ExtractkevinRemove@kevinaylward.co.uk> wrote: > >>"Jim Thompson" wrote in message >>news:id54p9592rafpno41qgr5ktbh97t86did5@4ax.com... >> >> >>>>for sure. Unless I'm very much mistaken, it would be a lot faster and >>>>cheaper to make a couple of boards and have a look. >>> >>>>Spice and Spice model based simulations at the device level, are pretty >>>>much, engineering perfect, even for non-linear noise effects. It cost >>>>money >>>>though. >>> >>>>Just this last week I have yet another asic come back where the >>>>simulations >>>of phase noise for a complicated oscillator system come nuts on. Its >>>Spectre >>>>R.F PSS Noise, but it still uses the same spice BSim3 and VBIC models >>>>used >>>>in Spice. This Software deals with all the complicated interaction of >>>>mixing >>>>up 1/f noise, non-linear buffer stages and VCF modulation and gets within >>>>a >>>>db or so over the range of -60 dBc to -170 dBc phase noise, due to device >>>>>noise. Its actually stunning that the right mathematics means that chips >>>>can >>>>>be designed first time correctly purely in the virtual world. Its just a >>>>>fact. Simulations work, and its faster and cheaper than spinning test >>>>chips >>>:-) >> >> >>>>Lot of nay-sayers here, but I've not had a chip come out of foundry in >>>many years that didn't perfectly match the simulations. >> >>>Of course, sometimes one misses doing a simulation or two... > >Once per fault type >:-} > >>I've mentioned before... some years ago a design simulated perfectly >>but, in real life, as it powered up, it sucked enough current to stop >>the power supply ramp-up. > >>Now that is a standard test I do. > >>(Fortunately it didn't kill the chip, and a quick ion-milling showed a >>viable solution, so we sampled ion-milled parts while we patched the >>mask set... only one layer, fortunately.) > >Often its the real trivial oversights. > >> >>>Sometimes you have to modify the kit setup though. Fabs are clueless as to >>>what an analog design requires. I have had fabs tie the pnp and npn models >>>together for weak, nominal and strong so had to have them split to >>>independently be able to do 4 strong/weak corners of npn/pnp X4 corners of >>>nmos/pmos X vps corners X temp corners etc. The current Cadence >>>corner-parameter sweep setups are really good. Unlimited combinations, >>>with >>>multiple setups. >> > > >>Yep. I roll my own corners, particularly now that Cadence has >>convinced X-Fab to drop PSpice support. Sometimes I have as many as >>81 corners in a run ;-) > > >Luxury...sheer luxury...you are lucky son...I used to dream when I could >only do so few simulations. Including parameter sweep combinations, I run >347,874, and still have time to make the tea for the whole team...and >breakfast. > > >Kevin Aylward B.Sc. >www.kevinaylward.co.uk >www.anasoft.co.uk - SuperSpice
How quaint, sonny. "Shall I be mother?" ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On Fri, 06 Jun 2014 09:37:00 -0700, Jim Thompson  
<To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote:

> The question is... How do you _see_ this noise in a transient > analysis? > > ...Jim Thompson
I'll try to post as much as possible for people here. And reply several times to put the models here, too. Have NO way to do the images, though... The following is a description, with results, upon using .tranoise, a new circuit simulation analysis technique, on a simple implementation of a 'discrete' component OpAmp model to see if indeed the output noise density function increases when an OpAmp goes into slew rate limit. The OpAmp model used was the MC1530 topology whose subckt model was kindly provided by Jim Thompson in the form of a netlist subckt model, with the note that he designed it when he was 23 years old. Only NPN transistors are used throughout the OpAmp with that model labeled 2N3904. See the OpAmp_R.asc for the topology which attempts to match all the component values and numbering information provided by Jim Thompson; combining his subckt model and an inspection of the MASK photo that appears in his OpAmp design tutorial regarding the MC1530. The NPN transistors appeared to be 'minimum geometry' size. However, the beta of this particular model peaks at over 10mA, which [from memory] is close to where beta peaks for a purchased discrete 2N3904 transistor. [Is the minimum geometry NPN actually placed into the package?] Without confirming, I assumed the minimum geometry NPN is smaller. Thus, the size of each of the NPN was adjusted to be smaller than a full blown NPN model, adjusted to 0.5x in many places, 1x, and 2.5x times in appropriate other places. Changing size did not appreciably change results at this point. The discrete version of MC1530 OpAmp was then configured into being used as a simple inverter. The inverter used Rinput = 10k, Rfdbk = 10k with 2.2pF capacitor in parallel to it and IN+ grounded. The load was 2k with 2.2pF in parallel. The circuit was powered by +/- 6 Vdc, and then driven by two different signal levels. One signal level keeps the OpAmp in linear mode and the other drives it into slew rate limit. First, driven with 2mVpk at 400kHz and then increased to 2Vpk which puts the circuit into slew rate limit. The circuit was simulated for these two conditions by first using normal LTspice .tran and then using .tranoise. The results were plotted to show the time waveforms and the FFT waveforms. As expected the slew rate limited V(out) time waveforms from a drive of 2Vpk look identical, yet yield distinctly different FFT plots, since .tranoise analyses contain noise in the calculated signals and .tran does not. This difference was far more obvious when the circuit was driven with only 2mVpk, because the noise appears as very distinct 'fuzz' on the time waveform. Looks like an actual scope trace. At this time, only five resistors [Rinput, Rfdbk, R7, R8, and R11 as listed in Jim Thompson's netlist] were 'allowed' to contribute noise. This decision was totally arbitrary. Other noise sources will be added and contributions from the NPN's will be added, just wanted to take a preliminary look. As a sanity check of this preliminary simulation, LTspice .noise analysis were compared to the .tranoise results. LTspice .noise analysis shows V(onoise) around 21.5 nVrms/rtHz. Using .tranoise analyses, with the background noise energy from ONLY those five resistors, resulted in a noise density function at the output, V(out), of around 14.2 nVrms/rtHz so it seemed reasonable to continue doing this preliminary comparison of results. By inspection of the .tranoise FFT plots in the low frequency range, the noise definitely increases as the OpAmp goes into slew rate limit [low frequency range is inside the loop gain]. Note how the noise comes up dramatically during slew rate limit, approximately 3X. In the higher frequency range, which is outside the loop gain, the noise density function did not change appreciably. Seems reasonable. Not shown here, the noise drops magnitudes when the output 'hits' the rails, again expected, but .tranoise will quantify the effect. Conclusion is that indeed the noise density function, at least inside the loop gain, does increase as the OpAmp goes into slew rate limit. In addition, .tranoise is a fascinating enhancement to circuit simulation. Since .tranoise analyses have noise simultaneously processed with signals, interactions between nonlinear circuit operation and noise become observable and those effects are quantifiable. Time waveforms LOOK like scope traces, and the FFT plots LOOK like spectrum analyzer traces. Simulation predicts an increase in noise floor, has anybody ever done this simple test WITH an actual circuit to see what happens?
On Fri, 06 Jun 2014 09:37:00 -0700, Jim Thompson  
<To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote:

> The question is... How do you _see_ this noise in a transient > analysis? > > ...Jim Thompson
here is the .asc followed [I think there's room] the symbol, watch out for word wrap = = = = here is MC1530_JimThompson_SUB.asc, which needs the following MC1530.asy Version 4 SHEET 1 1736 680 WIRE -272 0 -288 0 WIRE -192 0 -272 0 WIRE -16 0 -112 0 WIRE 80 0 -16 0 WIRE 240 0 160 0 WIRE 256 0 240 0 WIRE -16 48 -16 0 WIRE 320 48 288 48 WIRE 400 48 384 48 WIRE -16 160 -96 160 WIRE 112 160 64 160 WIRE 128 160 112 160 WIRE 288 160 288 48 WIRE 288 160 128 160 WIRE 304 160 288 160 WIRE 400 160 400 48 WIRE 400 160 384 160 WIRE 464 160 400 160 WIRE 560 160 464 160 WIRE 592 160 560 160 WIRE -96 176 -96 160 WIRE 224 208 208 208 WIRE 240 208 224 208 WIRE 240 240 240 208 WIRE -96 288 -96 256 WIRE 112 288 112 160 WIRE 176 288 112 288 WIRE 464 304 464 160 WIRE 464 304 304 304 WIRE 176 320 112 320 WIRE -96 400 -96 368 WIRE 112 400 112 320 WIRE 192 400 192 368 WIRE 240 416 240 368 WIRE 272 416 240 416 WIRE 288 416 272 416 WIRE 464 416 464 304 WIRE 464 416 384 416 WIRE 464 448 464 416 WIRE 384 464 384 416 WIRE 384 560 384 528 WIRE 464 560 464 528 FLAG 464 560 0 FLAG 384 560 0 FLAG -96 400 0 FLAG -16 48 0 FLAG 240 0 Vcc FLAG -272 0 Vee FLAG 560 160 out FLAG 128 160 in- FLAG 112 400 0 FLAG 192 400 0 FLAG 224 208 Vcc FLAG 272 416 Vee SYMBOL res -32 176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName Rinput SYMATTR Value 10k SYMBOL res 288 176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName Rfdbk SYMATTR Value 10k SYMBOL cap 320 64 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName Cfdbk SYMATTR Value 2.2pF SYMBOL res 448 432 R0 SYMATTR InstName R3 SYMATTR Value 2.2k SYMBOL cap 368 464 R0 SYMATTR InstName C2 SYMATTR Value 2.2pF SYMBOL voltage -96 160 R0 WINDOW 123 -96 49 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 -186 80 Left 2 WINDOW 0 -76 20 Left 2 SYMATTR Value2 AC 1 SYMATTR Value SINE(0 2 400k) SYMATTR InstName Vin SYMBOL Misc\\battery -96 0 R90 WINDOW 0 -32 56 VBottom 2 WINDOW 3 32 56 VTop 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName VVee SYMATTR Value 6 SYMBOL Misc\\battery 176 0 R90 WINDOW 0 -32 56 VBottom 2 WINDOW 3 32 56 VTop 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName VVcc SYMATTR Value 6 SYMBOL MC1530 224 304 R0 WINDOW 0 67 -58 Left 2 WINDOW 38 69 -26 Left 2 SYMATTR InstName U1 SYMATTR SpiceModel MC1530 SYMATTR Prefix X SYMBOL voltage -96 272 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 WINDOW 0 -128 36 Left 2 WINDOW 3 -110 68 Left 2 SYMATTR InstName Voffset SYMATTR Value {Voff} TEXT 1416 608 Left 2 ;right edge TEXT 672 -368 Left 2 !* The OpAmp I designed when I was 23 years old...\n.SUBCKT MC1530 IN+ IN- OUT VCC G_N_D VEE \nR9 1 G_N_D 3.2K \nR5 2 VEE 1.5K \nR3 3 VEE 2.2K \nR6 4 G_N_D 1.5K \nR10 G_N_D 5 3.3K \nR10A 6 VEE 100 \nR10B 7 VEE 100 \nQ38 9 8 4 2N3904JT \nQ37 10 10 VEE 2N3904JT \nQ40 5 5 6 2N3904JT \nQ31 11 11 2 2N3904JT \nQ30 1 1 11 2N3904JT \nQ29 12 1 3 2N3904JT \nQ42 OUT 10 VEE 2N3904JT 5\nQ33 8 IN- 12 2N3904JT \nR8 VCC 13 5K \nR4 VCC 9 3K \nQ35 VCC 9 14 2N3904JT \nQ41 VCC 13 OUT 2N3904JT 5\nQ34 13 15 10 2N3904JT \nQ39 15 5 7 2N3904JT \nR2 VCC 8 7.75K \nQ36 VCC 16 4 2N3904JT \nQ32 16 IN+ 12 2N3904JT \nR1 VCC 16 7.75K \nR11 15 OUT 30K \nR7 14 15 6K \nC1 17 16 33nF \nR26 17 8 3 \n.model 2N3904JT NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 \n+ Ne=1.259 Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 \n+ Rc=1 Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 \n+ Vje=.75 Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb=10)\n.ENDS MC1530 TEXT -288 -352 Left 2 ;.ac dec 200 1 100MEG\n.param Voff=0 TEXT -288 -272 Left 2 ;.tran 0 1.1m 0.1m 20nS\n.param Voff=0 TEXT -280 560 Left 2 !.options plotwinsize=0 TEXT -288 -200 Left 2 ;.noise V(out) Vin dec 200 1 5MEG\n.step param Voff list 0 5 -5 TEXT 160 -352 Left 2 !.ac dec 200 1 100MEG\n.step param Voff list 0 2 4 -2 -4 = = = here is MC1530.asy Version 4 SymbolType BLOCK LINE Normal 81 0 81 0 LINE Normal -48 -63 81 0 LINE Normal 16 -32 16 -63 LINE Normal -48 65 -48 -63 LINE Normal 81 0 -48 65 LINE Normal 16 63 16 33 LINE Normal -32 64 -32 57 PIN -48 16 LEFT 8 PINATTR PinName IN+ PINATTR SpiceOrder 1 PIN -48 -16 LEFT 8 PINATTR PinName IN- PINATTR SpiceOrder 2 PIN 80 0 RIGHT 8 PINATTR PinName OUT PINATTR SpiceOrder 3 PIN 16 -64 TOP 8 PINATTR PinName Vcc PINATTR SpiceOrder 4 PIN -32 64 BOTTOM 8 PINATTR PinName G.D PINATTR SpiceOrder 5 PIN 16 64 BOTTOM 8 PINATTR PinName Vee PINATTR SpiceOrder 6
On Fri, 06 Jun 2014 09:37:00 -0700, Jim Thompson  
<To-Email-Use-The-Envelope-Icon@on-my-web-site.com> wrote:

> The question is... How do you _see_ this noise in a transient > analysis? > > ...Jim Thompson
here is the 'detailed' version of the discrete OpAmp watch for wordwrap MC1530_num_2N3904JT_adjustablesize.asc Version 4 SHEET 1 3128 1064 WIRE 1504 -336 1488 -336 WIRE 1520 -336 1504 -336 WIRE 1104 -288 880 -288 WIRE 1312 -288 1104 -288 WIRE 1520 -288 1520 -336 WIRE 1520 -288 1312 -288 WIRE 1840 -288 1520 -288 WIRE 2112 -288 1840 -288 WIRE 2384 -288 2112 -288 WIRE 880 -240 880 -288 WIRE 1104 -240 1104 -288 WIRE 1520 -240 1520 -288 WIRE 2112 -240 2112 -288 WIRE 1840 -160 1840 -288 WIRE 2384 -160 2384 -288 WIRE 1520 -112 1520 -160 WIRE 1584 -112 1520 -112 WIRE 1776 -112 1584 -112 WIRE 2112 -112 2112 -160 WIRE 2176 -112 2112 -112 WIRE 2320 -112 2176 -112 WIRE 1312 -32 1312 -288 WIRE 1520 -32 1520 -112 WIRE 1840 -32 1840 -64 WIRE 1840 -16 1840 -32 WIRE 880 16 880 -160 WIRE 960 16 880 16 WIRE 1248 16 960 16 WIRE 1600 16 1584 16 WIRE 1408 64 1312 64 WIRE 1520 64 1408 64 WIRE 880 96 880 16 WIRE 896 96 880 96 WIRE 976 96 960 96 WIRE 1008 96 976 96 WIRE 1104 96 1104 -160 WIRE 1104 96 1088 96 WIRE 1184 96 1104 96 WIRE 1600 96 1600 16 WIRE 1600 96 1184 96 WIRE 1408 160 1408 64 WIRE 1840 160 1840 64 WIRE 1904 160 1840 160 WIRE 2208 160 1904 160 WIRE 2384 160 2384 -64 WIRE 2384 160 2288 160 WIRE 2496 160 2384 160 WIRE 2528 160 2496 160 WIRE -144 192 -160 192 WIRE -64 192 -144 192 WIRE 112 192 16 192 WIRE 208 192 112 192 WIRE 368 192 288 192 WIRE 384 192 368 192 WIRE 880 208 880 96 WIRE 1104 208 1104 96 WIRE 112 240 112 192 WIRE 2112 240 2112 -112 WIRE 688 256 672 256 WIRE 816 256 688 256 WIRE 1200 256 1168 256 WIRE 1408 256 1408 160 WIRE 1840 288 1840 160 WIRE 2048 288 1840 288 WIRE 320 304 288 304 WIRE 400 304 384 304 WIRE 880 336 880 304 WIRE 944 336 880 336 WIRE 992 336 944 336 WIRE 1104 336 1104 304 WIRE 1104 336 992 336 WIRE 688 352 672 352 WIRE 1200 352 1200 256 WIRE 1200 352 688 352 WIRE 992 384 992 336 WIRE 1840 384 1840 288 WIRE 48 416 -64 416 WIRE 192 416 128 416 WIRE 288 416 288 304 WIRE 288 416 192 416 WIRE 304 416 288 416 WIRE 400 416 400 304 WIRE 400 416 384 416 WIRE 464 416 400 416 WIRE 560 416 464 416 WIRE 592 416 560 416 WIRE -64 432 -64 416 WIRE 1120 432 1056 432 WIRE 1200 432 1120 432 WIRE 1264 432 1200 432 WIRE 1408 432 1408 336 WIRE 1408 432 1344 432 WIRE 1472 432 1408 432 WIRE 1632 432 1552 432 WIRE 1680 432 1632 432 WIRE 1776 432 1680 432 WIRE 1200 464 1200 432 WIRE 1200 464 1120 464 WIRE 1680 464 1680 432 WIRE 1680 464 1600 464 WIRE 1200 480 1200 464 WIRE 1680 480 1680 464 WIRE 160 528 144 528 WIRE 256 528 224 528 WIRE 464 528 464 416 WIRE 464 528 384 528 WIRE 1120 528 1120 464 WIRE 1136 528 1120 528 WIRE 1600 528 1600 464 WIRE 1616 528 1600 528 WIRE -64 544 -64 512 WIRE 2384 544 2384 160 WIRE 144 560 144 528 WIRE 464 560 464 528 WIRE 992 560 992 480 WIRE 384 576 384 528 WIRE 2112 592 2112 336 WIRE 2176 592 2112 592 WIRE 2320 592 2176 592 WIRE 1136 608 1120 608 WIRE 1200 608 1200 576 WIRE 1200 608 1136 608 WIRE 1200 624 1200 608 WIRE -64 656 -64 624 WIRE 1680 656 1680 576 WIRE 1840 656 1840 480 WIRE 384 672 384 640 WIRE 464 672 464 640 WIRE 1120 672 1120 608 WIRE 1136 672 1120 672 WIRE 2112 704 2112 592 WIRE 2112 704 2032 704 WIRE 2112 720 2112 704 WIRE 1200 736 1200 720 WIRE 1680 736 1680 656 WIRE 1840 736 1840 656 WIRE 992 752 992 560 WIRE 1200 752 1200 736 WIRE 2032 768 2032 704 WIRE 2048 768 2032 768 WIRE 992 880 992 832 WIRE 1200 880 1200 832 WIRE 1200 880 992 880 WIRE 1680 880 1680 816 WIRE 1680 880 1200 880 WIRE 1840 880 1840 816 WIRE 1840 880 1680 880 WIRE 2112 880 2112 816 WIRE 2112 880 1840 880 WIRE 2384 880 2384 640 WIRE 2384 880 2112 880 WIRE 1344 928 1328 928 WIRE 1408 928 1408 432 WIRE 1408 928 1344 928 WIRE 1408 944 1408 928 WIRE 1648 976 1632 976 WIRE 1680 976 1680 880 WIRE 1680 976 1648 976 WIRE 1408 1024 1408 1008 FLAG 464 672 0 FLAG 384 672 0 FLAG -64 656 0 FLAG 112 240 0 FLAG 368 192 Vcc FLAG -144 192 Vee FLAG 560 416 OUT FLAG 192 416 IN- FLAG 688 256 IN+ FLAG 688 352 IN- FLAG 1504 -336 Vcc FLAG 1408 1024 0 FLAG 1648 976 Vee FLAG 2496 160 OUT FLAG 144 560 0 FLAG 256 528 IN+ FLAG 1344 928 G_N_D FLAG 960 16 16 FLAG 1184 96 8 FLAG 1584 -112 9 FLAG 1408 160 4 FLAG 1904 160 15 FLAG 2176 -112 13 FLAG 992 560 3 FLAG 1136 608 11 FLAG 1120 432 1 FLAG 1632 432 5 FLAG 1680 656 6 FLAG 1840 656 7 FLAG 2176 592 10 FLAG 1840 -32 14 FLAG 976 96 17 FLAG 944 336 12 FLAG 1200 736 2 SYMBOL res 32 432 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName Rinput SYMATTR Value 10k SYMBOL res 288 432 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName Rfdbk SYMATTR Value 10k SYMBOL cap 320 320 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName Cfdbk SYMATTR Value 2.2pF SYMBOL res 448 544 R0 SYMATTR InstName Rload SYMATTR Value 2.2k SYMBOL cap 368 576 R0 SYMATTR InstName Cload SYMATTR Value 2.2pF SYMBOL voltage -64 416 R0 WINDOW 123 -100 46 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 -181 85 Left 2 WINDOW 0 -80 13 Left 2 SYMATTR Value2 AC 1 SYMATTR Value SINE(0 2 400k) SYMATTR InstName Vin SYMBOL Misc\\battery 32 192 R90 WINDOW 0 -32 56 VBottom 2 WINDOW 3 32 56 VTop 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName VVee SYMATTR Value 6 SYMBOL Misc\\battery 304 192 R90 WINDOW 0 -32 56 VBottom 2 WINDOW 3 32 56 VTop 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName VVcc SYMATTR Value 6 SYMBOL voltage -64 528 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 WINDOW 0 -116 29 Left 2 WINDOW 3 -116 75 Left 2 SYMATTR InstName Voffset SYMATTR Value {Voff} SYMBOL res 864 -256 R0 SYMATTR InstName R1 SYMATTR Value 7.75k SYMBOL res 1088 -256 R0 SYMATTR InstName R2 SYMATTR Value 7.75k SYMBOL res 976 736 R0 SYMATTR InstName R3 SYMATTR Value 2.2k SYMBOL res 1184 736 R0 SYMATTR InstName R5 SYMATTR Value 1.5k SYMBOL res 1392 240 R0 SYMATTR InstName R6 SYMATTR Value 1.5k SYMBOL res 1824 -32 R0 SYMATTR InstName R7 SYMATTR Value 6K SYMBOL res 2096 -256 R0 SYMATTR InstName R8 SYMATTR Value 5k SYMBOL res 1248 448 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R9 SYMATTR Value 3.2k SYMBOL res 1456 448 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R10 SYMATTR Value 3.3k SYMBOL res 1504 -256 R0 SYMATTR InstName R4 SYMATTR Value 3k SYMBOL res 2192 176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R11 SYMATTR Value 30k SYMBOL npn 816 208 R0 WINDOW 123 74 75 Left 2 WINDOW 0 75 15 Left 2 WINDOW 3 44 47 Left 2 SYMATTR Value2 {sz} SYMATTR InstName Q32 SYMATTR Value 2N3904JT SYMBOL npn 1168 208 M0 WINDOW 123 83 81 Left 2 WINDOW 0 86 20 Left 2 WINDOW 3 53 50 Left 2 SYMATTR Value2 {sz} SYMATTR InstName Q33 SYMATTR Value 2N3904JT SYMBOL npn 1248 -32 R0 WINDOW 123 68 75 Left 2 WINDOW 0 72 17 Left 2 WINDOW 3 41 47 Left 2 SYMATTR Value2 {sz} SYMATTR InstName Q36 SYMATTR Value 2N3904JT SYMBOL npn 1584 -32 M0 WINDOW 123 71 73 Left 2 WINDOW 0 72 14 Left 2 WINDOW 3 41 48 Left 2 SYMATTR Value2 {sz} SYMATTR InstName Q38 SYMATTR Value 2N3904JT SYMBOL npn 1056 384 M0 WINDOW 123 85 82 Left 2 WINDOW 0 87 21 Left 2 WINDOW 3 60 48 Left 2 SYMATTR Value2 {sz} SYMATTR InstName Q29 SYMATTR Value 2N3904JT SYMBOL npn 1136 480 R0 WINDOW 123 73 76 Left 2 WINDOW 0 73 21 Left 2 WINDOW 3 43 48 Left 2 SYMATTR Value2 {sz} SYMATTR InstName Q30 SYMATTR Value 2N3904JT SYMBOL npn 1136 624 R0 WINDOW 123 75 72 Left 2 WINDOW 0 75 15 Left 2 WINDOW 3 41 44 Left 2 SYMATTR Value2 {sz} SYMATTR InstName Q31 SYMATTR Value 2N3904JT SYMBOL npn 1616 480 R0 WINDOW 123 70 74 Left 2 WINDOW 0 64 23 Left 2 WINDOW 3 41 50 Left 2 SYMATTR Value2 {2*sz} SYMATTR InstName Q40 SYMATTR Value 2N3904JT SYMBOL npn 1776 384 R0 WINDOW 123 79 76 Left 2 WINDOW 0 77 18 Left 2 WINDOW 3 42 49 Left 2 SYMATTR Value2 {2*sz} SYMATTR InstName Q39 SYMATTR Value 2N3904JT SYMBOL npn 2048 720 R0 WINDOW 123 76 77 Left 2 WINDOW 0 72 16 Left 2 WINDOW 3 38 47 Left 2 SYMATTR Value2 {sz} SYMATTR InstName Q37 SYMATTR Value 2N3904JT SYMBOL npn 2320 544 R0 WINDOW 123 71 79 Left 2 WINDOW 0 71 18 Left 2 WINDOW 3 42 49 Left 2 SYMATTR Value2 {5*sz} SYMATTR InstName Q42 SYMATTR Value 2N3904JT SYMBOL npn 1776 -160 R0 WINDOW 123 74 75 Left 2 WINDOW 0 68 17 Left 2 WINDOW 3 39 48 Left 2 SYMATTR Value2 {sz} SYMATTR InstName Q35 SYMATTR Value 2N3904JT SYMBOL npn 2320 -160 R0 WINDOW 123 72 79 Left 2 WINDOW 0 71 15 Left 2 WINDOW 3 37 48 Left 2 SYMATTR Value2 {5*sz} SYMATTR InstName Q41 SYMATTR Value 2N3904JT SYMBOL npn 2048 240 R0 WINDOW 123 71 72 Left 2 WINDOW 0 70 18 Left 2 WINDOW 3 37 47 Left 2 SYMATTR Value2 {sz} SYMATTR InstName Q34 SYMATTR Value 2N3904JT SYMBOL res 992 112 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R26 SYMATTR Value 3 SYMBOL cap 960 80 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 33nF SYMBOL res 1664 720 R0 SYMATTR InstName R10A SYMATTR Value 100 SYMBOL res 1824 720 R0 SYMATTR InstName R10B SYMATTR Value 100 SYMBOL Misc\\jumper 192 464 R0 SYMATTR InstName X1 SYMBOL Misc\\jumper 1344 976 R270 SYMATTR InstName XGND TEXT -136 -280 Left 2 ;.ac dec 200 10k 100MEG\n.param Voff=0\n.step param sz list 0.1 0.2 0.4 0.7 1 TEXT -144 -152 Left 2 ;.tran 0 1.1m 0.1m 20nS\n.param Voff=0 sz=0.5 TEXT -160 736 Left 2 !.options plotwinsize=0 TEXT 288 -160 Left 2 ;.noise V(out) Vin dec 200 1 10MEG\n.param Voff=0\n.step param sz list 0.1 0.2 0.4 0.7 1 TEXT 296 -280 Left 2 ;.noise V(out) Vin dec 200 1 10MEG\n.param sz=0.5\n.step param Voff list 0 2 -2 TEXT 888 -88 Left 2 ;LAG+ TEXT 1112 -88 Left 2 ;LAG- TEXT 1848 -40 Left 2 ;LEAD+ TEXT 1848 88 Left 2 ;LEAD- TEXT -144 776 Left 2 !.model 2N3904JT NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 \n+ Ne=1.259 Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 \n+ Rc=1 Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 \n+ Vje=.75 Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb=10)