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LTSpice simulator of my oscillator is far from reality; bad models?

Started by Clifford Heath April 4, 2014
Folk,

Thanks to some good help here in the past, I have a nice clean 
oscillator (for my new fox transmitters), but I'm having trouble with 
the LTSpice simulation at higher frequencies. I'm assuming that the 
Intersil Spice model for the CA3046 is bad, and I know JT has a better one.

Anyhow, I have two questions about the attached LTSpice schematic.

1) When I set it to 30MHz, LTSpice says the oscillator will start nicely 
(even up to 150MHz in fact). Now I know that the (calculated) Colpitts 
capacitance ratio is bad, as is the base capacitor, but with the 
physical circuit built in a tight layout in SMD and a range of more 
sensible capacitances substituted, I can't get it to oscillate above 
about 12MHz. Why does it not want to run in real life, when Spice says 
it should? Can someone provide me a better CA3046 model please, or say 
what else might be going on?

2) I'd like some insight into the correct formulae to calculate the 
Colpitts capacitive divider ratio, and the minimum safe base coupling 
capacitor. The CA3046 data sheet says that Cbe and Ccb are both in the 
range of 0.6pF, and the Ft is around 300MHz. So at 150MHz I only have 
3dB of gain to play with, so that Cbe means I need at least a couple of 
pF to drive the base, and the divider ratio has to give reasonable 
drive. If anyone could suggest better "rule of thumb" for calculating 
these things from Ft and Cin, I'd appreciate it.

Clifford Heath
-- Cut Here for OscProblem.asc --
Version 4
SHEET 1 2160 1200
WIRE 304 -336 192 -336
WIRE 752 -336 304 -336
WIRE 192 -288 192 -336
WIRE 192 -176 192 -208
WIRE 192 -176 -64 -176
WIRE 432 -176 192 -176
WIRE 528 -176 432 -176
WIRE 192 -128 192 -176
WIRE 752 -96 752 -336
WIRE 304 -48 304 -336
WIRE 432 -48 432 -176
WIRE -48 0 -64 0
WIRE 32 0 -48 0
WIRE 96 0 32 0
WIRE 192 0 192 -48
WIRE 192 0 160 0
WIRE 240 0 192 0
WIRE 32 64 32 0
WIRE 528 64 528 -176
WIRE -48 144 -48 0
WIRE 432 160 432 32
WIRE 32 208 32 128
WIRE 304 208 304 48
WIRE 304 208 32 208
WIRE 368 208 304 208
WIRE 192 256 192 0
WIRE 304 256 304 208
WIRE 32 272 32 208
WIRE -48 384 -48 224
WIRE 32 384 32 336
WIRE 32 384 -48 384
WIRE 192 384 192 336
WIRE 192 384 32 384
WIRE 304 384 304 336
WIRE 304 384 192 384
WIRE 432 384 432 256
WIRE 432 384 304 384
WIRE 528 384 528 128
WIRE 528 384 432 384
WIRE 752 384 752 -16
WIRE 752 384 528 384
WIRE 752 400 752 384
FLAG 752 400 0
FLAG -64 0 Vosc
IOPIN -64 0 Out
FLAG -64 -176 Vbias
IOPIN -64 -176 Out
SYMBOL voltage 752 -112 R0
WINDOW 123 24 126 Left 2
WINDOW 39 24 111 Left 2
SYMATTR InstName V1
SYMATTR Value 3.2v
SYMBOL cap 16 64 R0
SYMATTR InstName C1
SYMATTR Value {C1}
SYMBOL cap 16 272 R0
SYMATTR InstName C2
SYMATTR Value {C2}
SYMBOL ind -64 128 R0
SYMATTR InstName L3
SYMATTR Value {L1}
SYMBOL npn 240 -48 R0
SYMATTR InstName Q1
SYMATTR Value CA3046
SYMBOL res 176 -144 R0
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL npn 368 160 R0
SYMATTR InstName Q2
SYMATTR Value CA3046
SYMBOL res 176 -304 R0
SYMATTR InstName R2
SYMATTR Value 47k
SYMBOL cap 512 64 R0
SYMATTR InstName C4
SYMATTR Value {100/(F0*10k)}
SYMBOL res 288 240 R0
SYMATTR InstName R6
SYMATTR Value 2.2k
SYMBOL cap 160 -16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value {C3}
SYMBOL res 176 240 R0
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL res 416 -64 R0
SYMATTR InstName R8
SYMATTR Value 10k
TEXT 864 -424 Left 2 !.tran 0 {10u + (2000/F0)} 0 {1/(F0*50)}
TEXT -96 -384 Left 2 !.param F0=30Meg
TEXT -96 440 Left 2 !; Calculate main tank components from F0, ZT and 
stray capacitances:\n.param CSTRAY1=1.7p CSTRAY2=0.8pF\n.param 
L1={ZT/(2*PI*F0)} DIV=17 C2={1/(2*PI*F0*(ZT/DIV)) - CSTRAY1} 
CT={(1/(2*PI*F0*ZT)) - CSTRAY2} C1={1/((1/CT) - (1/C2))}\n.MEASURE L1_ 
PARAM L1\n.MEASURE C1_ PARAM C1\n.MEASURE C2_ PARAM C2
TEXT 872 232 Left 2 !.param ZCouple1=5k C3={max(1/(2*PI*F0*ZCouple1), 
1pF)}\n.MEASURE C3_ PARAM C3
TEXT -96 -344 Left 2 !.param ZT=350
TEXT 872 144 Left 2 !.MEASURE C4_ PARAM {100/(F0*10k)}
TEXT 864 -320 Left 2 !*COPYRIGHT � 1997 INTERSIL CORPORATION\n*ALL 
RIGHTS RESERVED\n*\n*CA3046 PSpice MODEL\n*REV: 2-24-97\n** ----- BJT 
MODEL -----\n*\n.model CA3046 NPN\n+ (IS = 10.0E-15 XTI=3.000E+00 
EG=1.110E+00 VAF=1.00E+02\n+ VAR=1.000E+02 BF=145.7E+00 ISE=114.286E-15 
NE=1.480E+00\n+ IKF=46.700E-03 XTB=0.000E+00 BR=.1000E+00 
ISC=10.005E-15\n+ NC=2.000E+00 IKR=10.00E-03 RC=10.000E+00 
CJC=991.71E-15\n+ MJC=0.333E-00 VJC=0.7500E-00 FC=5.000E-01 
CJE=1.02E-12\n+ MJE=.336E-00 VJE=0.750E-00 TR=10.000E-09 
TF=277.01E-12\n+ ITF=1.750E-00 XTF=309.38E+00 VTF=16.37E+00 
PTF=0.000E+00\n+ RE=0.0E+00 RB=0.00E+00
TEXT -96 -424 Left 2 ;Change these parameters to vary the operating 
frequency and tank impedance
TEXT 696 560 Left 2 ;This model was initially designed and built (works 
fine) at 3.58 MHz.\nWhen run at any frequency up to 150MHz, it still 
simulates fine.\nHowever, the physical circuit only reaches half 
amplitude at 12MHz,\nand doesn't start at all much above that, even when 
larger C3 and\nsmaller C1/C2 ratio is used (to overcome lower gain, 
input capacitance;\n1pf for C3 cannot ever be enough with Cbe=0.5pF 
Ft=300MHz).\nI'd really like to know why. Is my CA3046 model wrong?
On Thu, 03 Apr 2014 20:03:58 -0700, Clifford Heath <no.spam@please.net>  
wrote:

> ...snip....
first glance, 1. SAME model for CA3046 is that in a package, or as a chip? 2. L3 is a 'perfect' inductor?? any photos? of the circuitry? Don't wish to cast aspersions, but layout above 10 MHz starts to become important. up there a short connection is no longer a connection, unless it's wider than long, it's an inductor. resistors have inductance, caps have inductance, everything has stray cap to gnd, and the effect of phase shift along the circuitry ??? I know, but a few degrees is a few degrees. Example of 'macroscopic high frequency modeling: modeled an EMC Conducted Test [made models for the LISN], complete with AC chord models, gnded sheet metal planes, etc. SOLAR ELECTRONICS LISN 8012-50-R-24-BNC RHODE & SCHWARZ LISN ESH2-Z5 in order to explain, design SMPS line filtering and found out that above 10MHz, everything just kind of falls apart. go from accurate to errors worse than 2 to 3 dB, which is still better than a guess, but did not feel solid enough, just too 'squishy' for my taste. Once problem solved could not justify going back to find out what was not quite right. I always thought it just parasitics that aren't represented well.
On Fri, 04 Apr 2014 14:03:58 +1100, Clifford Heath
<no.spam@please.net> wrote:

From my archives (and recently provided to Robert Macy for his noise
experiments)...

Some IC models (NPN) from that era...

******************************************************************
.MODEL CA3046_ORG NPN IS=3.860200F BF=120 NF=1.04845 VAF=61.1026 IKF=
+ 50.000000M ISE=3.100000P NE=2.16533 BR=100.101000M NR=1.04845 ISC=0
+ NC=1 RB=214.644 RBM=214.644 RE=721.362980M RC=9.2065 CJE=1.249000P
+ VJE=899.999940M MJE=499.999970M TF=210.000000P XTF=1.85 VTF=1.585
+ ITF=50.000000M PTF=0 CJC=1.000000P VJC=749.999940M MJC=333.000000M
+ XCJC=499.999970M TR=10.000000N CJS=6.300000P VJS=749.999940M MJS=
+ 499.999970M XTB=1.5 EG=1.11 XTI=3 KF=0 AF=1 FC=499.999970M
*
*COPYRIGHT &#2013266089; 1997 INTERSIL CORPORATION
*ALL RIGHTS RESERVED
*
*CA3046 PSpice MODEL
*REV: 2-24-97
** ----- BJT MODEL -----
*
.model CA3046 NPN
+ (IS = 10.0E-15 XTI= 3.000E+00 EG = 1.110E+00 VAF= 1.00E+02
+ VAR = 1.000E+02 BF = 145.7E+00 ISE = 114.286E-15 NE = 1.480E+00
+ IKF = 46.700E-03 XTB = 0.000E+00 BR = .1000E+00 ISC = 10.005E-15
+ NC = 2.000E+00 IKR = 10.00E-03 RC = 10.000E+00 CJC = 991.71E-15
+ MJC = 0.333E-00 VJC = 0.7500E-00 FC = 5.000E-01 CJE = 1.02E-12
+ MJE = .336E-00 VJE = 0.750E-00 TR = 10.000E-09 TF = 277.01E-12
+ ITF = 1.750E-00 XTF = 309.38E+00 VTF= 16.37E+00 PTF = 0.000E+00
+ RE = 0.0E+00 RB = 0.00E+00
*
*COPYRIGHT &#2013266089; 1997 INTERSIL CORPORATION
*ALL RIGHTS RESERVED
*
*CA3086 PSpice MODEL
*REV: 2-24-97
** ----- BJT MODEL -----
*
.model CA3086 NPN
+ (IS = 10.0E-15 XTI= 3.000E+00 EG = 1.110E+00 VAF= 1.00E+02
+ VAR = 1.000E+02 BF = 156.6E+00 ISE = 114.886E-15 NE = 1.470E+00
+ IKF = 36.700E-03 XTB = 0.000E+00 BR = .1000E+00 ISC = 10.005E-15
+ NC = 2.000E+00 IKR = 10.00E-03 RC = 10.000E+00 CJC = 991.79E-15
+ MJC = 0.333E-00 VJC = 0.7500E-00 FC = 5.000E-01 CJE = 1.02E-12
+ MJE = .336E- 00 VJE = 0.750E-00 TR = 10.000E-09 TF = 278.55E-12
+ ITF = .770E-00 XTF = 91.38E+00 VTF= 18.37E+00 PTF = 0.000E+00
+ RE = 0.0E+00 RB = 0.00E+00
*
*COPYRIGHT &#2013266089; 1997 INTERSIL CORPORATION
*ALL RIGHTS RESERVED
*
*CA3127 PSpice MODEL
*REV: 2-13-97
** ----- BJT MODEL -----
*
.model CA3127 NPN
+ (IS = 3.20p XTI= 3.000 EG = 1.110 VAF= 100
+ VAR = 100 BF = 95.2E ISE = 20.586p NE = 1.990
+ IKF = 61.500m XTB = 0 BR =100m ISC = 10.805n
+ NC = 2.000n IKR = 10m RC = 10m CJC = 281.1f
+ MJC = 0.138 VJC = 0.75 FC = 0.5 CJE = 651.9f
+ MJE = .336 VJE = 0.750 TR = 10n TF = 122.61p
+ ITF = 1.600p XTF = 2.050K VTF= 307 PTF = 0
+ RE = 0 RB = 0
* Application Note MM9701
******************************************************************
.SUBCKT CA3046PAK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Q1 1 2 3 [SUB] CA3046
Q2 5 4 3 [SUB] CA3046
Q3 8 6 7 [SUB] CA3046
Q4 11 9 10 [SUB] CA3046
Q5 14 12 13 [SUB] CA3046
RSUB SUB 13 1
.ENDS CA3046PAK
******************************************************************

>Folk, > >Thanks to some good help here in the past, I have a nice clean >oscillator (for my new fox transmitters), but I'm having trouble with >the LTSpice simulation at higher frequencies. I'm assuming that the >Intersil Spice model for the CA3046 is bad, and I know JT has a better one. > >Anyhow, I have two questions about the attached LTSpice schematic. > >1) When I set it to 30MHz, LTSpice says the oscillator will start nicely >(even up to 150MHz in fact). Now I know that the (calculated) Colpitts >capacitance ratio is bad, as is the base capacitor, but with the >physical circuit built in a tight layout in SMD and a range of more >sensible capacitances substituted, I can't get it to oscillate above >about 12MHz. Why does it not want to run in real life, when Spice says >it should? Can someone provide me a better CA3046 model please, or say >what else might be going on? > >2) I'd like some insight into the correct formulae to calculate the >Colpitts capacitive divider ratio, and the minimum safe base coupling >capacitor. The CA3046 data sheet says that Cbe and Ccb are both in the >range of 0.6pF, and the Ft is around 300MHz. So at 150MHz I only have >3dB of gain to play with, so that Cbe means I need at least a couple of >pF to drive the base, and the divider ratio has to give reasonable >drive. If anyone could suggest better "rule of thumb" for calculating >these things from Ft and Cin, I'd appreciate it. > >Clifford Heath >-- Cut Here for OscProblem.asc -- >Version 4 >SHEET 1 2160 1200 >WIRE 304 -336 192 -336 >WIRE 752 -336 304 -336 >WIRE 192 -288 192 -336 >WIRE 192 -176 192 -208 >WIRE 192 -176 -64 -176 >WIRE 432 -176 192 -176 >WIRE 528 -176 432 -176 >WIRE 192 -128 192 -176 >WIRE 752 -96 752 -336 >WIRE 304 -48 304 -336 >WIRE 432 -48 432 -176 >WIRE -48 0 -64 0 >WIRE 32 0 -48 0 >WIRE 96 0 32 0 >WIRE 192 0 192 -48 >WIRE 192 0 160 0 >WIRE 240 0 192 0 >WIRE 32 64 32 0 >WIRE 528 64 528 -176 >WIRE -48 144 -48 0 >WIRE 432 160 432 32 >WIRE 32 208 32 128 >WIRE 304 208 304 48 >WIRE 304 208 32 208 >WIRE 368 208 304 208 >WIRE 192 256 192 0 >WIRE 304 256 304 208 >WIRE 32 272 32 208 >WIRE -48 384 -48 224 >WIRE 32 384 32 336 >WIRE 32 384 -48 384 >WIRE 192 384 192 336 >WIRE 192 384 32 384 >WIRE 304 384 304 336 >WIRE 304 384 192 384 >WIRE 432 384 432 256 >WIRE 432 384 304 384 >WIRE 528 384 528 128 >WIRE 528 384 432 384 >WIRE 752 384 752 -16 >WIRE 752 384 528 384 >WIRE 752 400 752 384 >FLAG 752 400 0 >FLAG -64 0 Vosc >IOPIN -64 0 Out >FLAG -64 -176 Vbias >IOPIN -64 -176 Out >SYMBOL voltage 752 -112 R0 >WINDOW 123 24 126 Left 2 >WINDOW 39 24 111 Left 2 >SYMATTR InstName V1 >SYMATTR Value 3.2v >SYMBOL cap 16 64 R0 >SYMATTR InstName C1 >SYMATTR Value {C1} >SYMBOL cap 16 272 R0 >SYMATTR InstName C2 >SYMATTR Value {C2} >SYMBOL ind -64 128 R0 >SYMATTR InstName L3 >SYMATTR Value {L1} >SYMBOL npn 240 -48 R0 >SYMATTR InstName Q1 >SYMATTR Value CA3046 >SYMBOL res 176 -144 R0 >SYMATTR InstName R4 >SYMATTR Value 100k >SYMBOL npn 368 160 R0 >SYMATTR InstName Q2 >SYMATTR Value CA3046 >SYMBOL res 176 -304 R0 >SYMATTR InstName R2 >SYMATTR Value 47k >SYMBOL cap 512 64 R0 >SYMATTR InstName C4 >SYMATTR Value {100/(F0*10k)} >SYMBOL res 288 240 R0 >SYMATTR InstName R6 >SYMATTR Value 2.2k >SYMBOL cap 160 -16 R90 >WINDOW 0 0 32 VBottom 2 >WINDOW 3 32 32 VTop 2 >SYMATTR InstName C3 >SYMATTR Value {C3} >SYMBOL res 176 240 R0 >SYMATTR InstName R3 >SYMATTR Value 100k >SYMBOL res 416 -64 R0 >SYMATTR InstName R8 >SYMATTR Value 10k >TEXT 864 -424 Left 2 !.tran 0 {10u + (2000/F0)} 0 {1/(F0*50)} >TEXT -96 -384 Left 2 !.param F0=30Meg >TEXT -96 440 Left 2 !; Calculate main tank components from F0, ZT and >stray capacitances:\n.param CSTRAY1=1.7p CSTRAY2=0.8pF\n.param >L1={ZT/(2*PI*F0)} DIV=17 C2={1/(2*PI*F0*(ZT/DIV)) - CSTRAY1} >CT={(1/(2*PI*F0*ZT)) - CSTRAY2} C1={1/((1/CT) - (1/C2))}\n.MEASURE L1_ >PARAM L1\n.MEASURE C1_ PARAM C1\n.MEASURE C2_ PARAM C2 >TEXT 872 232 Left 2 !.param ZCouple1=5k C3={max(1/(2*PI*F0*ZCouple1), >1pF)}\n.MEASURE C3_ PARAM C3 >TEXT -96 -344 Left 2 !.param ZT=350 >TEXT 872 144 Left 2 !.MEASURE C4_ PARAM {100/(F0*10k)} >TEXT 864 -320 Left 2 !*COPYRIGHT &#2013266089; 1997 INTERSIL CORPORATION\n*ALL >RIGHTS RESERVED\n*\n*CA3046 PSpice MODEL\n*REV: 2-24-97\n** ----- BJT >MODEL -----\n*\n.model CA3046 NPN\n+ (IS = 10.0E-15 XTI=3.000E+00 >EG=1.110E+00 VAF=1.00E+02\n+ VAR=1.000E+02 BF=145.7E+00 ISE=114.286E-15 >NE=1.480E+00\n+ IKF=46.700E-03 XTB=0.000E+00 BR=.1000E+00 >ISC=10.005E-15\n+ NC=2.000E+00 IKR=10.00E-03 RC=10.000E+00 >CJC=991.71E-15\n+ MJC=0.333E-00 VJC=0.7500E-00 FC=5.000E-01 >CJE=1.02E-12\n+ MJE=.336E-00 VJE=0.750E-00 TR=10.000E-09 >TF=277.01E-12\n+ ITF=1.750E-00 XTF=309.38E+00 VTF=16.37E+00 >PTF=0.000E+00\n+ RE=0.0E+00 RB=0.00E+00 >TEXT -96 -424 Left 2 ;Change these parameters to vary the operating >frequency and tank impedance >TEXT 696 560 Left 2 ;This model was initially designed and built (works >fine) at 3.58 MHz.\nWhen run at any frequency up to 150MHz, it still >simulates fine.\nHowever, the physical circuit only reaches half >amplitude at 12MHz,\nand doesn't start at all much above that, even when >larger C3 and\nsmaller C1/C2 ratio is used (to overcome lower gain, >input capacitance;\n1pf for C3 cannot ever be enough with Cbe=0.5pF >Ft=300MHz).\nI'd really like to know why. Is my CA3046 model wrong?
...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
On 04/04/14 15:04, Jim Thompson wrote:
> On Fri, 04 Apr 2014 14:03:58 +1100, Clifford Heath > <no.spam@please.net> wrote: > From my archives (and recently provided to Robert Macy for his noise > experiments)... > Some IC models (NPN) from that era...
Thanks, that second one is the same one I copied into the ASC file below. is the CA3046_ORG the model originally from Intersil, and the other is yours? My device is actually LM3046, but I don't expect any differences that would affect things at 30MHz, though perhaps at 150. Layouts are referenced in my other response. Clifford Heath.
> ****************************************************************** > .MODEL CA3046_ORG NPN IS=3.860200F BF=120 NF=1.04845 VAF=61.1026 IKF= > + 50.000000M ISE=3.100000P NE=2.16533 BR=100.101000M NR=1.04845 ISC=0 > + NC=1 RB=214.644 RBM=214.644 RE=721.362980M RC=9.2065 CJE=1.249000P > + VJE=899.999940M MJE=499.999970M TF=210.000000P XTF=1.85 VTF=1.585 > + ITF=50.000000M PTF=0 CJC=1.000000P VJC=749.999940M MJC=333.000000M > + XCJC=499.999970M TR=10.000000N CJS=6.300000P VJS=749.999940M MJS= > + 499.999970M XTB=1.5 EG=1.11 XTI=3 KF=0 AF=1 FC=499.999970M > * > *COPYRIGHT &#2013266089; 1997 INTERSIL CORPORATION > *ALL RIGHTS RESERVED > * > *CA3046 PSpice MODEL > *REV: 2-24-97 > ** ----- BJT MODEL ----- > * > .model CA3046 NPN > + (IS = 10.0E-15 XTI= 3.000E+00 EG = 1.110E+00 VAF= 1.00E+02 > + VAR = 1.000E+02 BF = 145.7E+00 ISE = 114.286E-15 NE = 1.480E+00 > + IKF = 46.700E-03 XTB = 0.000E+00 BR = .1000E+00 ISC = 10.005E-15 > + NC = 2.000E+00 IKR = 10.00E-03 RC = 10.000E+00 CJC = 991.71E-15 > + MJC = 0.333E-00 VJC = 0.7500E-00 FC = 5.000E-01 CJE = 1.02E-12 > + MJE = .336E-00 VJE = 0.750E-00 TR = 10.000E-09 TF = 277.01E-12 > + ITF = 1.750E-00 XTF = 309.38E+00 VTF= 16.37E+00 PTF = 0.000E+00 > + RE = 0.0E+00 RB = 0.00E+00 > * > *COPYRIGHT &#2013266089; 1997 INTERSIL CORPORATION > *ALL RIGHTS RESERVED > * > *CA3086 PSpice MODEL > *REV: 2-24-97 > ** ----- BJT MODEL ----- > * > .model CA3086 NPN > + (IS = 10.0E-15 XTI= 3.000E+00 EG = 1.110E+00 VAF= 1.00E+02 > + VAR = 1.000E+02 BF = 156.6E+00 ISE = 114.886E-15 NE = 1.470E+00 > + IKF = 36.700E-03 XTB = 0.000E+00 BR = .1000E+00 ISC = 10.005E-15 > + NC = 2.000E+00 IKR = 10.00E-03 RC = 10.000E+00 CJC = 991.79E-15 > + MJC = 0.333E-00 VJC = 0.7500E-00 FC = 5.000E-01 CJE = 1.02E-12 > + MJE = .336E- 00 VJE = 0.750E-00 TR = 10.000E-09 TF = 278.55E-12 > + ITF = .770E-00 XTF = 91.38E+00 VTF= 18.37E+00 PTF = 0.000E+00 > + RE = 0.0E+00 RB = 0.00E+00 > * > *COPYRIGHT &#2013266089; 1997 INTERSIL CORPORATION > *ALL RIGHTS RESERVED > * > *CA3127 PSpice MODEL > *REV: 2-13-97 > ** ----- BJT MODEL ----- > * > .model CA3127 NPN > + (IS = 3.20p XTI= 3.000 EG = 1.110 VAF= 100 > + VAR = 100 BF = 95.2E ISE = 20.586p NE = 1.990 > + IKF = 61.500m XTB = 0 BR =100m ISC = 10.805n > + NC = 2.000n IKR = 10m RC = 10m CJC = 281.1f > + MJC = 0.138 VJC = 0.75 FC = 0.5 CJE = 651.9f > + MJE = .336 VJE = 0.750 TR = 10n TF = 122.61p > + ITF = 1.600p XTF = 2.050K VTF= 307 PTF = 0 > + RE = 0 RB = 0 > * Application Note MM9701 > ****************************************************************** > .SUBCKT CA3046PAK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 > Q1 1 2 3 [SUB] CA3046 > Q2 5 4 3 [SUB] CA3046 > Q3 8 6 7 [SUB] CA3046 > Q4 11 9 10 [SUB] CA3046 > Q5 14 12 13 [SUB] CA3046 > RSUB SUB 13 1 > .ENDS CA3046PAK > ****************************************************************** > >> Folk, >> >> Thanks to some good help here in the past, I have a nice clean >> oscillator (for my new fox transmitters), but I'm having trouble with >> the LTSpice simulation at higher frequencies. I'm assuming that the >> Intersil Spice model for the CA3046 is bad, and I know JT has a better one. >> >> Anyhow, I have two questions about the attached LTSpice schematic. >> >> 1) When I set it to 30MHz, LTSpice says the oscillator will start nicely >> (even up to 150MHz in fact). Now I know that the (calculated) Colpitts >> capacitance ratio is bad, as is the base capacitor, but with the >> physical circuit built in a tight layout in SMD and a range of more >> sensible capacitances substituted, I can't get it to oscillate above >> about 12MHz. Why does it not want to run in real life, when Spice says >> it should? Can someone provide me a better CA3046 model please, or say >> what else might be going on? >> >> 2) I'd like some insight into the correct formulae to calculate the >> Colpitts capacitive divider ratio, and the minimum safe base coupling >> capacitor. The CA3046 data sheet says that Cbe and Ccb are both in the >> range of 0.6pF, and the Ft is around 300MHz. So at 150MHz I only have >> 3dB of gain to play with, so that Cbe means I need at least a couple of >> pF to drive the base, and the divider ratio has to give reasonable >> drive. If anyone could suggest better "rule of thumb" for calculating >> these things from Ft and Cin, I'd appreciate it. >> >> Clifford Heath >> -- Cut Here for OscProblem.asc -- >> Version 4 >> SHEET 1 2160 1200 >> WIRE 304 -336 192 -336 >> WIRE 752 -336 304 -336 >> WIRE 192 -288 192 -336 >> WIRE 192 -176 192 -208 >> WIRE 192 -176 -64 -176 >> WIRE 432 -176 192 -176 >> WIRE 528 -176 432 -176 >> WIRE 192 -128 192 -176 >> WIRE 752 -96 752 -336 >> WIRE 304 -48 304 -336 >> WIRE 432 -48 432 -176 >> WIRE -48 0 -64 0 >> WIRE 32 0 -48 0 >> WIRE 96 0 32 0 >> WIRE 192 0 192 -48 >> WIRE 192 0 160 0 >> WIRE 240 0 192 0 >> WIRE 32 64 32 0 >> WIRE 528 64 528 -176 >> WIRE -48 144 -48 0 >> WIRE 432 160 432 32 >> WIRE 32 208 32 128 >> WIRE 304 208 304 48 >> WIRE 304 208 32 208 >> WIRE 368 208 304 208 >> WIRE 192 256 192 0 >> WIRE 304 256 304 208 >> WIRE 32 272 32 208 >> WIRE -48 384 -48 224 >> WIRE 32 384 32 336 >> WIRE 32 384 -48 384 >> WIRE 192 384 192 336 >> WIRE 192 384 32 384 >> WIRE 304 384 304 336 >> WIRE 304 384 192 384 >> WIRE 432 384 432 256 >> WIRE 432 384 304 384 >> WIRE 528 384 528 128 >> WIRE 528 384 432 384 >> WIRE 752 384 752 -16 >> WIRE 752 384 528 384 >> WIRE 752 400 752 384 >> FLAG 752 400 0 >> FLAG -64 0 Vosc >> IOPIN -64 0 Out >> FLAG -64 -176 Vbias >> IOPIN -64 -176 Out >> SYMBOL voltage 752 -112 R0 >> WINDOW 123 24 126 Left 2 >> WINDOW 39 24 111 Left 2 >> SYMATTR InstName V1 >> SYMATTR Value 3.2v >> SYMBOL cap 16 64 R0 >> SYMATTR InstName C1 >> SYMATTR Value {C1} >> SYMBOL cap 16 272 R0 >> SYMATTR InstName C2 >> SYMATTR Value {C2} >> SYMBOL ind -64 128 R0 >> SYMATTR InstName L3 >> SYMATTR Value {L1} >> SYMBOL npn 240 -48 R0 >> SYMATTR InstName Q1 >> SYMATTR Value CA3046 >> SYMBOL res 176 -144 R0 >> SYMATTR InstName R4 >> SYMATTR Value 100k >> SYMBOL npn 368 160 R0 >> SYMATTR InstName Q2 >> SYMATTR Value CA3046 >> SYMBOL res 176 -304 R0 >> SYMATTR InstName R2 >> SYMATTR Value 47k >> SYMBOL cap 512 64 R0 >> SYMATTR InstName C4 >> SYMATTR Value {100/(F0*10k)} >> SYMBOL res 288 240 R0 >> SYMATTR InstName R6 >> SYMATTR Value 2.2k >> SYMBOL cap 160 -16 R90 >> WINDOW 0 0 32 VBottom 2 >> WINDOW 3 32 32 VTop 2 >> SYMATTR InstName C3 >> SYMATTR Value {C3} >> SYMBOL res 176 240 R0 >> SYMATTR InstName R3 >> SYMATTR Value 100k >> SYMBOL res 416 -64 R0 >> SYMATTR InstName R8 >> SYMATTR Value 10k >> TEXT 864 -424 Left 2 !.tran 0 {10u + (2000/F0)} 0 {1/(F0*50)} >> TEXT -96 -384 Left 2 !.param F0=30Meg >> TEXT -96 440 Left 2 !; Calculate main tank components from F0, ZT and >> stray capacitances:\n.param CSTRAY1=1.7p CSTRAY2=0.8pF\n.param >> L1={ZT/(2*PI*F0)} DIV=17 C2={1/(2*PI*F0*(ZT/DIV)) - CSTRAY1} >> CT={(1/(2*PI*F0*ZT)) - CSTRAY2} C1={1/((1/CT) - (1/C2))}\n.MEASURE L1_ >> PARAM L1\n.MEASURE C1_ PARAM C1\n.MEASURE C2_ PARAM C2 >> TEXT 872 232 Left 2 !.param ZCouple1=5k C3={max(1/(2*PI*F0*ZCouple1), >> 1pF)}\n.MEASURE C3_ PARAM C3 >> TEXT -96 -344 Left 2 !.param ZT=350 >> TEXT 872 144 Left 2 !.MEASURE C4_ PARAM {100/(F0*10k)} >> TEXT 864 -320 Left 2 !*COPYRIGHT &#2013266089; 1997 INTERSIL CORPORATION\n*ALL >> RIGHTS RESERVED\n*\n*CA3046 PSpice MODEL\n*REV: 2-24-97\n** ----- BJT >> MODEL -----\n*\n.model CA3046 NPN\n+ (IS = 10.0E-15 XTI=3.000E+00 >> EG=1.110E+00 VAF=1.00E+02\n+ VAR=1.000E+02 BF=145.7E+00 ISE=114.286E-15 >> NE=1.480E+00\n+ IKF=46.700E-03 XTB=0.000E+00 BR=.1000E+00 >> ISC=10.005E-15\n+ NC=2.000E+00 IKR=10.00E-03 RC=10.000E+00 >> CJC=991.71E-15\n+ MJC=0.333E-00 VJC=0.7500E-00 FC=5.000E-01 >> CJE=1.02E-12\n+ MJE=.336E-00 VJE=0.750E-00 TR=10.000E-09 >> TF=277.01E-12\n+ ITF=1.750E-00 XTF=309.38E+00 VTF=16.37E+00 >> PTF=0.000E+00\n+ RE=0.0E+00 RB=0.00E+00 >> TEXT -96 -424 Left 2 ;Change these parameters to vary the operating >> frequency and tank impedance >> TEXT 696 560 Left 2 ;This model was initially designed and built (works >> fine) at 3.58 MHz.\nWhen run at any frequency up to 150MHz, it still >> simulates fine.\nHowever, the physical circuit only reaches half >> amplitude at 12MHz,\nand doesn't start at all much above that, even when >> larger C3 and\nsmaller C1/C2 ratio is used (to overcome lower gain, >> input capacitance;\n1pf for C3 cannot ever be enough with Cbe=0.5pF >> Ft=300MHz).\nI'd really like to know why. Is my CA3046 model wrong? > > ...Jim Thompson >
On 04/04/14 14:33, RobertMacy wrote:
> On Thu, 03 Apr 2014 20:03:58 -0700, Clifford Heath <no.spam@please.net> > wrote:
> 1. SAME model for CA3046 is that in a package, or as a chip?
I'm using LM3046, which is the replacement for the CA3046 - all five transistors are meant to be the same (though one - the one I use for AGC) has its emitter joined to the substrate. I don't know how its parameters differ, but I'm sure its Ft and gain are not worse than the CA3046. Note that the circuit implemented at 3.6MHz behaves almost exactly as it simulates. It's at higher frequencies that things go awry.
> 2. L3 is a 'perfect' inductor??
Well, no, obviously. It's a T37-6 toroid up to 12MHz, air-core on 8mm or 6mm for my experiments at 30Mhz, 50MHz and 150MHz.
> any photos? of the circuitry? Don't wish to cast aspersions, but layout > above 10 MHz starts to become important. up there a short connection is > no longer a connection,
Yes, I'm aware of that. I've routed it single-sided on a copper rear plane, using 0805 components throughout. Within that constraint, I'll be very surprised if you can find a way to substantially improve it... but here are the snapshots of this part of the circuit (from Eagle): <http://cjh.polyplex.org/electronics/fox/Oscillator.brd.png> <http://cjh.polyplex.org/electronics/fox/Oscillator.sch.png> The other three transistors are n/c in this test board, but in the 3.6MHz version they're a phase splitter and push-pull output driver. unless it's wider than long, it's an inductor.
> resistors have inductance, caps have inductance, everything has stray > cap to gnd, and the effect of phase shift along the circuitry ??? I > know, but a few degrees is a few degrees.
Yes. But when you run the model I posted at 150MHz, it simulates just fine, even though the capacitance ratio and base coupling capacitor clearly show that it should not have enough gain to start. Even at 30MHz, and even after playing with a range of different values, the real thing still doesn't start. At 12MHz it only reaches 50mV p-p, not the 100mV that the AGC limits it to. Clearly a long way from what the sim is saying, and I need to know why. But first, I'd like a better guess (or I know, math...) at plausible values for these parts to make it oscillate at 30MHz, before I try 50 or 150. BTW, if you're the guy working at Linear on this sim, props to you. I downloaded the Mac version recently, and though it is extraordinarily strange for a Mac app, it's so nice not to have Windows running under Wine. Clifford Heath.
> Example of 'macroscopic high frequency modeling: modeled an EMC > Conducted Test [made models for the LISN], complete with AC chord > models, gnded sheet metal planes, etc. > SOLAR ELECTRONICS LISN 8012-50-R-24-BNC > RHODE & SCHWARZ LISN ESH2-Z5 > in order to explain, design SMPS line filtering and found out that above > 10MHz, everything just kind of falls apart. go from accurate to errors > worse than 2 to 3 dB, which is still better than a guess, but did not > feel solid enough, just too 'squishy' for my taste. Once problem solved > could not justify going back to find out what was not quite right. I > always thought it just parasitics that aren't represented well. > > >
Could you try inserting a few k-ohm resistor
in series with Q2 base on your real-world circuit,
just to reduce loading on the tuned circuit? Or
even simpler just try lifting the base connection
on Q2 and see if it will start oscillation at the
higher frequencies?

piglet
On 04/04/14 20:58, piglet wrote:
> Could you try inserting a few k-ohm resistor > in series with Q2 base on your real-world circuit, > just to reduce loading on the tuned circuit? Or > even simpler just try lifting the base connection > on Q2 and see if it will start oscillation at the > higher frequencies?
Yes, there's a trace beside the square via I could cut. (The osc transistor is top-right, AGC top-left) The C3 base coupling cap is already only a very weak link from the tank though... perhaps too weak. The components shown on the Eagle fragments are for 3.6MHz; 10pF is worth over 4k at that frequency (and works fine). I've dropped it to a variety of much smaller values for higher frequency operation to let that tank run free.
On 04/04/2014 14:03, Clifford Heath wrote:
> Folk, > > Thanks to some good help here in the past, I have a nice clean > oscillator (for my new fox transmitters), but I'm having trouble with > the LTSpice simulation at higher frequencies. I'm assuming that the > Intersil Spice model for the CA3046 is bad, and I know JT has a better one. > > Anyhow, I have two questions about the attached LTSpice schematic. > > 1) When I set it to 30MHz, LTSpice says the oscillator will start nicely > (even up to 150MHz in fact). Now I know that the (calculated) Colpitts > capacitance ratio is bad, as is the base capacitor, but with the > physical circuit built in a tight layout in SMD and a range of more > sensible capacitances substituted, I can't get it to oscillate above > about 12MHz. Why does it not want to run in real life, when Spice says > it should? Can someone provide me a better CA3046 model please, or say > what else might be going on?
[snip] I would suggest estimating the length of some of the more critical physical wires on the hardware version, and putting appropriate parasitics back into the simulation model. Particularly in series with the emitter of transistors, it can affect gain at RF. I would suggest modelling the emitter pin and leadframe and the wiring as 1nH per millimetre of length, as a first guess, plus another nanohenry for the bondwire (unless it is already in your transistor model). Whilst this probably isn't the cause, it might start to expain something. Another thing that may be worth trying, though it isn't usually necessary until you get to GHz frequencies: The capacitance across unwanted junctions on chips (perhaps collector to substrate in your case) can be lossy. If you model it as a pure capacitor then you can simulate better Q or gain or noise figure than reality. Of course if you add an infinite value resistor in series with the parasitic capacitances then that also gives zero losses and artificially good performance. There is some intermediate value of resistance to put in the model in series with the parasitic capacitance, between zero and infinity Ohms, that will result in the worst possible losses. There is some other value of series resistance that is the best model of reality. Often the most representative value is close to the worst case losses value, except when you don't want things to oscillate in which case it is very different. It is important to put some losses in the model of your inductor also, as another poster mentioned. Beware of metal very close to the inductor. I sometimes like to put inductors in screened cans, but all metalwork should ideally be spaced away from the turns of the inductor by at least the inductor diameter, to avoid causing more losses. Hopefully you have some low-ESR decoupling (e.g. 100n chip ceramic) capacitor(s) across your supply right near the oscillator. Otherwise the impedance of the supply wiring might stop things from working, in a way that would not be simulated. I suggest you get one of those label machines, and affix a label to your prototype that says "unconditionally stable amplifier". It will surely oscillate then. Are you able to verify the DC collector current and Vce of your not-oscillating transistor? I would check that the collector current is close to (but slightly lower than) the value that gives the peak Ft value. (I have been warned that above the current that gives peak Ft, models are often not very good and/or device performance is more unpredictable, and to therefore stay somewhat below that current if good Ft is important). Also make sure the Vce is well over a volt, and more if the transistor has a poorly contacted collector with lots of distributed resistance (which could cause parts of the device to saturate before other parts, and wouldn't usually be modelled). For oscillators, I like to pick a transistor with an Ft that is about 10 times higher than the highest desired oscillation frequency. Something like an old BFY90, in your case, or one of the many surface mount RF transistors that you can get these days. Actually I prefer FET LC oscillators but none of this is really relevant to the simulation problem. Chris
On 04/04/2014 10:44 AM, Clifford Heath wrote:
> On 04/04/14 14:33, RobertMacy wrote: >> On Thu, 03 Apr 2014 20:03:58 -0700, Clifford Heath <no.spam@please.net> >> wrote: > >> 1. SAME model for CA3046 is that in a package, or as a chip? > > I'm using LM3046, which is the replacement for the CA3046 - all five > transistors are meant to be the same (though one - the one I use for > AGC) has its emitter joined to the substrate. I don't know how its > parameters differ, but I'm sure its Ft and gain are not worse than the > CA3046. > > Note that the circuit implemented at 3.6MHz behaves almost exactly as it > simulates. It's at higher frequencies that things go awry. > >> 2. L3 is a 'perfect' inductor?? > > Well, no, obviously. It's a T37-6 toroid up to 12MHz, air-core on 8mm or > 6mm for my experiments at 30Mhz, 50MHz and 150MHz. > >> any photos? of the circuitry? Don't wish to cast aspersions, but layout >> above 10 MHz starts to become important. up there a short connection is >> no longer a connection, > > Yes, I'm aware of that. I've routed it single-sided on a copper rear > plane, using 0805 components throughout. Within that constraint, I'll be > very surprised if you can find a way to substantially improve it... but > here are the snapshots of this part of the circuit (from Eagle): > <http://cjh.polyplex.org/electronics/fox/Oscillator.brd.png> > <http://cjh.polyplex.org/electronics/fox/Oscillator.sch.png>
A solid copper plane introduces a significant amount of capacitance from each node to ground. You can simulate this adding parasitic capacitances here and there. Furthermore, you have to make sure that the gnd points on the top layer are really gnd. At higher frequencies this usefully means a lot of vias to gnd. It could be that some node that should be gnd has a long path to the bottom plane. I can't tell from your pictures. Pere <snipped rest of post>
On 04/04/2014 19:44, Clifford Heath wrote:
[snip]
>> any photos? of the circuitry? Don't wish to cast aspersions, but layout >> above 10 MHz starts to become important. up there a short connection is >> no longer a connection, > > Yes, I'm aware of that. I've routed it single-sided on a copper rear > plane, using 0805 components throughout. Within that constraint, I'll be > very surprised if you can find a way to substantially improve it... but > here are the snapshots of this part of the circuit (from Eagle): > <http://cjh.polyplex.org/electronics/fox/Oscillator.brd.png> > <http://cjh.polyplex.org/electronics/fox/Oscillator.sch.png>
[snip] Thanks for posting the diagrams. Some loss in the inductor would certainly be more realistic. I hope the inductor is not sitting right on the PCB unless you make a big hole in the ground plane under the inductor, at least 2x the diameter of the inductor. Otherwise it is going to reduce the Q like a shorted turn. As long the hole is big enough so that the ground plane is spaced far enough from the turns, it is no longer a problem and actually helps with shielding the inductor. I note that you are taking the output via C9 from the top of the tank, which is a very sensitive node. I hope it is going to something with really low loss, or that could be a cause for reducing the Q and tendency to oscillate. I would suggest taking the output from some low-impedance node, such as a tap on the inductor, or the top of R6 or something like that. Also not related to the present problem, I think you could probably get rid of C6 and R7 - the DC voltage on each side of C6 is the same, assuming the varactors stay reverse biased. Chris